1 /* arch/arm/mach-s5p6440/gpio.c
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5P6440 - GPIOlib support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/irq.h>
16 #include <linux/gpio.h>
19 #include <mach/regs-gpio.h>
21 #include <plat/gpio-core.h>
22 #include <plat/gpio-cfg.h>
23 #include <plat/gpio-cfg-helpers.h>
27 * Bank GPIOs Style SlpCon ExtInt Group
36 * N 16 2Bit No IRQ_EINT
40 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
41 * [2] BANK has two control registers, GPxCON0 and GPxCON1
44 static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
47 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
48 void __iomem *base = ourchip->base;
49 void __iomem *regcon = base;
69 s3c_gpio_lock(ourchip, flags);
71 con = __raw_readl(regcon);
72 con &= ~(0xf << con_4bit_shift(offset));
73 __raw_writel(con, regcon);
75 s3c_gpio_unlock(ourchip, flags);
80 static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
81 unsigned int offset, int value)
83 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
84 void __iomem *base = ourchip->base;
85 void __iomem *regcon = base;
89 unsigned con_offset = offset;
107 s3c_gpio_lock(ourchip, flags);
109 con = __raw_readl(regcon);
110 con &= ~(0xf << con_4bit_shift(con_offset));
111 con |= 0x1 << con_4bit_shift(con_offset);
113 dat = __raw_readl(base + GPIODAT_OFF);
117 dat &= ~(1 << offset);
119 __raw_writel(con, regcon);
120 __raw_writel(dat, base + GPIODAT_OFF);
122 s3c_gpio_unlock(ourchip, flags);
127 int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
128 unsigned int off, unsigned int cfg)
130 void __iomem *reg = chip->base;
142 shift = (off & 7) * 4;
146 shift = ((off + 1) & 7) * 4;
149 shift = ((off + 1) & 7) * 4;
153 if (s3c_gpio_is_cfg_special(cfg)) {
158 s3c_gpio_lock(chip, flags);
160 con = __raw_readl(reg);
161 con &= ~(0xf << shift);
163 __raw_writel(con, reg);
165 s3c_gpio_unlock(chip, flags);
170 static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
177 .set_config = s5p6440_gpio_setcfg_4bit_rbank,
180 .set_config = s3c_gpio_setcfg_s3c24xx,
181 .get_config = s3c_gpio_getcfg_s3c24xx,
184 .set_config = s3c_gpio_setcfg_s3c24xx,
185 .get_config = s3c_gpio_getcfg_s3c24xx,
188 .set_config = s3c_gpio_setcfg_s3c24xx,
189 .get_config = s3c_gpio_getcfg_s3c24xx,
193 static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
195 .base = S5P6440_GPA_BASE,
196 .config = &s5p6440_gpio_cfgs[1],
198 .base = S5P6440_GPA(0),
199 .ngpio = S5P6440_GPIO_A_NR,
203 .base = S5P6440_GPB_BASE,
204 .config = &s5p6440_gpio_cfgs[1],
206 .base = S5P6440_GPB(0),
207 .ngpio = S5P6440_GPIO_B_NR,
211 .base = S5P6440_GPC_BASE,
212 .config = &s5p6440_gpio_cfgs[1],
214 .base = S5P6440_GPC(0),
215 .ngpio = S5P6440_GPIO_C_NR,
219 .base = S5P6440_GPG_BASE,
220 .config = &s5p6440_gpio_cfgs[1],
222 .base = S5P6440_GPG(0),
223 .ngpio = S5P6440_GPIO_G_NR,
229 static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
231 .base = S5P6440_GPH_BASE + 0x4,
232 .config = &s5p6440_gpio_cfgs[1],
234 .base = S5P6440_GPH(0),
235 .ngpio = S5P6440_GPIO_H_NR,
241 static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
243 .base = S5P6440_GPR_BASE + 0x4,
244 .config = &s5p6440_gpio_cfgs[2],
246 .base = S5P6440_GPR(0),
247 .ngpio = S5P6440_GPIO_R_NR,
253 static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
255 .base = S5P6440_GPF_BASE,
256 .config = &s5p6440_gpio_cfgs[5],
258 .base = S5P6440_GPF(0),
259 .ngpio = S5P6440_GPIO_F_NR,
263 .base = S5P6440_GPI_BASE,
264 .config = &s5p6440_gpio_cfgs[3],
266 .base = S5P6440_GPI(0),
267 .ngpio = S5P6440_GPIO_I_NR,
271 .base = S5P6440_GPJ_BASE,
272 .config = &s5p6440_gpio_cfgs[3],
274 .base = S5P6440_GPJ(0),
275 .ngpio = S5P6440_GPIO_J_NR,
279 .base = S5P6440_GPN_BASE,
280 .config = &s5p6440_gpio_cfgs[4],
282 .base = S5P6440_GPN(0),
283 .ngpio = S5P6440_GPIO_N_NR,
287 .base = S5P6440_GPP_BASE,
288 .config = &s5p6440_gpio_cfgs[5],
290 .base = S5P6440_GPP(0),
291 .ngpio = S5P6440_GPIO_P_NR,
297 void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
299 for (; nr_chips > 0; nr_chips--, chipcfg++) {
300 if (!chipcfg->set_config)
301 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
302 if (!chipcfg->get_config)
303 chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
304 if (!chipcfg->set_pull)
305 chipcfg->set_pull = s3c_gpio_setpull_updown;
306 if (!chipcfg->get_pull)
307 chipcfg->get_pull = s3c_gpio_getpull_updown;
311 static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
314 for (; nr_chips > 0; nr_chips--, chip++) {
315 chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input;
316 chip->chip.direction_output =
317 s5p6440_gpiolib_rbank_4bit2_output;
318 s3c_gpiolib_add(chip);
322 static int __init s5p6440_gpiolib_init(void)
324 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
325 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
327 s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs,
328 ARRAY_SIZE(s5p6440_gpio_cfgs));
330 for (; nr_chips > 0; nr_chips--, chips++)
331 s3c_gpiolib_add(chips);
333 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
334 ARRAY_SIZE(s5p6440_gpio_4bit));
336 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
337 ARRAY_SIZE(s5p6440_gpio_4bit2));
339 s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2,
340 ARRAY_SIZE(gpio_rbank_4bit2));
344 arch_initcall(s5p6440_gpiolib_init);