1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P6440 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
25 #include <mach/regs-clock.h>
26 #include <mach/s5p64x0-clock.h>
28 #include <plat/cpu-freq.h>
29 #include <plat/clock.h>
32 #include <plat/s5p-clock.h>
33 #include <plat/clock-clksrc.h>
37 static u32 epll_div[][5] = {
38 { 36000000, 0, 48, 1, 4 },
39 { 48000000, 0, 32, 1, 3 },
40 { 60000000, 0, 40, 1, 3 },
41 { 72000000, 0, 48, 1, 3 },
42 { 84000000, 0, 28, 1, 2 },
43 { 96000000, 0, 32, 1, 2 },
44 { 32768000, 45264, 43, 1, 4 },
45 { 45158000, 6903, 30, 1, 3 },
46 { 49152000, 50332, 32, 1, 3 },
47 { 67738000, 10398, 45, 1, 3 },
48 { 73728000, 9961, 49, 1, 3 }
51 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
53 unsigned int epll_con, epll_con_k;
56 if (clk->rate == rate) /* Return if nothing changed */
59 epll_con = __raw_readl(S5P64X0_EPLL_CON);
60 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
62 epll_con_k &= ~(PLL90XX_KDIV_MASK);
63 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
65 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
66 if (epll_div[i][0] == rate) {
67 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
68 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
69 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
70 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
75 if (i == ARRAY_SIZE(epll_div)) {
76 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
80 __raw_writel(epll_con, S5P64X0_EPLL_CON);
81 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
83 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
91 static struct clk_ops s5p6440_epll_ops = {
92 .get_rate = s5p_epll_get_rate,
93 .set_rate = s5p6440_epll_set_rate,
96 static struct clksrc_clk clk_hclk = {
99 .parent = &clk_armclk.clk,
101 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
104 static struct clksrc_clk clk_pclk = {
107 .parent = &clk_hclk.clk,
109 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
111 static struct clksrc_clk clk_hclk_low = {
113 .name = "clk_hclk_low",
115 .sources = &clkset_hclk_low,
116 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
117 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
120 static struct clksrc_clk clk_pclk_low = {
122 .name = "clk_pclk_low",
123 .parent = &clk_hclk_low.clk,
125 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
129 * The following clocks will be disabled during clock initialization. It is
130 * recommended to keep the following clocks disabled until the driver requests
131 * for enabling the clock.
133 static struct clk init_clocks_off[] = {
136 .parent = &clk_hclk.clk,
137 .enable = s5p64x0_mem_ctrl,
141 .parent = &clk_hclk_low.clk,
142 .enable = s5p64x0_hclk0_ctrl,
146 .parent = &clk_hclk.clk,
147 .enable = s5p64x0_hclk0_ctrl,
151 .devname = "dma-pl330",
152 .parent = &clk_hclk_low.clk,
153 .enable = s5p64x0_hclk0_ctrl,
154 .ctrlbit = (1 << 12),
157 .devname = "s3c-sdhci.0",
158 .parent = &clk_hclk_low.clk,
159 .enable = s5p64x0_hclk0_ctrl,
160 .ctrlbit = (1 << 17),
163 .devname = "s3c-sdhci.1",
164 .parent = &clk_hclk_low.clk,
165 .enable = s5p64x0_hclk0_ctrl,
166 .ctrlbit = (1 << 18),
169 .devname = "s3c-sdhci.2",
170 .parent = &clk_hclk_low.clk,
171 .enable = s5p64x0_hclk0_ctrl,
172 .ctrlbit = (1 << 19),
175 .parent = &clk_hclk_low.clk,
176 .enable = s5p64x0_hclk0_ctrl,
180 .parent = &clk_hclk.clk,
181 .enable = s5p64x0_hclk0_ctrl,
182 .ctrlbit = (1 << 25),
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk1_ctrl,
189 .name = "hclk_fimgvg",
190 .parent = &clk_hclk.clk,
191 .enable = s5p64x0_hclk1_ctrl,
195 .parent = &clk_hclk_low.clk,
196 .enable = s5p64x0_hclk1_ctrl,
200 .parent = &clk_pclk_low.clk,
201 .enable = s5p64x0_pclk_ctrl,
205 .parent = &clk_pclk_low.clk,
206 .enable = s5p64x0_pclk_ctrl,
210 .parent = &clk_pclk_low.clk,
211 .enable = s5p64x0_pclk_ctrl,
215 .parent = &clk_pclk_low.clk,
216 .enable = s5p64x0_pclk_ctrl,
220 .parent = &clk_pclk_low.clk,
221 .enable = s5p64x0_pclk_ctrl,
222 .ctrlbit = (1 << 12),
225 .parent = &clk_pclk_low.clk,
226 .enable = s5p64x0_pclk_ctrl,
227 .ctrlbit = (1 << 17),
230 .devname = "s3c64xx-spi.0",
231 .parent = &clk_pclk_low.clk,
232 .enable = s5p64x0_pclk_ctrl,
233 .ctrlbit = (1 << 21),
236 .devname = "s3c64xx-spi.1",
237 .parent = &clk_pclk_low.clk,
238 .enable = s5p64x0_pclk_ctrl,
239 .ctrlbit = (1 << 22),
242 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 25),
247 .devname = "samsung-i2s.0",
248 .parent = &clk_pclk_low.clk,
249 .enable = s5p64x0_pclk_ctrl,
250 .ctrlbit = (1 << 26),
253 .parent = &clk_pclk_low.clk,
254 .enable = s5p64x0_pclk_ctrl,
255 .ctrlbit = (1 << 28),
258 .parent = &clk_pclk.clk,
259 .enable = s5p64x0_pclk_ctrl,
260 .ctrlbit = (1 << 29),
263 .parent = &clk_pclk.clk,
264 .enable = s5p64x0_pclk_ctrl,
265 .ctrlbit = (1 << 30),
267 .name = "pclk_fimgvg",
268 .parent = &clk_pclk.clk,
269 .enable = s5p64x0_pclk_ctrl,
270 .ctrlbit = (1 << 31),
272 .name = "sclk_spi_48",
273 .devname = "s3c64xx-spi.0",
275 .enable = s5p64x0_sclk_ctrl,
276 .ctrlbit = (1 << 22),
278 .name = "sclk_spi_48",
279 .devname = "s3c64xx-spi.1",
281 .enable = s5p64x0_sclk_ctrl,
282 .ctrlbit = (1 << 23),
285 .devname = "s3c-sdhci.0",
287 .enable = s5p64x0_sclk_ctrl,
288 .ctrlbit = (1 << 27),
291 .devname = "s3c-sdhci.1",
293 .enable = s5p64x0_sclk_ctrl,
294 .ctrlbit = (1 << 28),
297 .devname = "s3c-sdhci.2",
299 .enable = s5p64x0_sclk_ctrl,
300 .ctrlbit = (1 << 29),
305 * The following clocks will be enabled during clock initialization.
307 static struct clk init_clocks[] = {
310 .parent = &clk_hclk.clk,
311 .enable = s5p64x0_hclk0_ctrl,
315 .parent = &clk_hclk.clk,
316 .enable = s5p64x0_hclk0_ctrl,
317 .ctrlbit = (1 << 21),
320 .devname = "s3c6400-uart.0",
321 .parent = &clk_pclk_low.clk,
322 .enable = s5p64x0_pclk_ctrl,
326 .devname = "s3c6400-uart.1",
327 .parent = &clk_pclk_low.clk,
328 .enable = s5p64x0_pclk_ctrl,
332 .devname = "s3c6400-uart.2",
333 .parent = &clk_pclk_low.clk,
334 .enable = s5p64x0_pclk_ctrl,
338 .devname = "s3c6400-uart.3",
339 .parent = &clk_pclk_low.clk,
340 .enable = s5p64x0_pclk_ctrl,
344 .parent = &clk_pclk_low.clk,
345 .enable = s5p64x0_pclk_ctrl,
346 .ctrlbit = (1 << 18),
350 static struct clk clk_iis_cd_v40 = {
351 .name = "iis_cdclk_v40",
354 static struct clk clk_pcm_cd = {
358 static struct clk *clkset_group1_list[] = {
364 static struct clksrc_sources clkset_group1 = {
365 .sources = clkset_group1_list,
366 .nr_sources = ARRAY_SIZE(clkset_group1_list),
369 static struct clk *clkset_uart_list[] = {
374 static struct clksrc_sources clkset_uart = {
375 .sources = clkset_uart_list,
376 .nr_sources = ARRAY_SIZE(clkset_uart_list),
379 static struct clk *clkset_audio_list[] = {
387 static struct clksrc_sources clkset_audio = {
388 .sources = clkset_audio_list,
389 .nr_sources = ARRAY_SIZE(clkset_audio_list),
392 static struct clksrc_clk clksrcs[] = {
396 .devname = "s3c-sdhci.0",
397 .ctrlbit = (1 << 24),
398 .enable = s5p64x0_sclk_ctrl,
400 .sources = &clkset_group1,
401 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
402 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
406 .devname = "s3c-sdhci.1",
407 .ctrlbit = (1 << 25),
408 .enable = s5p64x0_sclk_ctrl,
410 .sources = &clkset_group1,
411 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
412 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
416 .devname = "s3c-sdhci.2",
417 .ctrlbit = (1 << 26),
418 .enable = s5p64x0_sclk_ctrl,
420 .sources = &clkset_group1,
421 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
422 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
427 .enable = s5p64x0_sclk_ctrl,
429 .sources = &clkset_uart,
430 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
431 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
435 .devname = "s3c64xx-spi.0",
436 .ctrlbit = (1 << 20),
437 .enable = s5p64x0_sclk_ctrl,
439 .sources = &clkset_group1,
440 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
441 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
445 .devname = "s3c64xx-spi.1",
446 .ctrlbit = (1 << 21),
447 .enable = s5p64x0_sclk_ctrl,
449 .sources = &clkset_group1,
450 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
451 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
455 .ctrlbit = (1 << 10),
456 .enable = s5p64x0_sclk_ctrl,
458 .sources = &clkset_group1,
459 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
460 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
463 .name = "sclk_dispcon",
465 .enable = s5p64x0_sclk1_ctrl,
467 .sources = &clkset_group1,
468 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
469 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
472 .name = "sclk_fimgvg",
474 .enable = s5p64x0_sclk1_ctrl,
476 .sources = &clkset_group1,
477 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
478 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
481 .name = "sclk_audio2",
482 .ctrlbit = (1 << 11),
483 .enable = s5p64x0_sclk_ctrl,
485 .sources = &clkset_audio,
486 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
487 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
491 /* Clock initialization code */
492 static struct clksrc_clk *sysclks[] = {
504 static struct clk dummy_apb_pclk = {
509 void __init_or_cpufreq s5p6440_setup_clocks(void)
511 struct clk *xtal_clk;
516 unsigned long hclk_low;
518 unsigned long pclk_low;
525 /* Set S5P6440 functions for clk_fout_epll */
527 clk_fout_epll.enable = s5p_epll_enable;
528 clk_fout_epll.ops = &s5p6440_epll_ops;
530 clk_48m.enable = s5p64x0_clk48m_ctrl;
532 xtal_clk = clk_get(NULL, "ext_xtal");
533 BUG_ON(IS_ERR(xtal_clk));
535 xtal = clk_get_rate(xtal_clk);
538 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
539 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
540 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
541 __raw_readl(S5P64X0_EPLL_CON_K));
543 clk_fout_apll.rate = apll;
544 clk_fout_mpll.rate = mpll;
545 clk_fout_epll.rate = epll;
547 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
549 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
551 fclk = clk_get_rate(&clk_armclk.clk);
552 hclk = clk_get_rate(&clk_hclk.clk);
553 pclk = clk_get_rate(&clk_pclk.clk);
554 hclk_low = clk_get_rate(&clk_hclk_low.clk);
555 pclk_low = clk_get_rate(&clk_pclk_low.clk);
557 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
558 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
559 print_mhz(hclk), print_mhz(hclk_low),
560 print_mhz(pclk), print_mhz(pclk_low));
566 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
567 s3c_set_clksrc(&clksrcs[ptr], true);
570 static struct clk *clks[] __initdata = {
576 void __init s5p6440_register_clocks(void)
580 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
582 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
583 s3c_register_clksrc(sysclks[ptr], 1);
585 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
586 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
588 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
589 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
591 s3c24xx_register_clock(&dummy_apb_pclk);