1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P6440 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
25 #include <mach/regs-clock.h>
26 #include <mach/s5p64x0-clock.h>
28 #include <plat/cpu-freq.h>
29 #include <plat/clock.h>
32 #include <plat/s5p-clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/s5p6440.h>
36 static u32 epll_div[][5] = {
37 { 36000000, 0, 48, 1, 4 },
38 { 48000000, 0, 32, 1, 3 },
39 { 60000000, 0, 40, 1, 3 },
40 { 72000000, 0, 48, 1, 3 },
41 { 84000000, 0, 28, 1, 2 },
42 { 96000000, 0, 32, 1, 2 },
43 { 32768000, 45264, 43, 1, 4 },
44 { 45158000, 6903, 30, 1, 3 },
45 { 49152000, 50332, 32, 1, 3 },
46 { 67738000, 10398, 45, 1, 3 },
47 { 73728000, 9961, 49, 1, 3 }
50 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
52 unsigned int epll_con, epll_con_k;
55 if (clk->rate == rate) /* Return if nothing changed */
58 epll_con = __raw_readl(S5P64X0_EPLL_CON);
59 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
61 epll_con_k &= ~(PLL90XX_KDIV_MASK);
62 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
64 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
65 if (epll_div[i][0] == rate) {
66 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
67 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
68 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
69 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
74 if (i == ARRAY_SIZE(epll_div)) {
75 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
79 __raw_writel(epll_con, S5P64X0_EPLL_CON);
80 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
87 static struct clk_ops s5p6440_epll_ops = {
88 .get_rate = s5p64x0_epll_get_rate,
89 .set_rate = s5p6440_epll_set_rate,
92 static struct clksrc_clk clk_hclk = {
96 .parent = &clk_armclk.clk,
98 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
101 static struct clksrc_clk clk_pclk = {
105 .parent = &clk_hclk.clk,
107 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
109 static struct clksrc_clk clk_hclk_low = {
111 .name = "clk_hclk_low",
114 .sources = &clkset_hclk_low,
115 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
116 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
119 static struct clksrc_clk clk_pclk_low = {
121 .name = "clk_pclk_low",
123 .parent = &clk_hclk_low.clk,
125 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
129 * The following clocks will be disabled during clock initialization. It is
130 * recommended to keep the following clocks disabled until the driver requests
131 * for enabling the clock.
133 static struct clk init_clocks_disable[] = {
137 .parent = &clk_hclk.clk,
138 .enable = s5p64x0_mem_ctrl,
143 .parent = &clk_hclk_low.clk,
144 .enable = s5p64x0_hclk0_ctrl,
149 .parent = &clk_hclk.clk,
150 .enable = s5p64x0_hclk0_ctrl,
155 .parent = &clk_hclk_low.clk,
156 .enable = s5p64x0_hclk0_ctrl,
157 .ctrlbit = (1 << 17),
161 .parent = &clk_hclk_low.clk,
162 .enable = s5p64x0_hclk0_ctrl,
163 .ctrlbit = (1 << 18),
167 .parent = &clk_hclk_low.clk,
168 .enable = s5p64x0_hclk0_ctrl,
169 .ctrlbit = (1 << 19),
173 .parent = &clk_hclk_low.clk,
174 .enable = s5p64x0_hclk0_ctrl,
179 .parent = &clk_hclk.clk,
180 .enable = s5p64x0_hclk0_ctrl,
181 .ctrlbit = (1 << 25),
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk1_ctrl,
189 .name = "hclk_fimgvg",
191 .parent = &clk_hclk.clk,
192 .enable = s5p64x0_hclk1_ctrl,
197 .parent = &clk_hclk_low.clk,
198 .enable = s5p64x0_hclk1_ctrl,
203 .parent = &clk_pclk_low.clk,
204 .enable = s5p64x0_pclk_ctrl,
209 .parent = &clk_pclk_low.clk,
210 .enable = s5p64x0_pclk_ctrl,
215 .parent = &clk_pclk_low.clk,
216 .enable = s5p64x0_pclk_ctrl,
221 .parent = &clk_pclk_low.clk,
222 .enable = s5p64x0_pclk_ctrl,
227 .parent = &clk_pclk_low.clk,
228 .enable = s5p64x0_pclk_ctrl,
229 .ctrlbit = (1 << 12),
233 .parent = &clk_pclk_low.clk,
234 .enable = s5p64x0_pclk_ctrl,
235 .ctrlbit = (1 << 17),
239 .parent = &clk_pclk_low.clk,
240 .enable = s5p64x0_pclk_ctrl,
241 .ctrlbit = (1 << 21),
245 .parent = &clk_pclk_low.clk,
246 .enable = s5p64x0_pclk_ctrl,
247 .ctrlbit = (1 << 22),
251 .parent = &clk_pclk_low.clk,
252 .enable = s5p64x0_pclk_ctrl,
253 .ctrlbit = (1 << 25),
257 .parent = &clk_pclk_low.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 26),
263 .parent = &clk_pclk_low.clk,
264 .enable = s5p64x0_pclk_ctrl,
265 .ctrlbit = (1 << 28),
269 .parent = &clk_pclk.clk,
270 .enable = s5p64x0_pclk_ctrl,
271 .ctrlbit = (1 << 29),
275 .parent = &clk_pclk.clk,
276 .enable = s5p64x0_pclk_ctrl,
277 .ctrlbit = (1 << 30),
279 .name = "pclk_fimgvg",
281 .parent = &clk_pclk.clk,
282 .enable = s5p64x0_pclk_ctrl,
283 .ctrlbit = (1 << 31),
285 .name = "sclk_spi_48",
288 .enable = s5p64x0_sclk_ctrl,
289 .ctrlbit = (1 << 22),
291 .name = "sclk_spi_48",
294 .enable = s5p64x0_sclk_ctrl,
295 .ctrlbit = (1 << 23),
300 .enable = s5p64x0_sclk_ctrl,
301 .ctrlbit = (1 << 27),
306 .enable = s5p64x0_sclk_ctrl,
307 .ctrlbit = (1 << 28),
312 .enable = s5p64x0_sclk_ctrl,
313 .ctrlbit = (1 << 29),
318 * The following clocks will be enabled during clock initialization.
320 static struct clk init_clocks[] = {
324 .parent = &clk_hclk.clk,
325 .enable = s5p64x0_hclk0_ctrl,
330 .parent = &clk_hclk.clk,
331 .enable = s5p64x0_hclk0_ctrl,
332 .ctrlbit = (1 << 21),
336 .parent = &clk_hclk_low.clk,
337 .enable = s5p64x0_hclk0_ctrl,
338 .ctrlbit = (1 << 12),
342 .parent = &clk_pclk_low.clk,
343 .enable = s5p64x0_pclk_ctrl,
348 .parent = &clk_pclk_low.clk,
349 .enable = s5p64x0_pclk_ctrl,
354 .parent = &clk_pclk_low.clk,
355 .enable = s5p64x0_pclk_ctrl,
360 .parent = &clk_pclk_low.clk,
361 .enable = s5p64x0_pclk_ctrl,
366 .parent = &clk_pclk_low.clk,
367 .enable = s5p64x0_pclk_ctrl,
368 .ctrlbit = (1 << 18),
372 static struct clk clk_iis_cd_v40 = {
373 .name = "iis_cdclk_v40",
377 static struct clk clk_pcm_cd = {
382 static struct clk *clkset_group1_list[] = {
388 static struct clksrc_sources clkset_group1 = {
389 .sources = clkset_group1_list,
390 .nr_sources = ARRAY_SIZE(clkset_group1_list),
393 static struct clk *clkset_uart_list[] = {
398 static struct clksrc_sources clkset_uart = {
399 .sources = clkset_uart_list,
400 .nr_sources = ARRAY_SIZE(clkset_uart_list),
403 static struct clk *clkset_audio_list[] = {
411 static struct clksrc_sources clkset_audio = {
412 .sources = clkset_audio_list,
413 .nr_sources = ARRAY_SIZE(clkset_audio_list),
416 static struct clksrc_clk clksrcs[] = {
421 .ctrlbit = (1 << 24),
422 .enable = s5p64x0_sclk_ctrl,
424 .sources = &clkset_group1,
425 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
426 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
431 .ctrlbit = (1 << 25),
432 .enable = s5p64x0_sclk_ctrl,
434 .sources = &clkset_group1,
435 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
436 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
441 .ctrlbit = (1 << 26),
442 .enable = s5p64x0_sclk_ctrl,
444 .sources = &clkset_group1,
445 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
446 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
452 .enable = s5p64x0_sclk_ctrl,
454 .sources = &clkset_uart,
455 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
456 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
461 .ctrlbit = (1 << 20),
462 .enable = s5p64x0_sclk_ctrl,
464 .sources = &clkset_group1,
465 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
466 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
471 .ctrlbit = (1 << 21),
472 .enable = s5p64x0_sclk_ctrl,
474 .sources = &clkset_group1,
475 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
476 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
481 .ctrlbit = (1 << 10),
482 .enable = s5p64x0_sclk_ctrl,
484 .sources = &clkset_group1,
485 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
486 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
489 .name = "sclk_dispcon",
492 .enable = s5p64x0_sclk1_ctrl,
494 .sources = &clkset_group1,
495 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
496 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
499 .name = "sclk_fimgvg",
502 .enable = s5p64x0_sclk1_ctrl,
504 .sources = &clkset_group1,
505 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
506 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
509 .name = "sclk_audio2",
511 .ctrlbit = (1 << 11),
512 .enable = s5p64x0_sclk_ctrl,
514 .sources = &clkset_audio,
515 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
516 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
520 /* Clock initialization code */
521 static struct clksrc_clk *sysclks[] = {
533 void __init_or_cpufreq s5p6440_setup_clocks(void)
535 struct clk *xtal_clk;
540 unsigned long hclk_low;
542 unsigned long pclk_low;
549 /* Set S5P6440 functions for clk_fout_epll */
551 clk_fout_epll.enable = s5p64x0_epll_enable;
552 clk_fout_epll.ops = &s5p6440_epll_ops;
554 clk_48m.enable = s5p64x0_clk48m_ctrl;
556 xtal_clk = clk_get(NULL, "ext_xtal");
557 BUG_ON(IS_ERR(xtal_clk));
559 xtal = clk_get_rate(xtal_clk);
562 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
563 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
564 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
565 __raw_readl(S5P64X0_EPLL_CON_K));
567 clk_fout_apll.rate = apll;
568 clk_fout_mpll.rate = mpll;
569 clk_fout_epll.rate = epll;
571 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
573 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
575 fclk = clk_get_rate(&clk_armclk.clk);
576 hclk = clk_get_rate(&clk_hclk.clk);
577 pclk = clk_get_rate(&clk_pclk.clk);
578 hclk_low = clk_get_rate(&clk_hclk_low.clk);
579 pclk_low = clk_get_rate(&clk_pclk_low.clk);
581 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
582 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
583 print_mhz(hclk), print_mhz(hclk_low),
584 print_mhz(pclk), print_mhz(pclk_low));
590 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
591 s3c_set_clksrc(&clksrcs[ptr], true);
594 static struct clk *clks[] __initdata = {
600 void __init s5p6440_register_clocks(void)
606 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
608 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
609 s3c_register_clksrc(sysclks[ptr], 1);
611 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
612 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
614 clkp = init_clocks_disable;
615 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
617 ret = s3c24xx_register_clock(clkp);
619 printk(KERN_ERR "Failed to register clock %s (%d)\n",
622 (clkp->enable)(clkp, 0);