1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P6450 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
25 #include <mach/regs-clock.h>
26 #include <mach/s5p64x0-clock.h>
28 #include <plat/cpu-freq.h>
29 #include <plat/clock.h>
32 #include <plat/s5p-clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/s5p6450.h>
36 static struct clksrc_clk clk_mout_dpll = {
41 .sources = &clk_src_dpll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
45 static u32 epll_div[][5] = {
46 { 133000000, 27307, 55, 2, 2 },
47 { 100000000, 43691, 41, 2, 2 },
48 { 480000000, 0, 80, 2, 0 },
51 static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
53 unsigned int epll_con, epll_con_k;
56 if (clk->rate == rate) /* Return if nothing changed */
59 epll_con = __raw_readl(S5P64X0_EPLL_CON);
60 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
62 epll_con_k &= ~(PLL90XX_KDIV_MASK);
63 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
65 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
66 if (epll_div[i][0] == rate) {
67 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
68 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
69 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
70 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
75 if (i == ARRAY_SIZE(epll_div)) {
76 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
80 __raw_writel(epll_con, S5P64X0_EPLL_CON);
81 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
88 static struct clk_ops s5p6450_epll_ops = {
89 .get_rate = s5p64x0_epll_get_rate,
90 .set_rate = s5p6450_epll_set_rate,
93 static struct clksrc_clk clk_dout_epll = {
97 .parent = &clk_mout_epll.clk,
99 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
102 static struct clksrc_clk clk_mout_hclk_sel = {
104 .name = "mout_hclk_sel",
107 .sources = &clkset_hclk_low,
108 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
111 static struct clk *clkset_hclk_list[] = {
112 &clk_mout_hclk_sel.clk,
116 static struct clksrc_sources clkset_hclk = {
117 .sources = clkset_hclk_list,
118 .nr_sources = ARRAY_SIZE(clkset_hclk_list),
121 static struct clksrc_clk clk_hclk = {
126 .sources = &clkset_hclk,
127 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
128 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
131 static struct clksrc_clk clk_pclk = {
135 .parent = &clk_hclk.clk,
137 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
139 static struct clksrc_clk clk_dout_pwm_ratio0 = {
141 .name = "clk_dout_pwm_ratio0",
143 .parent = &clk_mout_hclk_sel.clk,
145 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
148 static struct clksrc_clk clk_pclk_to_wdt_pwm = {
150 .name = "clk_pclk_to_wdt_pwm",
152 .parent = &clk_dout_pwm_ratio0.clk,
154 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
157 static struct clksrc_clk clk_hclk_low = {
159 .name = "clk_hclk_low",
162 .sources = &clkset_hclk_low,
163 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
164 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
167 static struct clksrc_clk clk_pclk_low = {
169 .name = "clk_pclk_low",
171 .parent = &clk_hclk_low.clk,
173 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
177 * The following clocks will be disabled during clock initialization. It is
178 * recommended to keep the following clocks disabled until the driver requests
179 * for enabling the clock.
181 static struct clk init_clocks_disable[] = {
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk0_ctrl,
191 .parent = &clk_hclk_low.clk,
192 .enable = s5p64x0_hclk0_ctrl,
193 .ctrlbit = (1 << 17),
197 .parent = &clk_hclk_low.clk,
198 .enable = s5p64x0_hclk0_ctrl,
199 .ctrlbit = (1 << 18),
203 .parent = &clk_hclk_low.clk,
204 .enable = s5p64x0_hclk0_ctrl,
205 .ctrlbit = (1 << 19),
209 .parent = &clk_hclk_low.clk,
210 .enable = s5p64x0_hclk0_ctrl,
211 .ctrlbit = (1 << 20),
216 .enable = s5p64x0_hclk1_ctrl,
221 .parent = &clk_pclk_low.clk,
222 .enable = s5p64x0_pclk_ctrl,
227 .parent = &clk_pclk_low.clk,
228 .enable = s5p64x0_pclk_ctrl,
229 .ctrlbit = (1 << 12),
233 .parent = &clk_pclk_low.clk,
234 .enable = s5p64x0_pclk_ctrl,
235 .ctrlbit = (1 << 17),
239 .parent = &clk_pclk_low.clk,
240 .enable = s5p64x0_pclk_ctrl,
241 .ctrlbit = (1 << 21),
245 .parent = &clk_pclk_low.clk,
246 .enable = s5p64x0_pclk_ctrl,
247 .ctrlbit = (1 << 22),
251 .parent = &clk_pclk_low.clk,
252 .enable = s5p64x0_pclk_ctrl,
253 .ctrlbit = (1 << 26),
257 .parent = &clk_pclk_low.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 27),
263 .parent = &clk_pclk.clk,
264 .enable = s5p64x0_pclk_ctrl,
265 .ctrlbit = (1 << 30),
270 * The following clocks will be enabled during clock initialization.
272 static struct clk init_clocks[] = {
276 .parent = &clk_hclk.clk,
277 .enable = s5p64x0_hclk0_ctrl,
282 .parent = &clk_hclk.clk,
283 .enable = s5p64x0_hclk0_ctrl,
284 .ctrlbit = (1 << 21),
288 .parent = &clk_hclk_low.clk,
289 .enable = s5p64x0_hclk0_ctrl,
290 .ctrlbit = (1 << 12),
294 .parent = &clk_pclk_low.clk,
295 .enable = s5p64x0_pclk_ctrl,
300 .parent = &clk_pclk_low.clk,
301 .enable = s5p64x0_pclk_ctrl,
306 .parent = &clk_pclk_low.clk,
307 .enable = s5p64x0_pclk_ctrl,
312 .parent = &clk_pclk_low.clk,
313 .enable = s5p64x0_pclk_ctrl,
318 .parent = &clk_pclk_to_wdt_pwm.clk,
319 .enable = s5p64x0_pclk_ctrl,
324 .parent = &clk_pclk_low.clk,
325 .enable = s5p64x0_pclk_ctrl,
326 .ctrlbit = (1 << 18),
330 static struct clk *clkset_uart_list[] = {
335 static struct clksrc_sources clkset_uart = {
336 .sources = clkset_uart_list,
337 .nr_sources = ARRAY_SIZE(clkset_uart_list),
340 static struct clk *clkset_mali_list[] = {
346 static struct clksrc_sources clkset_mali = {
347 .sources = clkset_mali_list,
348 .nr_sources = ARRAY_SIZE(clkset_mali_list),
351 static struct clk *clkset_group2_list[] = {
357 static struct clksrc_sources clkset_group2 = {
358 .sources = clkset_group2_list,
359 .nr_sources = ARRAY_SIZE(clkset_group2_list),
362 static struct clk *clkset_dispcon_list[] = {
369 static struct clksrc_sources clkset_dispcon = {
370 .sources = clkset_dispcon_list,
371 .nr_sources = ARRAY_SIZE(clkset_dispcon_list),
374 static struct clk *clkset_hsmmc44_list[] = {
382 static struct clksrc_sources clkset_hsmmc44 = {
383 .sources = clkset_hsmmc44_list,
384 .nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
387 static struct clk *clkset_sclk_audio0_list[] = {
388 [0] = &clk_dout_epll.clk,
389 [1] = &clk_dout_mpll.clk,
390 [2] = &clk_ext_xtal_mux,
395 static struct clksrc_sources clkset_sclk_audio0 = {
396 .sources = clkset_sclk_audio0_list,
397 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
400 static struct clksrc_clk clk_sclk_audio0 = {
404 .enable = s5p64x0_sclk_ctrl,
406 .parent = &clk_dout_epll.clk,
408 .sources = &clkset_sclk_audio0,
409 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
410 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
413 static struct clksrc_clk clksrcs[] = {
418 .ctrlbit = (1 << 24),
419 .enable = s5p64x0_sclk_ctrl,
421 .sources = &clkset_group2,
422 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
423 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
428 .ctrlbit = (1 << 25),
429 .enable = s5p64x0_sclk_ctrl,
431 .sources = &clkset_group2,
432 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
433 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
438 .ctrlbit = (1 << 26),
439 .enable = s5p64x0_sclk_ctrl,
441 .sources = &clkset_group2,
442 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
449 .enable = s5p64x0_sclk_ctrl,
451 .sources = &clkset_uart,
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
453 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
458 .ctrlbit = (1 << 20),
459 .enable = s5p64x0_sclk_ctrl,
461 .sources = &clkset_group2,
462 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
463 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
468 .ctrlbit = (1 << 21),
469 .enable = s5p64x0_sclk_ctrl,
471 .sources = &clkset_group2,
472 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
473 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
478 .ctrlbit = (1 << 10),
479 .enable = s5p64x0_sclk_ctrl,
481 .sources = &clkset_group2,
482 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
483 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
489 .enable = s5p64x0_sclk1_ctrl,
491 .sources = &clkset_mali,
492 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
493 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
498 .ctrlbit = (1 << 12),
499 .enable = s5p64x0_sclk_ctrl,
501 .sources = &clkset_mali,
502 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
503 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
509 .enable = s5p64x0_sclk_ctrl,
511 .sources = &clkset_group2,
512 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
513 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
516 .name = "sclk_camif",
519 .enable = s5p64x0_sclk_ctrl,
521 .sources = &clkset_group2,
522 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
523 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
526 .name = "sclk_dispcon",
529 .enable = s5p64x0_sclk1_ctrl,
531 .sources = &clkset_dispcon,
532 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
533 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
536 .name = "sclk_hsmmc44",
538 .ctrlbit = (1 << 30),
539 .enable = s5p64x0_sclk_ctrl,
541 .sources = &clkset_hsmmc44,
542 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
543 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
547 /* Clock initialization code */
548 static struct clksrc_clk *sysclks[] = {
556 &clk_dout_pwm_ratio0,
557 &clk_pclk_to_wdt_pwm,
565 void __init_or_cpufreq s5p6450_setup_clocks(void)
567 struct clk *xtal_clk;
572 unsigned long hclk_low;
574 unsigned long pclk_low;
582 /* Set S5P6450 functions for clk_fout_epll */
584 clk_fout_epll.enable = s5p64x0_epll_enable;
585 clk_fout_epll.ops = &s5p6450_epll_ops;
587 clk_48m.enable = s5p64x0_clk48m_ctrl;
589 xtal_clk = clk_get(NULL, "ext_xtal");
590 BUG_ON(IS_ERR(xtal_clk));
592 xtal = clk_get_rate(xtal_clk);
595 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
596 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
597 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
598 __raw_readl(S5P64X0_EPLL_CON_K));
599 dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
600 __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
602 clk_fout_apll.rate = apll;
603 clk_fout_mpll.rate = mpll;
604 clk_fout_epll.rate = epll;
605 clk_fout_dpll.rate = dpll;
607 printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
608 " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
609 print_mhz(apll), print_mhz(mpll), print_mhz(epll),
612 fclk = clk_get_rate(&clk_armclk.clk);
613 hclk = clk_get_rate(&clk_hclk.clk);
614 pclk = clk_get_rate(&clk_pclk.clk);
615 hclk_low = clk_get_rate(&clk_hclk_low.clk);
616 pclk_low = clk_get_rate(&clk_pclk_low.clk);
618 printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
619 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
620 print_mhz(hclk), print_mhz(hclk_low),
621 print_mhz(pclk), print_mhz(pclk_low));
627 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
628 s3c_set_clksrc(&clksrcs[ptr], true);
631 void __init s5p6450_register_clocks(void)
637 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
638 s3c_register_clksrc(sysclks[ptr], 1);
640 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
641 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
643 clkp = init_clocks_disable;
644 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
646 ret = s3c24xx_register_clock(clkp);
648 printk(KERN_ERR "Failed to register clock %s (%d)\n",
651 (clkp->enable)(clkp, 0);