2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for S5P64X0 machines
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
20 #include <linux/device.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/gpio.h>
26 #include <linux/irq.h>
29 #include <asm/proc-fns.h>
30 #include <asm/system_misc.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/map.h>
33 #include <asm/mach/irq.h>
36 #include <mach/hardware.h>
37 #include <mach/regs-clock.h>
38 #include <mach/regs-gpio.h>
41 #include <plat/clock.h>
42 #include <plat/devs.h>
44 #include <plat/sdhci.h>
45 #include <plat/adc-core.h>
46 #include <plat/fb-core.h>
47 #include <plat/gpio-cfg.h>
48 #include <plat/regs-irqtype.h>
49 #include <plat/regs-serial.h>
50 #include <plat/watchdog-reset.h>
54 static const char name_s5p6440[] = "S5P6440";
55 static const char name_s5p6450[] = "S5P6450";
57 static struct cpu_table cpu_ids[] __initdata = {
59 .idcode = S5P6440_CPU_ID,
60 .idmask = S5P64XX_CPU_MASK,
61 .map_io = s5p6440_map_io,
62 .init_clocks = s5p6440_init_clocks,
63 .init_uarts = s5p6440_init_uarts,
67 .idcode = S5P6450_CPU_ID,
68 .idmask = S5P64XX_CPU_MASK,
69 .map_io = s5p6450_map_io,
70 .init_clocks = s5p6450_init_clocks,
71 .init_uarts = s5p6450_init_uarts,
77 /* Initial IO mappings */
79 static struct map_desc s5p64x0_iodesc[] __initdata = {
81 .virtual = (unsigned long)S5P_VA_CHIPID,
82 .pfn = __phys_to_pfn(S5P64X0_PA_CHIPID),
86 .virtual = (unsigned long)S3C_VA_SYS,
87 .pfn = __phys_to_pfn(S5P64X0_PA_SYSCON),
91 .virtual = (unsigned long)S3C_VA_TIMER,
92 .pfn = __phys_to_pfn(S5P64X0_PA_TIMER),
96 .virtual = (unsigned long)S3C_VA_WATCHDOG,
97 .pfn = __phys_to_pfn(S5P64X0_PA_WDT),
101 .virtual = (unsigned long)S5P_VA_SROMC,
102 .pfn = __phys_to_pfn(S5P64X0_PA_SROMC),
106 .virtual = (unsigned long)S5P_VA_GPIO,
107 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
111 .virtual = (unsigned long)VA_VIC0,
112 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
116 .virtual = (unsigned long)VA_VIC1,
117 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
123 static struct map_desc s5p6440_iodesc[] __initdata = {
125 .virtual = (unsigned long)S3C_VA_UART,
126 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
132 static struct map_desc s5p6450_iodesc[] __initdata = {
134 .virtual = (unsigned long)S3C_VA_UART,
135 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
139 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
140 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
146 static void s5p64x0_idle(void)
150 val = __raw_readl(S5P64X0_PWR_CFG);
153 __raw_writel(val, S5P64X0_PWR_CFG);
161 * register the standard CPU IO areas
164 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
166 /* initialize the io descriptors we need for initialization */
167 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
169 iotable_init(mach_desc, size);
171 /* detect cpu id and rev. */
172 s5p_init_cpu(S5P64X0_SYS_ID);
174 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
177 void __init s5p6440_map_io(void)
179 /* initialize any device information early */
180 s3c_adc_setname("s3c64xx-adc");
181 s3c_fb_setname("s5p64x0-fb");
183 s5p64x0_default_sdhci0();
184 s5p64x0_default_sdhci1();
185 s5p6440_default_sdhci2();
187 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
188 init_consistent_dma_size(SZ_8M);
191 void __init s5p6450_map_io(void)
193 /* initialize any device information early */
194 s3c_adc_setname("s3c64xx-adc");
195 s3c_fb_setname("s5p64x0-fb");
197 s5p64x0_default_sdhci0();
198 s5p64x0_default_sdhci1();
199 s5p6450_default_sdhci2();
201 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
202 init_consistent_dma_size(SZ_8M);
206 * s5p64x0_init_clocks
208 * register and setup the CPU clocks
211 void __init s5p6440_init_clocks(int xtal)
213 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
215 s3c24xx_register_baseclocks(xtal);
216 s5p_register_clocks(xtal);
217 s5p6440_register_clocks();
218 s5p6440_setup_clocks();
221 void __init s5p6450_init_clocks(int xtal)
223 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
225 s3c24xx_register_baseclocks(xtal);
226 s5p_register_clocks(xtal);
227 s5p6450_register_clocks();
228 s5p6450_setup_clocks();
234 * register the CPU interrupts
237 void __init s5p6440_init_irq(void)
239 /* S5P6440 supports 2 VIC */
243 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
244 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
249 s5p_init_irq(vic, ARRAY_SIZE(vic));
252 void __init s5p6450_init_irq(void)
254 /* S5P6450 supports only 2 VIC */
258 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
259 * VIC1 is missing IRQ VIC1[12, 14, 23]
264 s5p_init_irq(vic, ARRAY_SIZE(vic));
267 struct bus_type s5p64x0_subsys = {
268 .name = "s5p64x0-core",
269 .dev_name = "s5p64x0-core",
272 static struct device s5p64x0_dev = {
273 .bus = &s5p64x0_subsys,
276 static int __init s5p64x0_core_init(void)
278 return subsys_system_register(&s5p64x0_subsys, NULL);
280 core_initcall(s5p64x0_core_init);
282 int __init s5p64x0_init(void)
284 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
286 /* set idle function */
287 arm_pm_idle = s5p64x0_idle;
289 return device_register(&s5p64x0_dev);
292 /* uart registration process */
293 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
297 for (uart = 0; uart < no; uart++) {
298 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
299 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
302 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
305 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
307 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
310 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
312 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
314 int offs = eint_offset(data->irq);
324 printk(KERN_WARNING "No edge setting!\n");
326 case IRQ_TYPE_EDGE_RISING:
327 newvalue = S3C2410_EXTINT_RISEEDGE;
329 case IRQ_TYPE_EDGE_FALLING:
330 newvalue = S3C2410_EXTINT_FALLEDGE;
332 case IRQ_TYPE_EDGE_BOTH:
333 newvalue = S3C2410_EXTINT_BOTHEDGE;
335 case IRQ_TYPE_LEVEL_LOW:
336 newvalue = S3C2410_EXTINT_LOWLEV;
338 case IRQ_TYPE_LEVEL_HIGH:
339 newvalue = S3C2410_EXTINT_HILEV;
342 printk(KERN_ERR "No such irq type %d", type);
346 shift = (offs / 2) * 4;
349 ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
350 ctrl |= newvalue << shift;
351 __raw_writel(ctrl, S5P64X0_EINT0CON0);
353 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
354 if (soc_is_s5p6450())
355 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
357 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
363 * s5p64x0_irq_demux_eint
365 * This function demuxes the IRQ from the group0 external interrupts,
366 * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
367 * the specific handlers s5p64x0_irq_demux_eintX_Y.
369 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
371 u32 status = __raw_readl(S5P64X0_EINT0PEND);
372 u32 mask = __raw_readl(S5P64X0_EINT0MASK);
377 status &= (1 << (end - start + 1)) - 1;
379 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
381 generic_handle_irq(irq);
386 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
388 s5p64x0_irq_demux_eint(0, 3);
391 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
393 s5p64x0_irq_demux_eint(4, 11);
396 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
397 struct irq_desc *desc)
399 s5p64x0_irq_demux_eint(12, 15);
402 static int s5p64x0_alloc_gc(void)
404 struct irq_chip_generic *gc;
405 struct irq_chip_type *ct;
407 gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
408 S5P_VA_GPIO, handle_level_irq);
410 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
411 "external interrupts failed\n", __func__);
416 ct->chip.irq_ack = irq_gc_ack_set_bit;
417 ct->chip.irq_mask = irq_gc_mask_set_bit;
418 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
419 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
420 ct->chip.irq_set_wake = s3c_irqext_wake;
421 ct->regs.ack = EINT0PEND_OFFSET;
422 ct->regs.mask = EINT0MASK_OFFSET;
423 irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
424 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
428 static int __init s5p64x0_init_irq_eint(void)
430 int ret = s5p64x0_alloc_gc();
431 irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
432 irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
433 irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
437 arch_initcall(s5p64x0_init_irq_eint);
439 void s5p64x0_restart(char mode, const char *cmd)