1 /* linux/arch/arm/mach-s5p64x0/dev-spi.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
20 #include <mach/irqs.h>
21 #include <mach/regs-clock.h>
22 #include <mach/spi-clocks.h>
24 #include <plat/s3c64xx-spi.h>
25 #include <plat/gpio-cfg.h>
27 static char *s5p64x0_spi_src_clks[] = {
28 [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
29 [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
32 /* SPI Controller platform_devices */
34 /* Since we emulate multi-cs capability, we do not touch the CS.
35 * The emulated CS is toggled by board specific mechanism, as it can
36 * be either some immediate GPIO or some signal out of some other
37 * chip in between ... or some yet another way.
38 * We simply do not assume anything about CS.
40 static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
44 s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
45 s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
46 s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
47 s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
48 s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
49 s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
53 s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
54 s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
55 s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
56 s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
57 s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
58 s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
62 dev_err(&pdev->dev, "Invalid SPI Controller number!");
69 static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
73 s3c_gpio_cfgpin(S5P6450_GPC(0), S3C_GPIO_SFN(2));
74 s3c_gpio_cfgpin(S5P6450_GPC(1), S3C_GPIO_SFN(2));
75 s3c_gpio_cfgpin(S5P6450_GPC(2), S3C_GPIO_SFN(2));
76 s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
77 s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
78 s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
82 s3c_gpio_cfgpin(S5P6450_GPC(4), S3C_GPIO_SFN(2));
83 s3c_gpio_cfgpin(S5P6450_GPC(5), S3C_GPIO_SFN(2));
84 s3c_gpio_cfgpin(S5P6450_GPC(6), S3C_GPIO_SFN(2));
85 s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
86 s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
87 s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
91 dev_err(&pdev->dev, "Invalid SPI Controller number!");
98 static struct resource s5p64x0_spi0_resource[] = {
100 .start = S5P64X0_PA_SPI0,
101 .end = S5P64X0_PA_SPI0 + 0x100 - 1,
102 .flags = IORESOURCE_MEM,
105 .start = DMACH_SPI0_TX,
106 .end = DMACH_SPI0_TX,
107 .flags = IORESOURCE_DMA,
110 .start = DMACH_SPI0_RX,
111 .end = DMACH_SPI0_RX,
112 .flags = IORESOURCE_DMA,
117 .flags = IORESOURCE_IRQ,
121 static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
122 .cfg_gpio = s5p6440_spi_cfg_gpio,
123 .fifo_lvl_mask = 0x1ff,
127 static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
128 .cfg_gpio = s5p6450_spi_cfg_gpio,
129 .fifo_lvl_mask = 0x1ff,
133 static u64 spi_dmamask = DMA_BIT_MASK(32);
135 struct platform_device s5p64x0_device_spi0 = {
136 .name = "s3c64xx-spi",
138 .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
139 .resource = s5p64x0_spi0_resource,
141 .dma_mask = &spi_dmamask,
142 .coherent_dma_mask = DMA_BIT_MASK(32),
146 static struct resource s5p64x0_spi1_resource[] = {
148 .start = S5P64X0_PA_SPI1,
149 .end = S5P64X0_PA_SPI1 + 0x100 - 1,
150 .flags = IORESOURCE_MEM,
153 .start = DMACH_SPI1_TX,
154 .end = DMACH_SPI1_TX,
155 .flags = IORESOURCE_DMA,
158 .start = DMACH_SPI1_RX,
159 .end = DMACH_SPI1_RX,
160 .flags = IORESOURCE_DMA,
165 .flags = IORESOURCE_IRQ,
169 static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
170 .cfg_gpio = s5p6440_spi_cfg_gpio,
171 .fifo_lvl_mask = 0x7f,
175 static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
176 .cfg_gpio = s5p6450_spi_cfg_gpio,
177 .fifo_lvl_mask = 0x7f,
181 struct platform_device s5p64x0_device_spi1 = {
182 .name = "s3c64xx-spi",
184 .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
185 .resource = s5p64x0_spi1_resource,
187 .dma_mask = &spi_dmamask,
188 .coherent_dma_mask = DMA_BIT_MASK(32),
192 void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
195 struct s3c64xx_spi_info *pd;
197 id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
199 /* Reject invalid configuration */
200 if (!num_cs || src_clk_nr < 0
201 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
202 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
209 pd = &s5p6450_spi0_pdata;
211 pd = &s5p6440_spi0_pdata;
213 s5p64x0_device_spi0.dev.platform_data = pd;
217 pd = &s5p6450_spi1_pdata;
219 pd = &s5p6440_spi1_pdata;
221 s5p64x0_device_spi1.dev.platform_data = pd;
224 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
230 pd->src_clk_nr = src_clk_nr;
231 pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];