1 /* linux/arch/arm/mach-s5pc100/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PC100 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
23 #include <plat/cpu-freq.h>
24 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
28 #include <plat/s5p-clock.h>
29 #include <plat/clock-clksrc.h>
33 static struct clk s5p_clk_otgphy = {
37 static struct clk dummy_apb_pclk = {
42 static struct clk *clk_src_mout_href_list[] = {
47 static struct clksrc_sources clk_src_mout_href = {
48 .sources = clk_src_mout_href_list,
49 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
52 static struct clksrc_clk clk_mout_href = {
56 .sources = &clk_src_mout_href,
57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
60 static struct clk *clk_src_mout_48m_list[] = {
62 [1] = &s5p_clk_otgphy,
65 static struct clksrc_sources clk_src_mout_48m = {
66 .sources = clk_src_mout_48m_list,
67 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
70 static struct clksrc_clk clk_mout_48m = {
74 .sources = &clk_src_mout_48m,
75 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
78 static struct clksrc_clk clk_mout_mpll = {
82 .sources = &clk_src_mpll,
83 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
87 static struct clksrc_clk clk_mout_apll = {
91 .sources = &clk_src_apll,
92 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
95 static struct clksrc_clk clk_mout_epll = {
99 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
103 static struct clk *clk_src_mout_hpll_list[] = {
107 static struct clksrc_sources clk_src_mout_hpll = {
108 .sources = clk_src_mout_hpll_list,
109 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
112 static struct clksrc_clk clk_mout_hpll = {
116 .sources = &clk_src_mout_hpll,
117 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
120 static struct clksrc_clk clk_div_apll = {
123 .parent = &clk_mout_apll.clk,
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
128 static struct clksrc_clk clk_div_arm = {
131 .parent = &clk_div_apll.clk,
133 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
136 static struct clksrc_clk clk_div_d0_bus = {
138 .name = "div_d0_bus",
139 .parent = &clk_div_arm.clk,
141 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
144 static struct clksrc_clk clk_div_pclkd0 = {
146 .name = "div_pclkd0",
147 .parent = &clk_div_d0_bus.clk,
149 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
152 static struct clksrc_clk clk_div_secss = {
155 .parent = &clk_div_d0_bus.clk,
157 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
160 static struct clksrc_clk clk_div_apll2 = {
163 .parent = &clk_mout_apll.clk,
165 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
168 static struct clk *clk_src_mout_am_list[] = {
169 [0] = &clk_mout_mpll.clk,
170 [1] = &clk_div_apll2.clk,
173 static struct clksrc_sources clk_src_mout_am = {
174 .sources = clk_src_mout_am_list,
175 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
178 static struct clksrc_clk clk_mout_am = {
182 .sources = &clk_src_mout_am,
183 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
186 static struct clksrc_clk clk_div_d1_bus = {
188 .name = "div_d1_bus",
189 .parent = &clk_mout_am.clk,
191 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
194 static struct clksrc_clk clk_div_mpll2 = {
197 .parent = &clk_mout_am.clk,
199 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
202 static struct clksrc_clk clk_div_mpll = {
205 .parent = &clk_mout_am.clk,
207 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
210 static struct clk *clk_src_mout_onenand_list[] = {
211 [0] = &clk_div_d0_bus.clk,
212 [1] = &clk_div_d1_bus.clk,
215 static struct clksrc_sources clk_src_mout_onenand = {
216 .sources = clk_src_mout_onenand_list,
217 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
220 static struct clksrc_clk clk_mout_onenand = {
222 .name = "mout_onenand",
224 .sources = &clk_src_mout_onenand,
225 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
228 static struct clksrc_clk clk_div_onenand = {
230 .name = "div_onenand",
231 .parent = &clk_mout_onenand.clk,
233 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
236 static struct clksrc_clk clk_div_pclkd1 = {
238 .name = "div_pclkd1",
239 .parent = &clk_div_d1_bus.clk,
241 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
244 static struct clksrc_clk clk_div_cam = {
247 .parent = &clk_div_mpll2.clk,
249 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
252 static struct clksrc_clk clk_div_hdmi = {
255 .parent = &clk_mout_hpll.clk,
257 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
260 static u32 epll_div[][4] = {
261 { 32750000, 131, 3, 4 },
262 { 32768000, 131, 3, 4 },
263 { 36000000, 72, 3, 3 },
264 { 45000000, 90, 3, 3 },
265 { 45158000, 90, 3, 3 },
266 { 45158400, 90, 3, 3 },
267 { 48000000, 96, 3, 3 },
268 { 49125000, 131, 4, 3 },
269 { 49152000, 131, 4, 3 },
270 { 60000000, 120, 3, 3 },
271 { 67737600, 226, 5, 3 },
272 { 67738000, 226, 5, 3 },
273 { 73800000, 246, 5, 3 },
274 { 73728000, 246, 5, 3 },
275 { 72000000, 144, 3, 3 },
276 { 84000000, 168, 3, 3 },
277 { 96000000, 96, 3, 2 },
278 { 144000000, 144, 3, 2 },
279 { 192000000, 96, 3, 1 }
282 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
284 unsigned int epll_con;
287 if (clk->rate == rate) /* Return if nothing changed */
290 epll_con = __raw_readl(S5P_EPLL_CON);
292 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
294 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
295 if (epll_div[i][0] == rate) {
296 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
297 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
298 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
303 if (i == ARRAY_SIZE(epll_div)) {
304 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
308 __raw_writel(epll_con, S5P_EPLL_CON);
310 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
318 static struct clk_ops s5pc100_epll_ops = {
319 .get_rate = s5p_epll_get_rate,
320 .set_rate = s5pc100_epll_set_rate,
323 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
325 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
328 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
330 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
333 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
335 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
338 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
340 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
343 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
345 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
348 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
350 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
353 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
355 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
358 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
360 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
363 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
365 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
368 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
370 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
373 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
375 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
379 * The following clocks will be disabled during clock initialization. It is
380 * recommended to keep the following clocks disabled until the driver requests
381 * for enabling the clock.
383 static struct clk init_clocks_off[] = {
386 .parent = &clk_div_d0_bus.clk,
387 .enable = s5pc100_d0_0_ctrl,
391 .parent = &clk_div_d0_bus.clk,
392 .enable = s5pc100_d0_0_ctrl,
396 .parent = &clk_div_d0_bus.clk,
397 .enable = s5pc100_d0_0_ctrl,
401 .parent = &clk_div_d0_bus.clk,
402 .enable = s5pc100_d0_0_ctrl,
406 .parent = &clk_div_d0_bus.clk,
407 .enable = s5pc100_d0_0_ctrl,
411 .parent = &clk_div_d0_bus.clk,
412 .enable = s5pc100_d0_1_ctrl,
416 .parent = &clk_div_d0_bus.clk,
417 .enable = s5pc100_d0_1_ctrl,
421 .parent = &clk_div_d0_bus.clk,
422 .enable = s5pc100_d0_2_ctrl,
426 .parent = &clk_div_d0_bus.clk,
427 .enable = s5pc100_d0_2_ctrl,
431 .parent = &clk_div_d1_bus.clk,
432 .enable = s5pc100_d1_0_ctrl,
436 .parent = &clk_div_d1_bus.clk,
437 .enable = s5pc100_d1_0_ctrl,
441 .parent = &clk_div_d1_bus.clk,
442 .enable = s5pc100_d1_0_ctrl,
446 .devname = "dma-pl330.1",
447 .parent = &clk_div_d1_bus.clk,
448 .enable = s5pc100_d1_0_ctrl,
452 .devname = "dma-pl330.0",
453 .parent = &clk_div_d1_bus.clk,
454 .enable = s5pc100_d1_0_ctrl,
458 .parent = &clk_div_d1_bus.clk,
459 .enable = s5pc100_d1_1_ctrl,
463 .parent = &clk_div_d1_bus.clk,
464 .enable = s5pc100_d1_1_ctrl,
468 .devname = "s5p-fimc.0",
469 .parent = &clk_div_d1_bus.clk,
470 .enable = s5pc100_d1_1_ctrl,
474 .devname = "s5p-fimc.1",
475 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_1_ctrl,
480 .devname = "s5p-fimc.2",
481 .enable = s5pc100_d1_1_ctrl,
485 .parent = &clk_div_d1_bus.clk,
486 .enable = s5pc100_d1_1_ctrl,
490 .parent = &clk_div_d1_bus.clk,
491 .enable = s5pc100_d1_1_ctrl,
495 .parent = &clk_div_d1_bus.clk,
496 .enable = s5pc100_d1_1_ctrl,
500 .parent = &clk_div_d1_bus.clk,
501 .enable = s5pc100_d1_0_ctrl,
505 .parent = &clk_div_d1_bus.clk,
506 .enable = s5pc100_d1_2_ctrl,
510 .parent = &clk_div_d1_bus.clk,
511 .enable = s5pc100_d1_2_ctrl,
515 .parent = &clk_div_d1_bus.clk,
516 .enable = s5pc100_d1_2_ctrl,
520 .parent = &clk_div_d1_bus.clk,
521 .enable = s5pc100_d1_2_ctrl,
525 .parent = &clk_div_d1_bus.clk,
526 .enable = s5pc100_d1_2_ctrl,
530 .parent = &clk_div_d1_bus.clk,
531 .enable = s5pc100_d1_3_ctrl,
535 .parent = &clk_div_d1_bus.clk,
536 .enable = s5pc100_d1_3_ctrl,
540 .parent = &clk_div_d1_bus.clk,
541 .enable = s5pc100_d1_3_ctrl,
545 .parent = &clk_div_d1_bus.clk,
546 .enable = s5pc100_d1_3_ctrl,
550 .parent = &clk_div_d1_bus.clk,
551 .enable = s5pc100_d1_3_ctrl,
555 .devname = "s3c2440-i2c.0",
556 .parent = &clk_div_d1_bus.clk,
557 .enable = s5pc100_d1_4_ctrl,
561 .devname = "s3c2440-i2c.1",
562 .parent = &clk_div_d1_bus.clk,
563 .enable = s5pc100_d1_4_ctrl,
567 .devname = "s5pc100-spi.0",
568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_4_ctrl,
573 .devname = "s5pc100-spi.1",
574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_4_ctrl,
579 .devname = "s5pc100-spi.2",
580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_4_ctrl,
585 .parent = &clk_div_d1_bus.clk,
586 .enable = s5pc100_d1_4_ctrl,
590 .parent = &clk_div_d1_bus.clk,
591 .enable = s5pc100_d1_4_ctrl,
592 .ctrlbit = (1 << 10),
595 .parent = &clk_div_d1_bus.clk,
596 .enable = s5pc100_d1_4_ctrl,
597 .ctrlbit = (1 << 11),
600 .parent = &clk_div_d1_bus.clk,
601 .enable = s5pc100_d1_4_ctrl,
602 .ctrlbit = (1 << 12),
605 .parent = &clk_div_d1_bus.clk,
606 .enable = s5pc100_d1_4_ctrl,
607 .ctrlbit = (1 << 13),
610 .devname = "samsung-i2s.0",
611 .parent = &clk_div_pclkd1.clk,
612 .enable = s5pc100_d1_5_ctrl,
616 .devname = "samsung-i2s.1",
617 .parent = &clk_div_pclkd1.clk,
618 .enable = s5pc100_d1_5_ctrl,
622 .devname = "samsung-i2s.2",
623 .parent = &clk_div_pclkd1.clk,
624 .enable = s5pc100_d1_5_ctrl,
628 .parent = &clk_div_pclkd1.clk,
629 .enable = s5pc100_d1_5_ctrl,
633 .devname = "samsung-pcm.0",
634 .parent = &clk_div_pclkd1.clk,
635 .enable = s5pc100_d1_5_ctrl,
639 .devname = "samsung-pcm.1",
640 .parent = &clk_div_pclkd1.clk,
641 .enable = s5pc100_d1_5_ctrl,
645 .parent = &clk_div_pclkd1.clk,
646 .enable = s5pc100_d1_5_ctrl,
650 .parent = &clk_div_pclkd1.clk,
651 .enable = s5pc100_d1_5_ctrl,
655 .parent = &clk_div_pclkd1.clk,
656 .enable = s5pc100_d1_5_ctrl,
660 .devname = "s3c-sdhci.0",
661 .parent = &clk_mout_48m.clk,
662 .enable = s5pc100_sclk0_ctrl,
663 .ctrlbit = (1 << 15),
666 .devname = "s3c-sdhci.1",
667 .parent = &clk_mout_48m.clk,
668 .enable = s5pc100_sclk0_ctrl,
669 .ctrlbit = (1 << 16),
672 .devname = "s3c-sdhci.2",
673 .parent = &clk_mout_48m.clk,
674 .enable = s5pc100_sclk0_ctrl,
675 .ctrlbit = (1 << 17),
679 static struct clk clk_hsmmc2 = {
681 .devname = "s3c-sdhci.2",
682 .parent = &clk_div_d1_bus.clk,
683 .enable = s5pc100_d1_0_ctrl,
687 static struct clk clk_hsmmc1 = {
689 .devname = "s3c-sdhci.1",
690 .parent = &clk_div_d1_bus.clk,
691 .enable = s5pc100_d1_0_ctrl,
695 static struct clk clk_hsmmc0 = {
697 .devname = "s3c-sdhci.0",
698 .parent = &clk_div_d1_bus.clk,
699 .enable = s5pc100_d1_0_ctrl,
703 static struct clk clk_48m_spi0 = {
705 .devname = "s5pc100-spi.0",
706 .parent = &clk_mout_48m.clk,
707 .enable = s5pc100_sclk0_ctrl,
711 static struct clk clk_48m_spi1 = {
713 .devname = "s5pc100-spi.1",
714 .parent = &clk_mout_48m.clk,
715 .enable = s5pc100_sclk0_ctrl,
719 static struct clk clk_48m_spi2 = {
721 .devname = "s5pc100-spi.2",
722 .parent = &clk_mout_48m.clk,
723 .enable = s5pc100_sclk0_ctrl,
727 static struct clk clk_vclk54m = {
732 static struct clk clk_i2scdclk0 = {
733 .name = "i2s_cdclk0",
736 static struct clk clk_i2scdclk1 = {
737 .name = "i2s_cdclk1",
740 static struct clk clk_i2scdclk2 = {
741 .name = "i2s_cdclk2",
744 static struct clk clk_pcmcdclk0 = {
745 .name = "pcm_cdclk0",
748 static struct clk clk_pcmcdclk1 = {
749 .name = "pcm_cdclk1",
752 static struct clk *clk_src_group1_list[] = {
753 [0] = &clk_mout_epll.clk,
754 [1] = &clk_div_mpll2.clk,
756 [3] = &clk_mout_hpll.clk,
759 static struct clksrc_sources clk_src_group1 = {
760 .sources = clk_src_group1_list,
761 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
764 static struct clk *clk_src_group2_list[] = {
765 [0] = &clk_mout_epll.clk,
766 [1] = &clk_div_mpll.clk,
769 static struct clksrc_sources clk_src_group2 = {
770 .sources = clk_src_group2_list,
771 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
774 static struct clk *clk_src_group3_list[] = {
775 [0] = &clk_mout_epll.clk,
776 [1] = &clk_div_mpll.clk,
778 [3] = &clk_i2scdclk0,
779 [4] = &clk_pcmcdclk0,
780 [5] = &clk_mout_hpll.clk,
783 static struct clksrc_sources clk_src_group3 = {
784 .sources = clk_src_group3_list,
785 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
788 static struct clksrc_clk clk_sclk_audio0 = {
790 .name = "sclk_audio",
791 .devname = "samsung-pcm.0",
793 .enable = s5pc100_sclk1_ctrl,
795 .sources = &clk_src_group3,
796 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
797 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
800 static struct clk *clk_src_group4_list[] = {
801 [0] = &clk_mout_epll.clk,
802 [1] = &clk_div_mpll.clk,
804 [3] = &clk_i2scdclk1,
805 [4] = &clk_pcmcdclk1,
806 [5] = &clk_mout_hpll.clk,
809 static struct clksrc_sources clk_src_group4 = {
810 .sources = clk_src_group4_list,
811 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
814 static struct clksrc_clk clk_sclk_audio1 = {
816 .name = "sclk_audio",
817 .devname = "samsung-pcm.1",
819 .enable = s5pc100_sclk1_ctrl,
821 .sources = &clk_src_group4,
822 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
823 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
826 static struct clk *clk_src_group5_list[] = {
827 [0] = &clk_mout_epll.clk,
828 [1] = &clk_div_mpll.clk,
830 [3] = &clk_i2scdclk2,
831 [4] = &clk_mout_hpll.clk,
834 static struct clksrc_sources clk_src_group5 = {
835 .sources = clk_src_group5_list,
836 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
839 static struct clksrc_clk clk_sclk_audio2 = {
841 .name = "sclk_audio",
842 .devname = "samsung-pcm.2",
843 .ctrlbit = (1 << 10),
844 .enable = s5pc100_sclk1_ctrl,
846 .sources = &clk_src_group5,
847 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
848 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
851 static struct clk *clk_src_group6_list[] = {
854 [2] = &clk_div_hdmi.clk,
857 static struct clksrc_sources clk_src_group6 = {
858 .sources = clk_src_group6_list,
859 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
862 static struct clk *clk_src_group7_list[] = {
863 [0] = &clk_mout_epll.clk,
864 [1] = &clk_div_mpll.clk,
865 [2] = &clk_mout_hpll.clk,
869 static struct clksrc_sources clk_src_group7 = {
870 .sources = clk_src_group7_list,
871 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
874 static struct clk *clk_src_mmc0_list[] = {
875 [0] = &clk_mout_epll.clk,
876 [1] = &clk_div_mpll.clk,
880 static struct clksrc_sources clk_src_mmc0 = {
881 .sources = clk_src_mmc0_list,
882 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
885 static struct clk *clk_src_mmc12_list[] = {
886 [0] = &clk_mout_epll.clk,
887 [1] = &clk_div_mpll.clk,
889 [3] = &clk_mout_hpll.clk,
892 static struct clksrc_sources clk_src_mmc12 = {
893 .sources = clk_src_mmc12_list,
894 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
897 static struct clk *clk_src_irda_usb_list[] = {
898 [0] = &clk_mout_epll.clk,
899 [1] = &clk_div_mpll.clk,
901 [3] = &clk_mout_hpll.clk,
904 static struct clksrc_sources clk_src_irda_usb = {
905 .sources = clk_src_irda_usb_list,
906 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
909 static struct clk *clk_src_pwi_list[] = {
911 [1] = &clk_mout_epll.clk,
912 [2] = &clk_div_mpll.clk,
915 static struct clksrc_sources clk_src_pwi = {
916 .sources = clk_src_pwi_list,
917 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
920 static struct clk *clk_sclk_spdif_list[] = {
921 [0] = &clk_sclk_audio0.clk,
922 [1] = &clk_sclk_audio1.clk,
923 [2] = &clk_sclk_audio2.clk,
926 static struct clksrc_sources clk_src_sclk_spdif = {
927 .sources = clk_sclk_spdif_list,
928 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
931 static struct clksrc_clk clk_sclk_spdif = {
933 .name = "sclk_spdif",
934 .ctrlbit = (1 << 11),
935 .enable = s5pc100_sclk1_ctrl,
936 .ops = &s5p_sclk_spdif_ops,
938 .sources = &clk_src_sclk_spdif,
939 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
942 static struct clksrc_clk clksrcs[] = {
945 .name = "sclk_mixer",
947 .enable = s5pc100_sclk0_ctrl,
950 .sources = &clk_src_group6,
951 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
956 .enable = s5pc100_sclk1_ctrl,
959 .sources = &clk_src_group7,
960 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
961 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
965 .devname = "s5p-fimc.0",
967 .enable = s5pc100_sclk1_ctrl,
970 .sources = &clk_src_group7,
971 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
972 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
976 .devname = "s5p-fimc.1",
978 .enable = s5pc100_sclk1_ctrl,
981 .sources = &clk_src_group7,
982 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
983 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
987 .devname = "s5p-fimc.2",
989 .enable = s5pc100_sclk1_ctrl,
992 .sources = &clk_src_group7,
993 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
994 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
998 .ctrlbit = (1 << 10),
999 .enable = s5pc100_sclk0_ctrl,
1002 .sources = &clk_src_irda_usb,
1003 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1004 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1007 .name = "sclk_irda",
1008 .ctrlbit = (1 << 10),
1009 .enable = s5pc100_sclk0_ctrl,
1012 .sources = &clk_src_mmc12,
1013 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1014 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1018 .ctrlbit = (1 << 1),
1019 .enable = s5pc100_sclk0_ctrl,
1022 .sources = &clk_src_pwi,
1023 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1024 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1027 .name = "sclk_uhost",
1028 .ctrlbit = (1 << 11),
1029 .enable = s5pc100_sclk0_ctrl,
1032 .sources = &clk_src_irda_usb,
1033 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1034 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1038 static struct clksrc_clk clk_sclk_uart = {
1041 .ctrlbit = (1 << 3),
1042 .enable = s5pc100_sclk0_ctrl,
1044 .sources = &clk_src_group2,
1045 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1046 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1049 static struct clksrc_clk clk_sclk_mmc0 = {
1052 .devname = "s3c-sdhci.0",
1053 .ctrlbit = (1 << 12),
1054 .enable = s5pc100_sclk1_ctrl,
1056 .sources = &clk_src_mmc0,
1057 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1058 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1061 static struct clksrc_clk clk_sclk_mmc1 = {
1064 .devname = "s3c-sdhci.1",
1065 .ctrlbit = (1 << 13),
1066 .enable = s5pc100_sclk1_ctrl,
1068 .sources = &clk_src_mmc12,
1069 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1070 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1073 static struct clksrc_clk clk_sclk_mmc2 = {
1076 .devname = "s3c-sdhci.2",
1077 .ctrlbit = (1 << 14),
1078 .enable = s5pc100_sclk1_ctrl,
1080 .sources = &clk_src_mmc12,
1081 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1082 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1085 static struct clksrc_clk clk_sclk_spi0 = {
1088 .devname = "s5pc100-spi.0",
1089 .ctrlbit = (1 << 4),
1090 .enable = s5pc100_sclk0_ctrl,
1092 .sources = &clk_src_group1,
1093 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1094 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1097 static struct clksrc_clk clk_sclk_spi1 = {
1100 .devname = "s5pc100-spi.1",
1101 .ctrlbit = (1 << 5),
1102 .enable = s5pc100_sclk0_ctrl,
1104 .sources = &clk_src_group1,
1105 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1106 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1109 static struct clksrc_clk clk_sclk_spi2 = {
1112 .devname = "s5pc100-spi.2",
1113 .ctrlbit = (1 << 6),
1114 .enable = s5pc100_sclk0_ctrl,
1116 .sources = &clk_src_group1,
1117 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1118 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1121 /* Clock initialisation code */
1122 static struct clksrc_clk *sysclks[] = {
1150 static struct clk *clk_cdev[] = {
1159 static struct clksrc_clk *clksrc_cdev[] = {
1169 void __init_or_cpufreq s5pc100_setup_clocks(void)
1173 unsigned long hclkd0;
1174 unsigned long hclkd1;
1175 unsigned long pclkd0;
1176 unsigned long pclkd1;
1183 /* Set S5PC100 functions for clk_fout_epll */
1184 clk_fout_epll.enable = s5p_epll_enable;
1185 clk_fout_epll.ops = &s5pc100_epll_ops;
1187 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1189 xtal = clk_get_rate(&clk_xtal);
1191 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1193 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1194 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1195 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1196 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1198 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1199 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1201 clk_fout_apll.rate = apll;
1202 clk_fout_mpll.rate = mpll;
1203 clk_fout_epll.rate = epll;
1204 clk_mout_hpll.clk.rate = hpll;
1206 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1207 s3c_set_clksrc(&clksrcs[ptr], true);
1209 arm = clk_get_rate(&clk_div_arm.clk);
1210 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1211 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1212 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1213 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1215 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1216 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1219 clk_h.rate = hclkd1;
1220 clk_p.rate = pclkd1;
1224 * The following clocks will be enabled during clock initialization.
1226 static struct clk init_clocks[] = {
1229 .parent = &clk_div_d0_bus.clk,
1230 .enable = s5pc100_d0_0_ctrl,
1231 .ctrlbit = (1 << 1),
1234 .parent = &clk_div_d0_bus.clk,
1235 .enable = s5pc100_d0_0_ctrl,
1236 .ctrlbit = (1 << 0),
1239 .parent = &clk_div_d0_bus.clk,
1240 .enable = s5pc100_d0_1_ctrl,
1241 .ctrlbit = (1 << 5),
1244 .parent = &clk_div_d0_bus.clk,
1245 .enable = s5pc100_d0_1_ctrl,
1246 .ctrlbit = (1 << 4),
1249 .parent = &clk_div_d0_bus.clk,
1250 .enable = s5pc100_d0_1_ctrl,
1251 .ctrlbit = (1 << 1),
1254 .parent = &clk_div_d0_bus.clk,
1255 .enable = s5pc100_d0_1_ctrl,
1256 .ctrlbit = (1 << 0),
1259 .parent = &clk_div_d0_bus.clk,
1260 .enable = s5pc100_d0_1_ctrl,
1261 .ctrlbit = (1 << 0),
1264 .parent = &clk_div_d1_bus.clk,
1265 .enable = s5pc100_d1_3_ctrl,
1266 .ctrlbit = (1 << 1),
1269 .devname = "s3c6400-uart.0",
1270 .parent = &clk_div_d1_bus.clk,
1271 .enable = s5pc100_d1_4_ctrl,
1272 .ctrlbit = (1 << 0),
1275 .devname = "s3c6400-uart.1",
1276 .parent = &clk_div_d1_bus.clk,
1277 .enable = s5pc100_d1_4_ctrl,
1278 .ctrlbit = (1 << 1),
1281 .devname = "s3c6400-uart.2",
1282 .parent = &clk_div_d1_bus.clk,
1283 .enable = s5pc100_d1_4_ctrl,
1284 .ctrlbit = (1 << 2),
1287 .devname = "s3c6400-uart.3",
1288 .parent = &clk_div_d1_bus.clk,
1289 .enable = s5pc100_d1_4_ctrl,
1290 .ctrlbit = (1 << 3),
1293 .parent = &clk_div_d1_bus.clk,
1294 .enable = s5pc100_d1_3_ctrl,
1295 .ctrlbit = (1 << 6),
1299 static struct clk *clks[] __initdata = {
1308 static struct clk_lookup s5pc100_clk_lookup[] = {
1309 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1310 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1311 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1312 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1313 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1314 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1315 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1316 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1317 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1318 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
1319 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1320 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
1321 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1322 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
1323 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1326 void __init s5pc100_register_clocks(void)
1330 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1332 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1333 s3c_register_clksrc(sysclks[ptr], 1);
1335 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1336 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1337 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1338 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1340 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1341 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1342 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1344 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1345 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1346 s3c_disable_clocks(clk_cdev[ptr], 1);
1348 s3c24xx_register_clock(&dummy_apb_pclk);