arch/arm/mach-s5pc100/clock.c

   1 /* linux/arch/arm/mach-s5pc100/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PC100 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/io.h>
  20
  21 #include <mach/map.h>
  22
  23 #include <plat/cpu-freq.h>
  24 #include <mach/regs-clock.h>
  25 #include <plat/clock.h>
  26 #include <plat/cpu.h>
  27 #include <plat/pll.h>
  28 #include <plat/s5p-clock.h>
  29 #include <plat/clock-clksrc.h>
  30
  31 #include "common.h"
  32
  33 static struct clk s5p_clk_otgphy = {
  34         .name           = "otg_phy",
  35 };
  36
  37 static struct clk dummy_apb_pclk = {
  38         .name           = "apb_pclk",
  39         .id             = -1,
  40 };
  41
  42 static struct clk *clk_src_mout_href_list[] = {
  43         [0] = &s5p_clk_27m,
  44         [1] = &clk_fin_hpll,
  45 };
  46
  47 static struct clksrc_sources clk_src_mout_href = {
  48         .sources        = clk_src_mout_href_list,
  49         .nr_sources     = ARRAY_SIZE(clk_src_mout_href_list),
  50 };
  51
  52 static struct clksrc_clk clk_mout_href = {
  53         .clk = {
  54                 .name           = "mout_href",
  55         },
  56         .sources        = &clk_src_mout_href,
  57         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
  58 };
  59
  60 static struct clk *clk_src_mout_48m_list[] = {
  61         [0] = &clk_xusbxti,
  62         [1] = &s5p_clk_otgphy,
  63 };
  64
  65 static struct clksrc_sources clk_src_mout_48m = {
  66         .sources        = clk_src_mout_48m_list,
  67         .nr_sources     = ARRAY_SIZE(clk_src_mout_48m_list),
  68 };
  69
  70 static struct clksrc_clk clk_mout_48m = {
  71         .clk = {
  72                 .name           = "mout_48m",
  73         },
  74         .sources        = &clk_src_mout_48m,
  75         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
  76 };
  77
  78 static struct clksrc_clk clk_mout_mpll = {
  79         .clk = {
  80                 .name           = "mout_mpll",
  81         },
  82         .sources        = &clk_src_mpll,
  83         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  84 };
  85
  86
  87 static struct clksrc_clk clk_mout_apll = {
  88         .clk    = {
  89                 .name           = "mout_apll",
  90         },
  91         .sources        = &clk_src_apll,
  92         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  93 };
  94
  95 static struct clksrc_clk clk_mout_epll = {
  96         .clk    = {
  97                 .name           = "mout_epll",
  98         },
  99         .sources        = &clk_src_epll,
 100         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
 101 };
 102
 103 static struct clk *clk_src_mout_hpll_list[] = {
 104         [0] = &s5p_clk_27m,
 105 };
 106
 107 static struct clksrc_sources clk_src_mout_hpll = {
 108         .sources        = clk_src_mout_hpll_list,
 109         .nr_sources     = ARRAY_SIZE(clk_src_mout_hpll_list),
 110 };
 111
 112 static struct clksrc_clk clk_mout_hpll = {
 113         .clk    = {
 114                 .name           = "mout_hpll",
 115         },
 116         .sources        = &clk_src_mout_hpll,
 117         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 118 };
 119
 120 static struct clksrc_clk clk_div_apll = {
 121         .clk    = {
 122                 .name   = "div_apll",
 123                 .parent = &clk_mout_apll.clk,
 124         },
 125         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
 126 };
 127
 128 static struct clksrc_clk clk_div_arm = {
 129         .clk    = {
 130                 .name   = "div_arm",
 131                 .parent = &clk_div_apll.clk,
 132         },
 133         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 134 };
 135
 136 static struct clksrc_clk clk_div_d0_bus = {
 137         .clk    = {
 138                 .name   = "div_d0_bus",
 139                 .parent = &clk_div_arm.clk,
 140         },
 141         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
 142 };
 143
 144 static struct clksrc_clk clk_div_pclkd0 = {
 145         .clk    = {
 146                 .name   = "div_pclkd0",
 147                 .parent = &clk_div_d0_bus.clk,
 148         },
 149         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
 150 };
 151
 152 static struct clksrc_clk clk_div_secss = {
 153         .clk    = {
 154                 .name   = "div_secss",
 155                 .parent = &clk_div_d0_bus.clk,
 156         },
 157         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
 158 };
 159
 160 static struct clksrc_clk clk_div_apll2 = {
 161         .clk    = {
 162                 .name   = "div_apll2",
 163                 .parent = &clk_mout_apll.clk,
 164         },
 165         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
 166 };
 167
 168 static struct clk *clk_src_mout_am_list[] = {
 169         [0] = &clk_mout_mpll.clk,
 170         [1] = &clk_div_apll2.clk,
 171 };
 172
 173 struct clksrc_sources clk_src_mout_am = {
 174         .sources        = clk_src_mout_am_list,
 175         .nr_sources     = ARRAY_SIZE(clk_src_mout_am_list),
 176 };
 177
 178 static struct clksrc_clk clk_mout_am = {
 179         .clk    = {
 180                 .name   = "mout_am",
 181         },
 182         .sources = &clk_src_mout_am,
 183         .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
 184 };
 185
 186 static struct clksrc_clk clk_div_d1_bus = {
 187         .clk    = {
 188                 .name   = "div_d1_bus",
 189                 .parent = &clk_mout_am.clk,
 190         },
 191         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
 192 };
 193
 194 static struct clksrc_clk clk_div_mpll2 = {
 195         .clk    = {
 196                 .name   = "div_mpll2",
 197                 .parent = &clk_mout_am.clk,
 198         },
 199         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
 200 };
 201
 202 static struct clksrc_clk clk_div_mpll = {
 203         .clk    = {
 204                 .name   = "div_mpll",
 205                 .parent = &clk_mout_am.clk,
 206         },
 207         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
 208 };
 209
 210 static struct clk *clk_src_mout_onenand_list[] = {
 211         [0] = &clk_div_d0_bus.clk,
 212         [1] = &clk_div_d1_bus.clk,
 213 };
 214
 215 struct clksrc_sources clk_src_mout_onenand = {
 216         .sources        = clk_src_mout_onenand_list,
 217         .nr_sources     = ARRAY_SIZE(clk_src_mout_onenand_list),
 218 };
 219
 220 static struct clksrc_clk clk_mout_onenand = {
 221         .clk    = {
 222                 .name   = "mout_onenand",
 223         },
 224         .sources = &clk_src_mout_onenand,
 225         .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 226 };
 227
 228 static struct clksrc_clk clk_div_onenand = {
 229         .clk    = {
 230                 .name   = "div_onenand",
 231                 .parent = &clk_mout_onenand.clk,
 232         },
 233         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
 234 };
 235
 236 static struct clksrc_clk clk_div_pclkd1 = {
 237         .clk    = {
 238                 .name   = "div_pclkd1",
 239                 .parent = &clk_div_d1_bus.clk,
 240         },
 241         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
 242 };
 243
 244 static struct clksrc_clk clk_div_cam = {
 245         .clk    = {
 246                 .name   = "div_cam",
 247                 .parent = &clk_div_mpll2.clk,
 248         },
 249         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
 250 };
 251
 252 static struct clksrc_clk clk_div_hdmi = {
 253         .clk    = {
 254                 .name   = "div_hdmi",
 255                 .parent = &clk_mout_hpll.clk,
 256         },
 257         .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
 258 };
 259
 260 static u32 epll_div[][4] = {
 261         { 32750000,     131, 3, 4 },
 262         { 32768000,     131, 3, 4 },
 263         { 36000000,     72,  3, 3 },
 264         { 45000000,     90,  3, 3 },
 265         { 45158000,     90,  3, 3 },
 266         { 45158400,     90,  3, 3 },
 267         { 48000000,     96,  3, 3 },
 268         { 49125000,     131, 4, 3 },
 269         { 49152000,     131, 4, 3 },
 270         { 60000000,     120, 3, 3 },
 271         { 67737600,     226, 5, 3 },
 272         { 67738000,     226, 5, 3 },
 273         { 73800000,     246, 5, 3 },
 274         { 73728000,     246, 5, 3 },
 275         { 72000000,     144, 3, 3 },
 276         { 84000000,     168, 3, 3 },
 277         { 96000000,     96,  3, 2 },
 278         { 144000000,    144, 3, 2 },
 279         { 192000000,    96,  3, 1 }
 280 };
 281
 282 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
 283 {
 284         unsigned int epll_con;
 285         unsigned int i;
 286
 287         if (clk->rate == rate)  /* Return if nothing changed */
 288                 return 0;
 289
 290         epll_con = __raw_readl(S5P_EPLL_CON);
 291
 292         epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
 293
 294         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
 295                 if (epll_div[i][0] == rate) {
 296                         epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
 297                                     (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
 298                                     (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
 299                         break;
 300                 }
 301         }
 302
 303         if (i == ARRAY_SIZE(epll_div)) {
 304                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
 305                 return -EINVAL;
 306         }
 307
 308         __raw_writel(epll_con, S5P_EPLL_CON);
 309
 310         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
 311                         clk->rate, rate);
 312
 313         clk->rate = rate;
 314
 315         return 0;
 316 }
 317
 318 static struct clk_ops s5pc100_epll_ops = {
 319         .get_rate = s5p_epll_get_rate,
 320         .set_rate = s5pc100_epll_set_rate,
 321 };
 322
 323 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
 324 {
 325         return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
 326 }
 327
 328 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
 329 {
 330         return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
 331 }
 332
 333 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
 334 {
 335         return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
 336 }
 337
 338 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
 339 {
 340         return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
 341 }
 342
 343 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
 344 {
 345         return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
 346 }
 347
 348 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
 349 {
 350         return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
 351 }
 352
 353 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
 354 {
 355         return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
 356 }
 357
 358 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
 359 {
 360         return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
 361 }
 362
 363 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
 364 {
 365         return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
 366 }
 367
 368 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
 369 {
 370         return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
 371 }
 372
 373 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
 374 {
 375         return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
 376 }
 377
 378 /*
 379  * The following clocks will be disabled during clock initialization. It is
 380  * recommended to keep the following clocks disabled until the driver requests
 381  * for enabling the clock.
 382  */
 383 static struct clk init_clocks_off[] = {
 384         {
 385                 .name           = "cssys",
 386                 .parent         = &clk_div_d0_bus.clk,
 387                 .enable         = s5pc100_d0_0_ctrl,
 388                 .ctrlbit        = (1 << 6),
 389         }, {
 390                 .name           = "secss",
 391                 .parent         = &clk_div_d0_bus.clk,
 392                 .enable         = s5pc100_d0_0_ctrl,
 393                 .ctrlbit        = (1 << 5),
 394         }, {
 395                 .name           = "g2d",
 396                 .parent         = &clk_div_d0_bus.clk,
 397                 .enable         = s5pc100_d0_0_ctrl,
 398                 .ctrlbit        = (1 << 4),
 399         }, {
 400                 .name           = "mdma",
 401                 .parent         = &clk_div_d0_bus.clk,
 402                 .enable         = s5pc100_d0_0_ctrl,
 403                 .ctrlbit        = (1 << 3),
 404         }, {
 405                 .name           = "cfcon",
 406                 .parent         = &clk_div_d0_bus.clk,
 407                 .enable         = s5pc100_d0_0_ctrl,
 408                 .ctrlbit        = (1 << 2),
 409         }, {
 410                 .name           = "nfcon",
 411                 .parent         = &clk_div_d0_bus.clk,
 412                 .enable         = s5pc100_d0_1_ctrl,
 413                 .ctrlbit        = (1 << 3),
 414         }, {
 415                 .name           = "onenandc",
 416                 .parent         = &clk_div_d0_bus.clk,
 417                 .enable         = s5pc100_d0_1_ctrl,
 418                 .ctrlbit        = (1 << 2),
 419         }, {
 420                 .name           = "sdm",
 421                 .parent         = &clk_div_d0_bus.clk,
 422                 .enable         = s5pc100_d0_2_ctrl,
 423                 .ctrlbit        = (1 << 2),
 424         }, {
 425                 .name           = "seckey",
 426                 .parent         = &clk_div_d0_bus.clk,
 427                 .enable         = s5pc100_d0_2_ctrl,
 428                 .ctrlbit        = (1 << 1),
 429         }, {
 430                 .name           = "hsmmc",
 431                 .devname        = "s3c-sdhci.2",
 432                 .parent         = &clk_div_d1_bus.clk,
 433                 .enable         = s5pc100_d1_0_ctrl,
 434                 .ctrlbit        = (1 << 7),
 435         }, {
 436                 .name           = "hsmmc",
 437                 .devname        = "s3c-sdhci.1",
 438                 .parent         = &clk_div_d1_bus.clk,
 439                 .enable         = s5pc100_d1_0_ctrl,
 440                 .ctrlbit        = (1 << 6),
 441         }, {
 442                 .name           = "hsmmc",
 443                 .devname        = "s3c-sdhci.0",
 444                 .parent         = &clk_div_d1_bus.clk,
 445                 .enable         = s5pc100_d1_0_ctrl,
 446                 .ctrlbit        = (1 << 5),
 447         }, {
 448                 .name           = "modemif",
 449                 .parent         = &clk_div_d1_bus.clk,
 450                 .enable         = s5pc100_d1_0_ctrl,
 451                 .ctrlbit        = (1 << 4),
 452         }, {
 453                 .name           = "otg",
 454                 .parent         = &clk_div_d1_bus.clk,
 455                 .enable         = s5pc100_d1_0_ctrl,
 456                 .ctrlbit        = (1 << 3),
 457         }, {
 458                 .name           = "usbhost",
 459                 .parent         = &clk_div_d1_bus.clk,
 460                 .enable         = s5pc100_d1_0_ctrl,
 461                 .ctrlbit        = (1 << 2),
 462         }, {
 463                 .name           = "dma",
 464                 .devname        = "dma-pl330.1",
 465                 .parent         = &clk_div_d1_bus.clk,
 466                 .enable         = s5pc100_d1_0_ctrl,
 467                 .ctrlbit        = (1 << 1),
 468         }, {
 469                 .name           = "dma",
 470                 .devname        = "dma-pl330.0",
 471                 .parent         = &clk_div_d1_bus.clk,
 472                 .enable         = s5pc100_d1_0_ctrl,
 473                 .ctrlbit        = (1 << 0),
 474         }, {
 475                 .name           = "lcd",
 476                 .parent         = &clk_div_d1_bus.clk,
 477                 .enable         = s5pc100_d1_1_ctrl,
 478                 .ctrlbit        = (1 << 0),
 479         }, {
 480                 .name           = "rotator",
 481                 .parent         = &clk_div_d1_bus.clk,
 482                 .enable         = s5pc100_d1_1_ctrl,
 483                 .ctrlbit        = (1 << 1),
 484         }, {
 485                 .name           = "fimc",
 486                 .devname        = "s5p-fimc.0",
 487                 .parent         = &clk_div_d1_bus.clk,
 488                 .enable         = s5pc100_d1_1_ctrl,
 489                 .ctrlbit        = (1 << 2),
 490         }, {
 491                 .name           = "fimc",
 492                 .devname        = "s5p-fimc.1",
 493                 .parent         = &clk_div_d1_bus.clk,
 494                 .enable         = s5pc100_d1_1_ctrl,
 495                 .ctrlbit        = (1 << 3),
 496         }, {
 497                 .name           = "fimc",
 498                 .devname        = "s5p-fimc.2",
 499                 .enable         = s5pc100_d1_1_ctrl,
 500                 .ctrlbit        = (1 << 4),
 501         }, {
 502                 .name           = "jpeg",
 503                 .parent         = &clk_div_d1_bus.clk,
 504                 .enable         = s5pc100_d1_1_ctrl,
 505                 .ctrlbit        = (1 << 5),
 506         }, {
 507                 .name           = "mipi-dsim",
 508                 .parent         = &clk_div_d1_bus.clk,
 509                 .enable         = s5pc100_d1_1_ctrl,
 510                 .ctrlbit        = (1 << 6),
 511         }, {
 512                 .name           = "mipi-csis",
 513                 .parent         = &clk_div_d1_bus.clk,
 514                 .enable         = s5pc100_d1_1_ctrl,
 515                 .ctrlbit        = (1 << 7),
 516         }, {
 517                 .name           = "g3d",
 518                 .parent         = &clk_div_d1_bus.clk,
 519                 .enable         = s5pc100_d1_0_ctrl,
 520                 .ctrlbit        = (1 << 8),
 521         }, {
 522                 .name           = "tv",
 523                 .parent         = &clk_div_d1_bus.clk,
 524                 .enable         = s5pc100_d1_2_ctrl,
 525                 .ctrlbit        = (1 << 0),
 526         }, {
 527                 .name           = "vp",
 528                 .parent         = &clk_div_d1_bus.clk,
 529                 .enable         = s5pc100_d1_2_ctrl,
 530                 .ctrlbit        = (1 << 1),
 531         }, {
 532                 .name           = "mixer",
 533                 .parent         = &clk_div_d1_bus.clk,
 534                 .enable         = s5pc100_d1_2_ctrl,
 535                 .ctrlbit        = (1 << 2),
 536         }, {
 537                 .name           = "hdmi",
 538                 .parent         = &clk_div_d1_bus.clk,
 539                 .enable         = s5pc100_d1_2_ctrl,
 540                 .ctrlbit        = (1 << 3),
 541         }, {
 542                 .name           = "mfc",
 543                 .parent         = &clk_div_d1_bus.clk,
 544                 .enable         = s5pc100_d1_2_ctrl,
 545                 .ctrlbit        = (1 << 4),
 546         }, {
 547                 .name           = "apc",
 548                 .parent         = &clk_div_d1_bus.clk,
 549                 .enable         = s5pc100_d1_3_ctrl,
 550                 .ctrlbit        = (1 << 2),
 551         }, {
 552                 .name           = "iec",
 553                 .parent         = &clk_div_d1_bus.clk,
 554                 .enable         = s5pc100_d1_3_ctrl,
 555                 .ctrlbit        = (1 << 3),
 556         }, {
 557                 .name           = "systimer",
 558                 .parent         = &clk_div_d1_bus.clk,
 559                 .enable         = s5pc100_d1_3_ctrl,
 560                 .ctrlbit        = (1 << 7),
 561         }, {
 562                 .name           = "watchdog",
 563                 .parent         = &clk_div_d1_bus.clk,
 564                 .enable         = s5pc100_d1_3_ctrl,
 565                 .ctrlbit        = (1 << 8),
 566         }, {
 567                 .name           = "rtc",
 568                 .parent         = &clk_div_d1_bus.clk,
 569                 .enable         = s5pc100_d1_3_ctrl,
 570                 .ctrlbit        = (1 << 9),
 571         }, {
 572                 .name           = "i2c",
 573                 .devname        = "s3c2440-i2c.0",
 574                 .parent         = &clk_div_d1_bus.clk,
 575                 .enable         = s5pc100_d1_4_ctrl,
 576                 .ctrlbit        = (1 << 4),
 577         }, {
 578                 .name           = "i2c",
 579                 .devname        = "s3c2440-i2c.1",
 580                 .parent         = &clk_div_d1_bus.clk,
 581                 .enable         = s5pc100_d1_4_ctrl,
 582                 .ctrlbit        = (1 << 5),
 583         }, {
 584                 .name           = "spi",
 585                 .devname        = "s3c64xx-spi.0",
 586                 .parent         = &clk_div_d1_bus.clk,
 587                 .enable         = s5pc100_d1_4_ctrl,
 588                 .ctrlbit        = (1 << 6),
 589         }, {
 590                 .name           = "spi",
 591                 .devname        = "s3c64xx-spi.1",
 592                 .parent         = &clk_div_d1_bus.clk,
 593                 .enable         = s5pc100_d1_4_ctrl,
 594                 .ctrlbit        = (1 << 7),
 595         }, {
 596                 .name           = "spi",
 597                 .devname        = "s3c64xx-spi.2",
 598                 .parent         = &clk_div_d1_bus.clk,
 599                 .enable         = s5pc100_d1_4_ctrl,
 600                 .ctrlbit        = (1 << 8),
 601         }, {
 602                 .name           = "irda",
 603                 .parent         = &clk_div_d1_bus.clk,
 604                 .enable         = s5pc100_d1_4_ctrl,
 605                 .ctrlbit        = (1 << 9),
 606         }, {
 607                 .name           = "ccan",
 608                 .parent         = &clk_div_d1_bus.clk,
 609                 .enable         = s5pc100_d1_4_ctrl,
 610                 .ctrlbit        = (1 << 10),
 611         }, {
 612                 .name           = "ccan",
 613                 .parent         = &clk_div_d1_bus.clk,
 614                 .enable         = s5pc100_d1_4_ctrl,
 615                 .ctrlbit        = (1 << 11),
 616         }, {
 617                 .name           = "hsitx",
 618                 .parent         = &clk_div_d1_bus.clk,
 619                 .enable         = s5pc100_d1_4_ctrl,
 620                 .ctrlbit        = (1 << 12),
 621         }, {
 622                 .name           = "hsirx",
 623                 .parent         = &clk_div_d1_bus.clk,
 624                 .enable         = s5pc100_d1_4_ctrl,
 625                 .ctrlbit        = (1 << 13),
 626         }, {
 627                 .name           = "iis",
 628                 .devname        = "samsung-i2s.0",
 629                 .parent         = &clk_div_pclkd1.clk,
 630                 .enable         = s5pc100_d1_5_ctrl,
 631                 .ctrlbit        = (1 << 0),
 632         }, {
 633                 .name           = "iis",
 634                 .devname        = "samsung-i2s.1",
 635                 .parent         = &clk_div_pclkd1.clk,
 636                 .enable         = s5pc100_d1_5_ctrl,
 637                 .ctrlbit        = (1 << 1),
 638         }, {
 639                 .name           = "iis",
 640                 .devname        = "samsung-i2s.2",
 641                 .parent         = &clk_div_pclkd1.clk,
 642                 .enable         = s5pc100_d1_5_ctrl,
 643                 .ctrlbit        = (1 << 2),
 644         }, {
 645                 .name           = "ac97",
 646                 .parent         = &clk_div_pclkd1.clk,
 647                 .enable         = s5pc100_d1_5_ctrl,
 648                 .ctrlbit        = (1 << 3),
 649         }, {
 650                 .name           = "pcm",
 651                 .devname        = "samsung-pcm.0",
 652                 .parent         = &clk_div_pclkd1.clk,
 653                 .enable         = s5pc100_d1_5_ctrl,
 654                 .ctrlbit        = (1 << 4),
 655         }, {
 656                 .name           = "pcm",
 657                 .devname        = "samsung-pcm.1",
 658                 .parent         = &clk_div_pclkd1.clk,
 659                 .enable         = s5pc100_d1_5_ctrl,
 660                 .ctrlbit        = (1 << 5),
 661         }, {
 662                 .name           = "spdif",
 663                 .parent         = &clk_div_pclkd1.clk,
 664                 .enable         = s5pc100_d1_5_ctrl,
 665                 .ctrlbit        = (1 << 6),
 666         }, {
 667                 .name           = "adc",
 668                 .parent         = &clk_div_pclkd1.clk,
 669                 .enable         = s5pc100_d1_5_ctrl,
 670                 .ctrlbit        = (1 << 7),
 671         }, {
 672                 .name           = "keypad",
 673                 .parent         = &clk_div_pclkd1.clk,
 674                 .enable         = s5pc100_d1_5_ctrl,
 675                 .ctrlbit        = (1 << 8),
 676         }, {
 677                 .name           = "spi_48m",
 678                 .devname        = "s3c64xx-spi.0",
 679                 .parent         = &clk_mout_48m.clk,
 680                 .enable         = s5pc100_sclk0_ctrl,
 681                 .ctrlbit        = (1 << 7),
 682         }, {
 683                 .name           = "spi_48m",
 684                 .devname        = "s3c64xx-spi.1",
 685                 .parent         = &clk_mout_48m.clk,
 686                 .enable         = s5pc100_sclk0_ctrl,
 687                 .ctrlbit        = (1 << 8),
 688         }, {
 689                 .name           = "spi_48m",
 690                 .devname        = "s3c64xx-spi.2",
 691                 .parent         = &clk_mout_48m.clk,
 692                 .enable         = s5pc100_sclk0_ctrl,
 693                 .ctrlbit        = (1 << 9),
 694         }, {
 695                 .name           = "mmc_48m",
 696                 .devname        = "s3c-sdhci.0",
 697                 .parent         = &clk_mout_48m.clk,
 698                 .enable         = s5pc100_sclk0_ctrl,
 699                 .ctrlbit        = (1 << 15),
 700         }, {
 701                 .name           = "mmc_48m",
 702                 .devname        = "s3c-sdhci.1",
 703                 .parent         = &clk_mout_48m.clk,
 704                 .enable         = s5pc100_sclk0_ctrl,
 705                 .ctrlbit        = (1 << 16),
 706         }, {
 707                 .name           = "mmc_48m",
 708                 .devname        = "s3c-sdhci.2",
 709                 .parent         = &clk_mout_48m.clk,
 710                 .enable         = s5pc100_sclk0_ctrl,
 711                 .ctrlbit        = (1 << 17),
 712         },
 713 };
 714
 715 static struct clk clk_vclk54m = {
 716         .name           = "vclk_54m",
 717         .rate           = 54000000,
 718 };
 719
 720 static struct clk clk_i2scdclk0 = {
 721         .name           = "i2s_cdclk0",
 722 };
 723
 724 static struct clk clk_i2scdclk1 = {
 725         .name           = "i2s_cdclk1",
 726 };
 727
 728 static struct clk clk_i2scdclk2 = {
 729         .name           = "i2s_cdclk2",
 730 };
 731
 732 static struct clk clk_pcmcdclk0 = {
 733         .name           = "pcm_cdclk0",
 734 };
 735
 736 static struct clk clk_pcmcdclk1 = {
 737         .name           = "pcm_cdclk1",
 738 };
 739
 740 static struct clk *clk_src_group1_list[] = {
 741         [0] = &clk_mout_epll.clk,
 742         [1] = &clk_div_mpll2.clk,
 743         [2] = &clk_fin_epll,
 744         [3] = &clk_mout_hpll.clk,
 745 };
 746
 747 struct clksrc_sources clk_src_group1 = {
 748         .sources        = clk_src_group1_list,
 749         .nr_sources     = ARRAY_SIZE(clk_src_group1_list),
 750 };
 751
 752 static struct clk *clk_src_group2_list[] = {
 753         [0] = &clk_mout_epll.clk,
 754         [1] = &clk_div_mpll.clk,
 755 };
 756
 757 struct clksrc_sources clk_src_group2 = {
 758         .sources        = clk_src_group2_list,
 759         .nr_sources     = ARRAY_SIZE(clk_src_group2_list),
 760 };
 761
 762 static struct clk *clk_src_group3_list[] = {
 763         [0] = &clk_mout_epll.clk,
 764         [1] = &clk_div_mpll.clk,
 765         [2] = &clk_fin_epll,
 766         [3] = &clk_i2scdclk0,
 767         [4] = &clk_pcmcdclk0,
 768         [5] = &clk_mout_hpll.clk,
 769 };
 770
 771 struct clksrc_sources clk_src_group3 = {
 772         .sources        = clk_src_group3_list,
 773         .nr_sources     = ARRAY_SIZE(clk_src_group3_list),
 774 };
 775
 776 static struct clksrc_clk clk_sclk_audio0 = {
 777         .clk    = {
 778                 .name           = "sclk_audio",
 779                 .devname        = "samsung-pcm.0",
 780                 .ctrlbit        = (1 << 8),
 781                 .enable         = s5pc100_sclk1_ctrl,
 782         },
 783         .sources = &clk_src_group3,
 784         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
 785         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
 786 };
 787
 788 static struct clk *clk_src_group4_list[] = {
 789         [0] = &clk_mout_epll.clk,
 790         [1] = &clk_div_mpll.clk,
 791         [2] = &clk_fin_epll,
 792         [3] = &clk_i2scdclk1,
 793         [4] = &clk_pcmcdclk1,
 794         [5] = &clk_mout_hpll.clk,
 795 };
 796
 797 struct clksrc_sources clk_src_group4 = {
 798         .sources        = clk_src_group4_list,
 799         .nr_sources     = ARRAY_SIZE(clk_src_group4_list),
 800 };
 801
 802 static struct clksrc_clk clk_sclk_audio1 = {
 803         .clk    = {
 804                 .name           = "sclk_audio",
 805                 .devname        = "samsung-pcm.1",
 806                 .ctrlbit        = (1 << 9),
 807                 .enable         = s5pc100_sclk1_ctrl,
 808         },
 809         .sources = &clk_src_group4,
 810         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
 811         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 812 };
 813
 814 static struct clk *clk_src_group5_list[] = {
 815         [0] = &clk_mout_epll.clk,
 816         [1] = &clk_div_mpll.clk,
 817         [2] = &clk_fin_epll,
 818         [3] = &clk_i2scdclk2,
 819         [4] = &clk_mout_hpll.clk,
 820 };
 821
 822 struct clksrc_sources clk_src_group5 = {
 823         .sources        = clk_src_group5_list,
 824         .nr_sources     = ARRAY_SIZE(clk_src_group5_list),
 825 };
 826
 827 static struct clksrc_clk clk_sclk_audio2 = {
 828         .clk    = {
 829                 .name           = "sclk_audio",
 830                 .devname        = "samsung-pcm.2",
 831                 .ctrlbit        = (1 << 10),
 832                 .enable         = s5pc100_sclk1_ctrl,
 833         },
 834         .sources = &clk_src_group5,
 835         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
 836         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
 837 };
 838
 839 static struct clk *clk_src_group6_list[] = {
 840         [0] = &s5p_clk_27m,
 841         [1] = &clk_vclk54m,
 842         [2] = &clk_div_hdmi.clk,
 843 };
 844
 845 struct clksrc_sources clk_src_group6 = {
 846         .sources        = clk_src_group6_list,
 847         .nr_sources     = ARRAY_SIZE(clk_src_group6_list),
 848 };
 849
 850 static struct clk *clk_src_group7_list[] = {
 851         [0] = &clk_mout_epll.clk,
 852         [1] = &clk_div_mpll.clk,
 853         [2] = &clk_mout_hpll.clk,
 854         [3] = &clk_vclk54m,
 855 };
 856
 857 struct clksrc_sources clk_src_group7 = {
 858         .sources        = clk_src_group7_list,
 859         .nr_sources     = ARRAY_SIZE(clk_src_group7_list),
 860 };
 861
 862 static struct clk *clk_src_mmc0_list[] = {
 863         [0] = &clk_mout_epll.clk,
 864         [1] = &clk_div_mpll.clk,
 865         [2] = &clk_fin_epll,
 866 };
 867
 868 struct clksrc_sources clk_src_mmc0 = {
 869         .sources        = clk_src_mmc0_list,
 870         .nr_sources     = ARRAY_SIZE(clk_src_mmc0_list),
 871 };
 872
 873 static struct clk *clk_src_mmc12_list[] = {
 874         [0] = &clk_mout_epll.clk,
 875         [1] = &clk_div_mpll.clk,
 876         [2] = &clk_fin_epll,
 877         [3] = &clk_mout_hpll.clk,
 878 };
 879
 880 struct clksrc_sources clk_src_mmc12 = {
 881         .sources        = clk_src_mmc12_list,
 882         .nr_sources     = ARRAY_SIZE(clk_src_mmc12_list),
 883 };
 884
 885 static struct clk *clk_src_irda_usb_list[] = {
 886         [0] = &clk_mout_epll.clk,
 887         [1] = &clk_div_mpll.clk,
 888         [2] = &clk_fin_epll,
 889         [3] = &clk_mout_hpll.clk,
 890 };
 891
 892 struct clksrc_sources clk_src_irda_usb = {
 893         .sources        = clk_src_irda_usb_list,
 894         .nr_sources     = ARRAY_SIZE(clk_src_irda_usb_list),
 895 };
 896
 897 static struct clk *clk_src_pwi_list[] = {
 898         [0] = &clk_fin_epll,
 899         [1] = &clk_mout_epll.clk,
 900         [2] = &clk_div_mpll.clk,
 901 };
 902
 903 struct clksrc_sources clk_src_pwi = {
 904         .sources        = clk_src_pwi_list,
 905         .nr_sources     = ARRAY_SIZE(clk_src_pwi_list),
 906 };
 907
 908 static struct clk *clk_sclk_spdif_list[] = {
 909         [0] = &clk_sclk_audio0.clk,
 910         [1] = &clk_sclk_audio1.clk,
 911         [2] = &clk_sclk_audio2.clk,
 912 };
 913
 914 struct clksrc_sources clk_src_sclk_spdif = {
 915         .sources        = clk_sclk_spdif_list,
 916         .nr_sources     = ARRAY_SIZE(clk_sclk_spdif_list),
 917 };
 918
 919 static struct clksrc_clk clk_sclk_spdif = {
 920         .clk    = {
 921                 .name           = "sclk_spdif",
 922                 .ctrlbit        = (1 << 11),
 923                 .enable         = s5pc100_sclk1_ctrl,
 924                 .ops            = &s5p_sclk_spdif_ops,
 925         },
 926         .sources = &clk_src_sclk_spdif,
 927         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
 928 };
 929
 930 static struct clksrc_clk clksrcs[] = {
 931         {
 932                 .clk    = {
 933                         .name           = "sclk_spi",
 934                         .devname        = "s3c64xx-spi.0",
 935                         .ctrlbit        = (1 << 4),
 936                         .enable         = s5pc100_sclk0_ctrl,
 937
 938                 },
 939                 .sources = &clk_src_group1,
 940                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
 941                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
 942         }, {
 943                 .clk    = {
 944                         .name           = "sclk_spi",
 945                         .devname        = "s3c64xx-spi.1",
 946                         .ctrlbit        = (1 << 5),
 947                         .enable         = s5pc100_sclk0_ctrl,
 948
 949                 },
 950                 .sources = &clk_src_group1,
 951                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
 952                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
 953         }, {
 954                 .clk    = {
 955                         .name           = "sclk_spi",
 956                         .devname        = "s3c64xx-spi.2",
 957                         .ctrlbit        = (1 << 6),
 958                         .enable         = s5pc100_sclk0_ctrl,
 959
 960                 },
 961                 .sources = &clk_src_group1,
 962                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
 963                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
 964         }, {
 965                 .clk    = {
 966                         .name           = "uclk1",
 967                         .ctrlbit        = (1 << 3),
 968                         .enable         = s5pc100_sclk0_ctrl,
 969
 970                 },
 971                 .sources = &clk_src_group2,
 972                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 973                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 974         }, {
 975                 .clk    = {
 976                         .name           = "sclk_mixer",
 977                         .ctrlbit        = (1 << 6),
 978                         .enable         = s5pc100_sclk0_ctrl,
 979
 980                 },
 981                 .sources = &clk_src_group6,
 982                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
 983         }, {
 984                 .clk    = {
 985                         .name           = "sclk_lcd",
 986                         .ctrlbit        = (1 << 0),
 987                         .enable         = s5pc100_sclk1_ctrl,
 988
 989                 },
 990                 .sources = &clk_src_group7,
 991                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
 992                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 993         }, {
 994                 .clk    = {
 995                         .name           = "sclk_fimc",
 996                         .devname        = "s5p-fimc.0",
 997                         .ctrlbit        = (1 << 1),
 998                         .enable         = s5pc100_sclk1_ctrl,
 999
1000                 },
1001                 .sources = &clk_src_group7,
1002                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
1003                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
1004         }, {
1005                 .clk    = {
1006                         .name           = "sclk_fimc",
1007                         .devname        = "s5p-fimc.1",
1008                         .ctrlbit        = (1 << 2),
1009                         .enable         = s5pc100_sclk1_ctrl,
1010
1011                 },
1012                 .sources = &clk_src_group7,
1013                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1014                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1015         }, {
1016                 .clk    = {
1017                         .name           = "sclk_fimc",
1018                         .devname        = "s5p-fimc.2",
1019                         .ctrlbit        = (1 << 3),
1020                         .enable         = s5pc100_sclk1_ctrl,
1021
1022                 },
1023                 .sources = &clk_src_group7,
1024                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1025                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1026         }, {
1027                 .clk    = {
1028                         .name           = "sclk_mmc",
1029                         .devname        = "s3c-sdhci.0",
1030                         .ctrlbit        = (1 << 12),
1031                         .enable         = s5pc100_sclk1_ctrl,
1032
1033                 },
1034                 .sources = &clk_src_mmc0,
1035                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1036                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1037         }, {
1038                 .clk    = {
1039                         .name           = "sclk_mmc",
1040                         .devname        = "s3c-sdhci.1",
1041                         .ctrlbit        = (1 << 13),
1042                         .enable         = s5pc100_sclk1_ctrl,
1043
1044                 },
1045                 .sources = &clk_src_mmc12,
1046                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1047                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1048         }, {
1049                 .clk    = {
1050                         .name           = "sclk_mmc",
1051                         .devname        = "s3c-sdhci.2",
1052                         .ctrlbit        = (1 << 14),
1053                         .enable         = s5pc100_sclk1_ctrl,
1054
1055                 },
1056                 .sources = &clk_src_mmc12,
1057                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1058                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1059         }, {
1060                 .clk    = {
1061                         .name           = "sclk_irda",
1062                         .ctrlbit        = (1 << 10),
1063                         .enable         = s5pc100_sclk0_ctrl,
1064
1065                 },
1066                 .sources = &clk_src_irda_usb,
1067                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1068                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1069         }, {
1070                 .clk    = {
1071                         .name           = "sclk_irda",
1072                         .ctrlbit        = (1 << 10),
1073                         .enable         = s5pc100_sclk0_ctrl,
1074
1075                 },
1076                 .sources = &clk_src_mmc12,
1077                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1078                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1079         }, {
1080                 .clk    = {
1081                         .name           = "sclk_pwi",
1082                         .ctrlbit        = (1 << 1),
1083                         .enable         = s5pc100_sclk0_ctrl,
1084
1085                 },
1086                 .sources = &clk_src_pwi,
1087                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1088                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1089         }, {
1090                 .clk    = {
1091                         .name           = "sclk_uhost",
1092                         .ctrlbit        = (1 << 11),
1093                         .enable         = s5pc100_sclk0_ctrl,
1094
1095                 },
1096                 .sources = &clk_src_irda_usb,
1097                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1098                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1099         },
1100 };
1101
1102 /* Clock initialisation code */
1103 static struct clksrc_clk *sysclks[] = {
1104         &clk_mout_apll,
1105         &clk_mout_epll,
1106         &clk_mout_mpll,
1107         &clk_mout_hpll,
1108         &clk_mout_href,
1109         &clk_mout_48m,
1110         &clk_div_apll,
1111         &clk_div_arm,
1112         &clk_div_d0_bus,
1113         &clk_div_pclkd0,
1114         &clk_div_secss,
1115         &clk_div_apll2,
1116         &clk_mout_am,
1117         &clk_div_d1_bus,
1118         &clk_div_mpll2,
1119         &clk_div_mpll,
1120         &clk_mout_onenand,
1121         &clk_div_onenand,
1122         &clk_div_pclkd1,
1123         &clk_div_cam,
1124         &clk_div_hdmi,
1125         &clk_sclk_audio0,
1126         &clk_sclk_audio1,
1127         &clk_sclk_audio2,
1128         &clk_sclk_spdif,
1129 };
1130
1131 void __init_or_cpufreq s5pc100_setup_clocks(void)
1132 {
1133         unsigned long xtal;
1134         unsigned long arm;
1135         unsigned long hclkd0;
1136         unsigned long hclkd1;
1137         unsigned long pclkd0;
1138         unsigned long pclkd1;
1139         unsigned long apll;
1140         unsigned long mpll;
1141         unsigned long epll;
1142         unsigned long hpll;
1143         unsigned int ptr;
1144
1145         /* Set S5PC100 functions for clk_fout_epll */
1146         clk_fout_epll.enable = s5p_epll_enable;
1147         clk_fout_epll.ops = &s5pc100_epll_ops;
1148
1149         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1150
1151         xtal = clk_get_rate(&clk_xtal);
1152
1153         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1154
1155         apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1156         mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1157         epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1158         hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1159
1160         printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1161                         print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1162
1163         clk_fout_apll.rate = apll;
1164         clk_fout_mpll.rate = mpll;
1165         clk_fout_epll.rate = epll;
1166         clk_mout_hpll.clk.rate = hpll;
1167
1168         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1169                 s3c_set_clksrc(&clksrcs[ptr], true);
1170
1171         arm = clk_get_rate(&clk_div_arm.clk);
1172         hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1173         pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1174         hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1175         pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1176
1177         printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1178                         print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1179
1180         clk_f.rate = arm;
1181         clk_h.rate = hclkd1;
1182         clk_p.rate = pclkd1;
1183 }
1184
1185 /*
1186  * The following clocks will be enabled during clock initialization.
1187  */
1188 static struct clk init_clocks[] = {
1189         {
1190                 .name           = "tzic",
1191                 .parent         = &clk_div_d0_bus.clk,
1192                 .enable         = s5pc100_d0_0_ctrl,
1193                 .ctrlbit        = (1 << 1),
1194         }, {
1195                 .name           = "intc",
1196                 .parent         = &clk_div_d0_bus.clk,
1197                 .enable         = s5pc100_d0_0_ctrl,
1198                 .ctrlbit        = (1 << 0),
1199         }, {
1200                 .name           = "ebi",
1201                 .parent         = &clk_div_d0_bus.clk,
1202                 .enable         = s5pc100_d0_1_ctrl,
1203                 .ctrlbit        = (1 << 5),
1204         }, {
1205                 .name           = "intmem",
1206                 .parent         = &clk_div_d0_bus.clk,
1207                 .enable         = s5pc100_d0_1_ctrl,
1208                 .ctrlbit        = (1 << 4),
1209         }, {
1210                 .name           = "sromc",
1211                 .parent         = &clk_div_d0_bus.clk,
1212                 .enable         = s5pc100_d0_1_ctrl,
1213                 .ctrlbit        = (1 << 1),
1214         }, {
1215                 .name           = "dmc",
1216                 .parent         = &clk_div_d0_bus.clk,
1217                 .enable         = s5pc100_d0_1_ctrl,
1218                 .ctrlbit        = (1 << 0),
1219         }, {
1220                 .name           = "chipid",
1221                 .parent         = &clk_div_d0_bus.clk,
1222                 .enable         = s5pc100_d0_1_ctrl,
1223                 .ctrlbit        = (1 << 0),
1224         }, {
1225                 .name           = "gpio",
1226                 .parent         = &clk_div_d1_bus.clk,
1227                 .enable         = s5pc100_d1_3_ctrl,
1228                 .ctrlbit        = (1 << 1),
1229         }, {
1230                 .name           = "uart",
1231                 .devname        = "s3c6400-uart.0",
1232                 .parent         = &clk_div_d1_bus.clk,
1233                 .enable         = s5pc100_d1_4_ctrl,
1234                 .ctrlbit        = (1 << 0),
1235         }, {
1236                 .name           = "uart",
1237                 .devname        = "s3c6400-uart.1",
1238                 .parent         = &clk_div_d1_bus.clk,
1239                 .enable         = s5pc100_d1_4_ctrl,
1240                 .ctrlbit        = (1 << 1),
1241         }, {
1242                 .name           = "uart",
1243                 .devname        = "s3c6400-uart.2",
1244                 .parent         = &clk_div_d1_bus.clk,
1245                 .enable         = s5pc100_d1_4_ctrl,
1246                 .ctrlbit        = (1 << 2),
1247         }, {
1248                 .name           = "uart",
1249                 .devname        = "s3c6400-uart.3",
1250                 .parent         = &clk_div_d1_bus.clk,
1251                 .enable         = s5pc100_d1_4_ctrl,
1252                 .ctrlbit        = (1 << 3),
1253         }, {
1254                 .name           = "timers",
1255                 .parent         = &clk_div_d1_bus.clk,
1256                 .enable         = s5pc100_d1_3_ctrl,
1257                 .ctrlbit        = (1 << 6),
1258         },
1259 };
1260
1261 static struct clk *clks[] __initdata = {
1262         &clk_ext,
1263         &clk_i2scdclk0,
1264         &clk_i2scdclk1,
1265         &clk_i2scdclk2,
1266         &clk_pcmcdclk0,
1267         &clk_pcmcdclk1,
1268 };
1269
1270 void __init s5pc100_register_clocks(void)
1271 {
1272         int ptr;
1273
1274         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1275
1276         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1277                 s3c_register_clksrc(sysclks[ptr], 1);
1278
1279         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1280         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1281
1282         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1283         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1284
1285         s3c24xx_register_clock(&dummy_apb_pclk);
1286
1287         s3c_pwmclk_init();
1288 }