1 /* linux/arch/arm/mach-s5pc100/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PC100 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
23 #include <plat/cpu-freq.h>
24 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
28 #include <plat/s5p-clock.h>
29 #include <plat/clock-clksrc.h>
30 #include <plat/s5pc100.h>
32 static struct clk s5p_clk_otgphy = {
36 static struct clk *clk_src_mout_href_list[] = {
41 static struct clksrc_sources clk_src_mout_href = {
42 .sources = clk_src_mout_href_list,
43 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
46 static struct clksrc_clk clk_mout_href = {
50 .sources = &clk_src_mout_href,
51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
54 static struct clk *clk_src_mout_48m_list[] = {
56 [1] = &s5p_clk_otgphy,
59 static struct clksrc_sources clk_src_mout_48m = {
60 .sources = clk_src_mout_48m_list,
61 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
64 static struct clksrc_clk clk_mout_48m = {
68 .sources = &clk_src_mout_48m,
69 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
72 static struct clksrc_clk clk_mout_mpll = {
76 .sources = &clk_src_mpll,
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
81 static struct clksrc_clk clk_mout_apll = {
85 .sources = &clk_src_apll,
86 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
89 static struct clksrc_clk clk_mout_epll = {
93 .sources = &clk_src_epll,
94 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
97 static struct clk *clk_src_mout_hpll_list[] = {
101 static struct clksrc_sources clk_src_mout_hpll = {
102 .sources = clk_src_mout_hpll_list,
103 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
106 static struct clksrc_clk clk_mout_hpll = {
110 .sources = &clk_src_mout_hpll,
111 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
114 static struct clksrc_clk clk_div_apll = {
117 .parent = &clk_mout_apll.clk,
119 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
122 static struct clksrc_clk clk_div_arm = {
125 .parent = &clk_div_apll.clk,
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
130 static struct clksrc_clk clk_div_d0_bus = {
132 .name = "div_d0_bus",
133 .parent = &clk_div_arm.clk,
135 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
138 static struct clksrc_clk clk_div_pclkd0 = {
140 .name = "div_pclkd0",
141 .parent = &clk_div_d0_bus.clk,
143 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
146 static struct clksrc_clk clk_div_secss = {
149 .parent = &clk_div_d0_bus.clk,
151 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
154 static struct clksrc_clk clk_div_apll2 = {
157 .parent = &clk_mout_apll.clk,
159 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
162 static struct clk *clk_src_mout_am_list[] = {
163 [0] = &clk_mout_mpll.clk,
164 [1] = &clk_div_apll2.clk,
167 struct clksrc_sources clk_src_mout_am = {
168 .sources = clk_src_mout_am_list,
169 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
172 static struct clksrc_clk clk_mout_am = {
176 .sources = &clk_src_mout_am,
177 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
180 static struct clksrc_clk clk_div_d1_bus = {
182 .name = "div_d1_bus",
183 .parent = &clk_mout_am.clk,
185 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
188 static struct clksrc_clk clk_div_mpll2 = {
191 .parent = &clk_mout_am.clk,
193 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
196 static struct clksrc_clk clk_div_mpll = {
199 .parent = &clk_mout_am.clk,
201 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
204 static struct clk *clk_src_mout_onenand_list[] = {
205 [0] = &clk_div_d0_bus.clk,
206 [1] = &clk_div_d1_bus.clk,
209 struct clksrc_sources clk_src_mout_onenand = {
210 .sources = clk_src_mout_onenand_list,
211 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
214 static struct clksrc_clk clk_mout_onenand = {
216 .name = "mout_onenand",
218 .sources = &clk_src_mout_onenand,
219 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
222 static struct clksrc_clk clk_div_onenand = {
224 .name = "div_onenand",
225 .parent = &clk_mout_onenand.clk,
227 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
230 static struct clksrc_clk clk_div_pclkd1 = {
232 .name = "div_pclkd1",
233 .parent = &clk_div_d1_bus.clk,
235 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
238 static struct clksrc_clk clk_div_cam = {
241 .parent = &clk_div_mpll2.clk,
243 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
246 static struct clksrc_clk clk_div_hdmi = {
249 .parent = &clk_mout_hpll.clk,
251 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
254 static u32 epll_div[][4] = {
255 { 32750000, 131, 3, 4 },
256 { 32768000, 131, 3, 4 },
257 { 36000000, 72, 3, 3 },
258 { 45000000, 90, 3, 3 },
259 { 45158000, 90, 3, 3 },
260 { 45158400, 90, 3, 3 },
261 { 48000000, 96, 3, 3 },
262 { 49125000, 131, 4, 3 },
263 { 49152000, 131, 4, 3 },
264 { 60000000, 120, 3, 3 },
265 { 67737600, 226, 5, 3 },
266 { 67738000, 226, 5, 3 },
267 { 73800000, 246, 5, 3 },
268 { 73728000, 246, 5, 3 },
269 { 72000000, 144, 3, 3 },
270 { 84000000, 168, 3, 3 },
271 { 96000000, 96, 3, 2 },
272 { 144000000, 144, 3, 2 },
273 { 192000000, 96, 3, 1 }
276 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
278 unsigned int epll_con;
281 if (clk->rate == rate) /* Return if nothing changed */
284 epll_con = __raw_readl(S5P_EPLL_CON);
286 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
288 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
289 if (epll_div[i][0] == rate) {
290 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
291 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
292 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
297 if (i == ARRAY_SIZE(epll_div)) {
298 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
302 __raw_writel(epll_con, S5P_EPLL_CON);
304 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
312 static struct clk_ops s5pc100_epll_ops = {
313 .get_rate = s5p_epll_get_rate,
314 .set_rate = s5pc100_epll_set_rate,
317 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
319 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
322 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
324 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
327 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
329 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
332 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
334 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
337 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
339 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
342 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
344 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
347 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
349 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
352 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
354 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
357 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
359 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
362 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
364 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
367 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
369 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
373 * The following clocks will be disabled during clock initialization. It is
374 * recommended to keep the following clocks disabled until the driver requests
375 * for enabling the clock.
377 static struct clk init_clocks_off[] = {
380 .parent = &clk_div_d0_bus.clk,
381 .enable = s5pc100_d0_0_ctrl,
385 .parent = &clk_div_d0_bus.clk,
386 .enable = s5pc100_d0_0_ctrl,
390 .parent = &clk_div_d0_bus.clk,
391 .enable = s5pc100_d0_0_ctrl,
395 .parent = &clk_div_d0_bus.clk,
396 .enable = s5pc100_d0_0_ctrl,
400 .parent = &clk_div_d0_bus.clk,
401 .enable = s5pc100_d0_0_ctrl,
405 .parent = &clk_div_d0_bus.clk,
406 .enable = s5pc100_d0_1_ctrl,
410 .parent = &clk_div_d0_bus.clk,
411 .enable = s5pc100_d0_1_ctrl,
415 .parent = &clk_div_d0_bus.clk,
416 .enable = s5pc100_d0_2_ctrl,
420 .parent = &clk_div_d0_bus.clk,
421 .enable = s5pc100_d0_2_ctrl,
425 .devname = "s3c-sdhci.2",
426 .parent = &clk_div_d1_bus.clk,
427 .enable = s5pc100_d1_0_ctrl,
431 .devname = "s3c-sdhci.1",
432 .parent = &clk_div_d1_bus.clk,
433 .enable = s5pc100_d1_0_ctrl,
437 .devname = "s3c-sdhci.0",
438 .parent = &clk_div_d1_bus.clk,
439 .enable = s5pc100_d1_0_ctrl,
443 .parent = &clk_div_d1_bus.clk,
444 .enable = s5pc100_d1_0_ctrl,
448 .parent = &clk_div_d1_bus.clk,
449 .enable = s5pc100_d1_0_ctrl,
453 .parent = &clk_div_d1_bus.clk,
454 .enable = s5pc100_d1_0_ctrl,
458 .devname = "s3c-pl330.1",
459 .parent = &clk_div_d1_bus.clk,
460 .enable = s5pc100_d1_0_ctrl,
464 .devname = "s3c-pl330.0",
465 .parent = &clk_div_d1_bus.clk,
466 .enable = s5pc100_d1_0_ctrl,
470 .parent = &clk_div_d1_bus.clk,
471 .enable = s5pc100_d1_1_ctrl,
475 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_1_ctrl,
480 .devname = "s5p-fimc.0",
481 .parent = &clk_div_d1_bus.clk,
482 .enable = s5pc100_d1_1_ctrl,
486 .devname = "s5p-fimc.1",
487 .parent = &clk_div_d1_bus.clk,
488 .enable = s5pc100_d1_1_ctrl,
492 .devname = "s5p-fimc.2",
493 .enable = s5pc100_d1_1_ctrl,
497 .parent = &clk_div_d1_bus.clk,
498 .enable = s5pc100_d1_1_ctrl,
502 .parent = &clk_div_d1_bus.clk,
503 .enable = s5pc100_d1_1_ctrl,
507 .parent = &clk_div_d1_bus.clk,
508 .enable = s5pc100_d1_1_ctrl,
512 .parent = &clk_div_d1_bus.clk,
513 .enable = s5pc100_d1_0_ctrl,
517 .parent = &clk_div_d1_bus.clk,
518 .enable = s5pc100_d1_2_ctrl,
522 .parent = &clk_div_d1_bus.clk,
523 .enable = s5pc100_d1_2_ctrl,
527 .parent = &clk_div_d1_bus.clk,
528 .enable = s5pc100_d1_2_ctrl,
532 .parent = &clk_div_d1_bus.clk,
533 .enable = s5pc100_d1_2_ctrl,
537 .parent = &clk_div_d1_bus.clk,
538 .enable = s5pc100_d1_2_ctrl,
542 .parent = &clk_div_d1_bus.clk,
543 .enable = s5pc100_d1_3_ctrl,
547 .parent = &clk_div_d1_bus.clk,
548 .enable = s5pc100_d1_3_ctrl,
552 .parent = &clk_div_d1_bus.clk,
553 .enable = s5pc100_d1_3_ctrl,
557 .parent = &clk_div_d1_bus.clk,
558 .enable = s5pc100_d1_3_ctrl,
562 .parent = &clk_div_d1_bus.clk,
563 .enable = s5pc100_d1_3_ctrl,
567 .devname = "s3c2440-i2c.0",
568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_4_ctrl,
573 .devname = "s3c2440-i2c.1",
574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_4_ctrl,
579 .devname = "s3c64xx-spi.0",
580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_4_ctrl,
585 .devname = "s3c64xx-spi.1",
586 .parent = &clk_div_d1_bus.clk,
587 .enable = s5pc100_d1_4_ctrl,
591 .devname = "s3c64xx-spi.2",
592 .parent = &clk_div_d1_bus.clk,
593 .enable = s5pc100_d1_4_ctrl,
597 .parent = &clk_div_d1_bus.clk,
598 .enable = s5pc100_d1_4_ctrl,
602 .parent = &clk_div_d1_bus.clk,
603 .enable = s5pc100_d1_4_ctrl,
604 .ctrlbit = (1 << 10),
607 .parent = &clk_div_d1_bus.clk,
608 .enable = s5pc100_d1_4_ctrl,
609 .ctrlbit = (1 << 11),
612 .parent = &clk_div_d1_bus.clk,
613 .enable = s5pc100_d1_4_ctrl,
614 .ctrlbit = (1 << 12),
617 .parent = &clk_div_d1_bus.clk,
618 .enable = s5pc100_d1_4_ctrl,
619 .ctrlbit = (1 << 13),
622 .devname = "samsung-i2s.0",
623 .parent = &clk_div_pclkd1.clk,
624 .enable = s5pc100_d1_5_ctrl,
628 .devname = "samsung-i2s.1",
629 .parent = &clk_div_pclkd1.clk,
630 .enable = s5pc100_d1_5_ctrl,
634 .devname = "samsung-i2s.2",
635 .parent = &clk_div_pclkd1.clk,
636 .enable = s5pc100_d1_5_ctrl,
640 .parent = &clk_div_pclkd1.clk,
641 .enable = s5pc100_d1_5_ctrl,
645 .devname = "samsung-pcm.0",
646 .parent = &clk_div_pclkd1.clk,
647 .enable = s5pc100_d1_5_ctrl,
651 .devname = "samsung-pcm.1",
652 .parent = &clk_div_pclkd1.clk,
653 .enable = s5pc100_d1_5_ctrl,
657 .parent = &clk_div_pclkd1.clk,
658 .enable = s5pc100_d1_5_ctrl,
662 .parent = &clk_div_pclkd1.clk,
663 .enable = s5pc100_d1_5_ctrl,
667 .parent = &clk_div_pclkd1.clk,
668 .enable = s5pc100_d1_5_ctrl,
672 .devname = "s3c64xx-spi.0",
673 .parent = &clk_mout_48m.clk,
674 .enable = s5pc100_sclk0_ctrl,
678 .devname = "s3c64xx-spi.1",
679 .parent = &clk_mout_48m.clk,
680 .enable = s5pc100_sclk0_ctrl,
684 .devname = "s3c64xx-spi.2",
685 .parent = &clk_mout_48m.clk,
686 .enable = s5pc100_sclk0_ctrl,
690 .devname = "s3c-sdhci.0",
691 .parent = &clk_mout_48m.clk,
692 .enable = s5pc100_sclk0_ctrl,
693 .ctrlbit = (1 << 15),
696 .devname = "s3c-sdhci.1",
697 .parent = &clk_mout_48m.clk,
698 .enable = s5pc100_sclk0_ctrl,
699 .ctrlbit = (1 << 16),
702 .devname = "s3c-sdhci.2",
703 .parent = &clk_mout_48m.clk,
704 .enable = s5pc100_sclk0_ctrl,
705 .ctrlbit = (1 << 17),
709 static struct clk clk_vclk54m = {
714 static struct clk clk_i2scdclk0 = {
715 .name = "i2s_cdclk0",
718 static struct clk clk_i2scdclk1 = {
719 .name = "i2s_cdclk1",
722 static struct clk clk_i2scdclk2 = {
723 .name = "i2s_cdclk2",
726 static struct clk clk_pcmcdclk0 = {
727 .name = "pcm_cdclk0",
730 static struct clk clk_pcmcdclk1 = {
731 .name = "pcm_cdclk1",
734 static struct clk *clk_src_group1_list[] = {
735 [0] = &clk_mout_epll.clk,
736 [1] = &clk_div_mpll2.clk,
738 [3] = &clk_mout_hpll.clk,
741 struct clksrc_sources clk_src_group1 = {
742 .sources = clk_src_group1_list,
743 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
746 static struct clk *clk_src_group2_list[] = {
747 [0] = &clk_mout_epll.clk,
748 [1] = &clk_div_mpll.clk,
751 struct clksrc_sources clk_src_group2 = {
752 .sources = clk_src_group2_list,
753 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
756 static struct clk *clk_src_group3_list[] = {
757 [0] = &clk_mout_epll.clk,
758 [1] = &clk_div_mpll.clk,
760 [3] = &clk_i2scdclk0,
761 [4] = &clk_pcmcdclk0,
762 [5] = &clk_mout_hpll.clk,
765 struct clksrc_sources clk_src_group3 = {
766 .sources = clk_src_group3_list,
767 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
770 static struct clksrc_clk clk_sclk_audio0 = {
772 .name = "sclk_audio",
773 .devname = "samsung-pcm.0",
775 .enable = s5pc100_sclk1_ctrl,
777 .sources = &clk_src_group3,
778 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
779 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
782 static struct clk *clk_src_group4_list[] = {
783 [0] = &clk_mout_epll.clk,
784 [1] = &clk_div_mpll.clk,
786 [3] = &clk_i2scdclk1,
787 [4] = &clk_pcmcdclk1,
788 [5] = &clk_mout_hpll.clk,
791 struct clksrc_sources clk_src_group4 = {
792 .sources = clk_src_group4_list,
793 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
796 static struct clksrc_clk clk_sclk_audio1 = {
798 .name = "sclk_audio",
799 .devname = "samsung-pcm.1",
801 .enable = s5pc100_sclk1_ctrl,
803 .sources = &clk_src_group4,
804 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
805 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
808 static struct clk *clk_src_group5_list[] = {
809 [0] = &clk_mout_epll.clk,
810 [1] = &clk_div_mpll.clk,
812 [3] = &clk_i2scdclk2,
813 [4] = &clk_mout_hpll.clk,
816 struct clksrc_sources clk_src_group5 = {
817 .sources = clk_src_group5_list,
818 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
821 static struct clksrc_clk clk_sclk_audio2 = {
823 .name = "sclk_audio",
824 .devname = "samsung-pcm.2",
825 .ctrlbit = (1 << 10),
826 .enable = s5pc100_sclk1_ctrl,
828 .sources = &clk_src_group5,
829 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
830 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
833 static struct clk *clk_src_group6_list[] = {
836 [2] = &clk_div_hdmi.clk,
839 struct clksrc_sources clk_src_group6 = {
840 .sources = clk_src_group6_list,
841 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
844 static struct clk *clk_src_group7_list[] = {
845 [0] = &clk_mout_epll.clk,
846 [1] = &clk_div_mpll.clk,
847 [2] = &clk_mout_hpll.clk,
851 struct clksrc_sources clk_src_group7 = {
852 .sources = clk_src_group7_list,
853 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
856 static struct clk *clk_src_mmc0_list[] = {
857 [0] = &clk_mout_epll.clk,
858 [1] = &clk_div_mpll.clk,
862 struct clksrc_sources clk_src_mmc0 = {
863 .sources = clk_src_mmc0_list,
864 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
867 static struct clk *clk_src_mmc12_list[] = {
868 [0] = &clk_mout_epll.clk,
869 [1] = &clk_div_mpll.clk,
871 [3] = &clk_mout_hpll.clk,
874 struct clksrc_sources clk_src_mmc12 = {
875 .sources = clk_src_mmc12_list,
876 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
879 static struct clk *clk_src_irda_usb_list[] = {
880 [0] = &clk_mout_epll.clk,
881 [1] = &clk_div_mpll.clk,
883 [3] = &clk_mout_hpll.clk,
886 struct clksrc_sources clk_src_irda_usb = {
887 .sources = clk_src_irda_usb_list,
888 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
891 static struct clk *clk_src_pwi_list[] = {
893 [1] = &clk_mout_epll.clk,
894 [2] = &clk_div_mpll.clk,
897 struct clksrc_sources clk_src_pwi = {
898 .sources = clk_src_pwi_list,
899 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
902 static struct clk *clk_sclk_spdif_list[] = {
903 [0] = &clk_sclk_audio0.clk,
904 [1] = &clk_sclk_audio1.clk,
905 [2] = &clk_sclk_audio2.clk,
908 struct clksrc_sources clk_src_sclk_spdif = {
909 .sources = clk_sclk_spdif_list,
910 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
913 static struct clksrc_clk clk_sclk_spdif = {
915 .name = "sclk_spdif",
916 .ctrlbit = (1 << 11),
917 .enable = s5pc100_sclk1_ctrl,
918 .ops = &s5p_sclk_spdif_ops,
920 .sources = &clk_src_sclk_spdif,
921 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
924 static struct clksrc_clk clksrcs[] = {
928 .devname = "s3c64xx-spi.0",
930 .enable = s5pc100_sclk0_ctrl,
933 .sources = &clk_src_group1,
934 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
935 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
939 .devname = "s3c64xx-spi.1",
941 .enable = s5pc100_sclk0_ctrl,
944 .sources = &clk_src_group1,
945 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
946 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
950 .devname = "s3c64xx-spi.2",
952 .enable = s5pc100_sclk0_ctrl,
955 .sources = &clk_src_group1,
956 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
957 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
962 .enable = s5pc100_sclk0_ctrl,
965 .sources = &clk_src_group2,
966 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
967 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
970 .name = "sclk_mixer",
972 .enable = s5pc100_sclk0_ctrl,
975 .sources = &clk_src_group6,
976 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
981 .enable = s5pc100_sclk1_ctrl,
984 .sources = &clk_src_group7,
985 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
986 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
990 .devname = "s5p-fimc.0",
992 .enable = s5pc100_sclk1_ctrl,
995 .sources = &clk_src_group7,
996 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
997 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
1000 .name = "sclk_fimc",
1001 .devname = "s5p-fimc.1",
1002 .ctrlbit = (1 << 2),
1003 .enable = s5pc100_sclk1_ctrl,
1006 .sources = &clk_src_group7,
1007 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1008 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1011 .name = "sclk_fimc",
1012 .devname = "s5p-fimc.2",
1013 .ctrlbit = (1 << 3),
1014 .enable = s5pc100_sclk1_ctrl,
1017 .sources = &clk_src_group7,
1018 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1019 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1023 .devname = "s3c-sdhci.0",
1024 .ctrlbit = (1 << 12),
1025 .enable = s5pc100_sclk1_ctrl,
1028 .sources = &clk_src_mmc0,
1029 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1030 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1034 .devname = "s3c-sdhci.1",
1035 .ctrlbit = (1 << 13),
1036 .enable = s5pc100_sclk1_ctrl,
1039 .sources = &clk_src_mmc12,
1040 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1041 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1045 .devname = "s3c-sdhci.2",
1046 .ctrlbit = (1 << 14),
1047 .enable = s5pc100_sclk1_ctrl,
1050 .sources = &clk_src_mmc12,
1051 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1052 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1055 .name = "sclk_irda",
1056 .ctrlbit = (1 << 10),
1057 .enable = s5pc100_sclk0_ctrl,
1060 .sources = &clk_src_irda_usb,
1061 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1062 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1065 .name = "sclk_irda",
1066 .ctrlbit = (1 << 10),
1067 .enable = s5pc100_sclk0_ctrl,
1070 .sources = &clk_src_mmc12,
1071 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1072 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1076 .ctrlbit = (1 << 1),
1077 .enable = s5pc100_sclk0_ctrl,
1080 .sources = &clk_src_pwi,
1081 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1082 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1085 .name = "sclk_uhost",
1086 .ctrlbit = (1 << 11),
1087 .enable = s5pc100_sclk0_ctrl,
1090 .sources = &clk_src_irda_usb,
1091 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1092 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1096 /* Clock initialisation code */
1097 static struct clksrc_clk *sysclks[] = {
1125 void __init_or_cpufreq s5pc100_setup_clocks(void)
1129 unsigned long hclkd0;
1130 unsigned long hclkd1;
1131 unsigned long pclkd0;
1132 unsigned long pclkd1;
1139 /* Set S5PC100 functions for clk_fout_epll */
1140 clk_fout_epll.enable = s5p_epll_enable;
1141 clk_fout_epll.ops = &s5pc100_epll_ops;
1143 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1145 xtal = clk_get_rate(&clk_xtal);
1147 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1149 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1150 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1151 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1152 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1154 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1155 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1157 clk_fout_apll.rate = apll;
1158 clk_fout_mpll.rate = mpll;
1159 clk_fout_epll.rate = epll;
1160 clk_mout_hpll.clk.rate = hpll;
1162 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1163 s3c_set_clksrc(&clksrcs[ptr], true);
1165 arm = clk_get_rate(&clk_div_arm.clk);
1166 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1167 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1168 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1169 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1171 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1172 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1175 clk_h.rate = hclkd1;
1176 clk_p.rate = pclkd1;
1180 * The following clocks will be enabled during clock initialization.
1182 static struct clk init_clocks[] = {
1185 .parent = &clk_div_d0_bus.clk,
1186 .enable = s5pc100_d0_0_ctrl,
1187 .ctrlbit = (1 << 1),
1190 .parent = &clk_div_d0_bus.clk,
1191 .enable = s5pc100_d0_0_ctrl,
1192 .ctrlbit = (1 << 0),
1195 .parent = &clk_div_d0_bus.clk,
1196 .enable = s5pc100_d0_1_ctrl,
1197 .ctrlbit = (1 << 5),
1200 .parent = &clk_div_d0_bus.clk,
1201 .enable = s5pc100_d0_1_ctrl,
1202 .ctrlbit = (1 << 4),
1205 .parent = &clk_div_d0_bus.clk,
1206 .enable = s5pc100_d0_1_ctrl,
1207 .ctrlbit = (1 << 1),
1210 .parent = &clk_div_d0_bus.clk,
1211 .enable = s5pc100_d0_1_ctrl,
1212 .ctrlbit = (1 << 0),
1215 .parent = &clk_div_d0_bus.clk,
1216 .enable = s5pc100_d0_1_ctrl,
1217 .ctrlbit = (1 << 0),
1220 .parent = &clk_div_d1_bus.clk,
1221 .enable = s5pc100_d1_3_ctrl,
1222 .ctrlbit = (1 << 1),
1225 .devname = "s3c6400-uart.0",
1226 .parent = &clk_div_d1_bus.clk,
1227 .enable = s5pc100_d1_4_ctrl,
1228 .ctrlbit = (1 << 0),
1231 .devname = "s3c6400-uart.1",
1232 .parent = &clk_div_d1_bus.clk,
1233 .enable = s5pc100_d1_4_ctrl,
1234 .ctrlbit = (1 << 1),
1237 .devname = "s3c6400-uart.2",
1238 .parent = &clk_div_d1_bus.clk,
1239 .enable = s5pc100_d1_4_ctrl,
1240 .ctrlbit = (1 << 2),
1243 .devname = "s3c6400-uart.3",
1244 .parent = &clk_div_d1_bus.clk,
1245 .enable = s5pc100_d1_4_ctrl,
1246 .ctrlbit = (1 << 3),
1249 .parent = &clk_div_d1_bus.clk,
1250 .enable = s5pc100_d1_3_ctrl,
1251 .ctrlbit = (1 << 6),
1255 static struct clk *clks[] __initdata = {
1264 void __init s5pc100_register_clocks(void)
1268 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1270 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1271 s3c_register_clksrc(sysclks[ptr], 1);
1273 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1274 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1276 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1277 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));