1 /* linux/arch/arm/mach-s5pc100/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PC100 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
23 #include <plat/cpu-freq.h>
24 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
28 #include <plat/s5p-clock.h>
29 #include <plat/clock-clksrc.h>
30 #include <plat/s5pc100.h>
32 static struct clk s5p_clk_otgphy = {
37 static struct clk *clk_src_mout_href_list[] = {
42 static struct clksrc_sources clk_src_mout_href = {
43 .sources = clk_src_mout_href_list,
44 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
47 static struct clksrc_clk clk_mout_href = {
52 .sources = &clk_src_mout_href,
53 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
56 static struct clk *clk_src_mout_48m_list[] = {
58 [1] = &s5p_clk_otgphy,
61 static struct clksrc_sources clk_src_mout_48m = {
62 .sources = clk_src_mout_48m_list,
63 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
66 static struct clksrc_clk clk_mout_48m = {
71 .sources = &clk_src_mout_48m,
72 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
75 static struct clksrc_clk clk_mout_mpll = {
80 .sources = &clk_src_mpll,
81 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
85 static struct clksrc_clk clk_mout_apll = {
90 .sources = &clk_src_apll,
91 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
94 static struct clksrc_clk clk_mout_epll = {
99 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
103 static struct clk *clk_src_mout_hpll_list[] = {
107 static struct clksrc_sources clk_src_mout_hpll = {
108 .sources = clk_src_mout_hpll_list,
109 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
112 static struct clksrc_clk clk_mout_hpll = {
117 .sources = &clk_src_mout_hpll,
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
121 static struct clksrc_clk clk_div_apll = {
125 .parent = &clk_mout_apll.clk,
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
130 static struct clksrc_clk clk_div_arm = {
134 .parent = &clk_div_apll.clk,
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
139 static struct clksrc_clk clk_div_d0_bus = {
141 .name = "div_d0_bus",
143 .parent = &clk_div_arm.clk,
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
148 static struct clksrc_clk clk_div_pclkd0 = {
150 .name = "div_pclkd0",
152 .parent = &clk_div_d0_bus.clk,
154 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
157 static struct clksrc_clk clk_div_secss = {
161 .parent = &clk_div_d0_bus.clk,
163 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
166 static struct clksrc_clk clk_div_apll2 = {
170 .parent = &clk_mout_apll.clk,
172 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
175 static struct clk *clk_src_mout_am_list[] = {
176 [0] = &clk_mout_mpll.clk,
177 [1] = &clk_div_apll2.clk,
180 struct clksrc_sources clk_src_mout_am = {
181 .sources = clk_src_mout_am_list,
182 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
185 static struct clksrc_clk clk_mout_am = {
190 .sources = &clk_src_mout_am,
191 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
194 static struct clksrc_clk clk_div_d1_bus = {
196 .name = "div_d1_bus",
198 .parent = &clk_mout_am.clk,
200 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
203 static struct clksrc_clk clk_div_mpll2 = {
207 .parent = &clk_mout_am.clk,
209 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
212 static struct clksrc_clk clk_div_mpll = {
216 .parent = &clk_mout_am.clk,
218 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
221 static struct clk *clk_src_mout_onenand_list[] = {
222 [0] = &clk_div_d0_bus.clk,
223 [1] = &clk_div_d1_bus.clk,
226 struct clksrc_sources clk_src_mout_onenand = {
227 .sources = clk_src_mout_onenand_list,
228 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
231 static struct clksrc_clk clk_mout_onenand = {
233 .name = "mout_onenand",
236 .sources = &clk_src_mout_onenand,
237 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
240 static struct clksrc_clk clk_div_onenand = {
242 .name = "div_onenand",
244 .parent = &clk_mout_onenand.clk,
246 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
249 static struct clksrc_clk clk_div_pclkd1 = {
251 .name = "div_pclkd1",
253 .parent = &clk_div_d1_bus.clk,
255 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
258 static struct clksrc_clk clk_div_cam = {
262 .parent = &clk_div_mpll2.clk,
264 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
267 static struct clksrc_clk clk_div_hdmi = {
271 .parent = &clk_mout_hpll.clk,
273 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
276 static int s5pc100_epll_enable(struct clk *clk, int enable)
278 unsigned int ctrlbit = clk->ctrlbit;
279 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
282 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
284 __raw_writel(epll_con, S5P_EPLL_CON);
289 static unsigned long s5pc100_epll_get_rate(struct clk *clk)
294 static u32 epll_div[][4] = {
295 { 32750000, 131, 3, 4 },
296 { 32768000, 131, 3, 4 },
297 { 36000000, 72, 3, 3 },
298 { 45000000, 90, 3, 3 },
299 { 45158000, 90, 3, 3 },
300 { 45158400, 90, 3, 3 },
301 { 48000000, 96, 3, 3 },
302 { 49125000, 131, 4, 3 },
303 { 49152000, 131, 4, 3 },
304 { 60000000, 120, 3, 3 },
305 { 67737600, 226, 5, 3 },
306 { 67738000, 226, 5, 3 },
307 { 73800000, 246, 5, 3 },
308 { 73728000, 246, 5, 3 },
309 { 72000000, 144, 3, 3 },
310 { 84000000, 168, 3, 3 },
311 { 96000000, 96, 3, 2 },
312 { 144000000, 144, 3, 2 },
313 { 192000000, 96, 3, 1 }
316 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
318 unsigned int epll_con;
321 if (clk->rate == rate) /* Return if nothing changed */
324 epll_con = __raw_readl(S5P_EPLL_CON);
326 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
328 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
329 if (epll_div[i][0] == rate) {
330 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
331 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
332 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
337 if (i == ARRAY_SIZE(epll_div)) {
338 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
342 __raw_writel(epll_con, S5P_EPLL_CON);
349 static struct clk_ops s5pc100_epll_ops = {
350 .get_rate = s5pc100_epll_get_rate,
351 .set_rate = s5pc100_epll_set_rate,
354 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
356 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
359 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
361 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
364 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
366 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
369 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
371 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
374 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
376 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
379 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
381 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
384 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
386 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
389 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
391 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
394 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
396 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
399 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
401 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
404 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
406 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
410 * The following clocks will be disabled during clock initialization. It is
411 * recommended to keep the following clocks disabled until the driver requests
412 * for enabling the clock.
414 static struct clk init_clocks_disable[] = {
418 .parent = &clk_div_d0_bus.clk,
419 .enable = s5pc100_d0_0_ctrl,
424 .parent = &clk_div_d0_bus.clk,
425 .enable = s5pc100_d0_0_ctrl,
430 .parent = &clk_div_d0_bus.clk,
431 .enable = s5pc100_d0_0_ctrl,
436 .parent = &clk_div_d0_bus.clk,
437 .enable = s5pc100_d0_0_ctrl,
442 .parent = &clk_div_d0_bus.clk,
443 .enable = s5pc100_d0_0_ctrl,
448 .parent = &clk_div_d0_bus.clk,
449 .enable = s5pc100_d0_1_ctrl,
454 .parent = &clk_div_d0_bus.clk,
455 .enable = s5pc100_d0_1_ctrl,
460 .parent = &clk_div_d0_bus.clk,
461 .enable = s5pc100_d0_2_ctrl,
466 .parent = &clk_div_d0_bus.clk,
467 .enable = s5pc100_d0_2_ctrl,
472 .parent = &clk_div_d1_bus.clk,
473 .enable = s5pc100_d1_0_ctrl,
478 .parent = &clk_div_d1_bus.clk,
479 .enable = s5pc100_d1_0_ctrl,
484 .parent = &clk_div_d1_bus.clk,
485 .enable = s5pc100_d1_0_ctrl,
490 .parent = &clk_div_d1_bus.clk,
491 .enable = s5pc100_d1_0_ctrl,
496 .parent = &clk_div_d1_bus.clk,
497 .enable = s5pc100_d1_0_ctrl,
502 .parent = &clk_div_d1_bus.clk,
503 .enable = s5pc100_d1_0_ctrl,
508 .parent = &clk_div_d1_bus.clk,
509 .enable = s5pc100_d1_0_ctrl,
514 .parent = &clk_div_d1_bus.clk,
515 .enable = s5pc100_d1_0_ctrl,
520 .parent = &clk_div_d1_bus.clk,
521 .enable = s5pc100_d1_1_ctrl,
526 .parent = &clk_div_d1_bus.clk,
527 .enable = s5pc100_d1_1_ctrl,
532 .parent = &clk_div_d1_bus.clk,
533 .enable = s5pc100_d1_1_ctrl,
538 .parent = &clk_div_d1_bus.clk,
539 .enable = s5pc100_d1_1_ctrl,
544 .parent = &clk_div_d1_bus.clk,
545 .enable = s5pc100_d1_1_ctrl,
550 .parent = &clk_div_d1_bus.clk,
551 .enable = s5pc100_d1_1_ctrl,
556 .parent = &clk_div_d1_bus.clk,
557 .enable = s5pc100_d1_1_ctrl,
562 .parent = &clk_div_d1_bus.clk,
563 .enable = s5pc100_d1_1_ctrl,
568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_0_ctrl,
574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_2_ctrl,
580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_2_ctrl,
586 .parent = &clk_div_d1_bus.clk,
587 .enable = s5pc100_d1_2_ctrl,
592 .parent = &clk_div_d1_bus.clk,
593 .enable = s5pc100_d1_2_ctrl,
598 .parent = &clk_div_d1_bus.clk,
599 .enable = s5pc100_d1_2_ctrl,
604 .parent = &clk_div_d1_bus.clk,
605 .enable = s5pc100_d1_3_ctrl,
610 .parent = &clk_div_d1_bus.clk,
611 .enable = s5pc100_d1_3_ctrl,
616 .parent = &clk_div_d1_bus.clk,
617 .enable = s5pc100_d1_3_ctrl,
622 .parent = &clk_div_d1_bus.clk,
623 .enable = s5pc100_d1_3_ctrl,
628 .parent = &clk_div_d1_bus.clk,
629 .enable = s5pc100_d1_3_ctrl,
634 .parent = &clk_div_d1_bus.clk,
635 .enable = s5pc100_d1_4_ctrl,
640 .parent = &clk_div_d1_bus.clk,
641 .enable = s5pc100_d1_4_ctrl,
646 .parent = &clk_div_d1_bus.clk,
647 .enable = s5pc100_d1_4_ctrl,
652 .parent = &clk_div_d1_bus.clk,
653 .enable = s5pc100_d1_4_ctrl,
658 .parent = &clk_div_d1_bus.clk,
659 .enable = s5pc100_d1_4_ctrl,
664 .parent = &clk_div_d1_bus.clk,
665 .enable = s5pc100_d1_4_ctrl,
670 .parent = &clk_div_d1_bus.clk,
671 .enable = s5pc100_d1_4_ctrl,
672 .ctrlbit = (1 << 10),
676 .parent = &clk_div_d1_bus.clk,
677 .enable = s5pc100_d1_4_ctrl,
678 .ctrlbit = (1 << 11),
682 .parent = &clk_div_d1_bus.clk,
683 .enable = s5pc100_d1_4_ctrl,
684 .ctrlbit = (1 << 12),
688 .parent = &clk_div_d1_bus.clk,
689 .enable = s5pc100_d1_4_ctrl,
690 .ctrlbit = (1 << 13),
694 .parent = &clk_div_d1_bus.clk,
695 .enable = s5pc100_d1_5_ctrl,
700 .parent = &clk_div_d1_bus.clk,
701 .enable = s5pc100_d1_5_ctrl,
706 .parent = &clk_div_d1_bus.clk,
707 .enable = s5pc100_d1_5_ctrl,
712 .parent = &clk_div_d1_bus.clk,
713 .enable = s5pc100_d1_5_ctrl,
718 .parent = &clk_div_d1_bus.clk,
719 .enable = s5pc100_d1_5_ctrl,
724 .parent = &clk_div_d1_bus.clk,
725 .enable = s5pc100_d1_5_ctrl,
730 .parent = &clk_div_d1_bus.clk,
731 .enable = s5pc100_d1_5_ctrl,
736 .parent = &clk_div_d1_bus.clk,
737 .enable = s5pc100_d1_5_ctrl,
742 .parent = &clk_div_d1_bus.clk,
743 .enable = s5pc100_d1_5_ctrl,
748 .parent = &clk_mout_48m.clk,
749 .enable = s5pc100_sclk0_ctrl,
754 .parent = &clk_mout_48m.clk,
755 .enable = s5pc100_sclk0_ctrl,
760 .parent = &clk_mout_48m.clk,
761 .enable = s5pc100_sclk0_ctrl,
766 .parent = &clk_mout_48m.clk,
767 .enable = s5pc100_sclk0_ctrl,
768 .ctrlbit = (1 << 15),
772 .parent = &clk_mout_48m.clk,
773 .enable = s5pc100_sclk0_ctrl,
774 .ctrlbit = (1 << 16),
778 .parent = &clk_mout_48m.clk,
779 .enable = s5pc100_sclk0_ctrl,
780 .ctrlbit = (1 << 17),
784 static struct clk clk_vclk54m = {
790 static struct clk clk_i2scdclk0 = {
791 .name = "i2s_cdclk0",
795 static struct clk clk_i2scdclk1 = {
796 .name = "i2s_cdclk1",
800 static struct clk clk_i2scdclk2 = {
801 .name = "i2s_cdclk2",
805 static struct clk clk_pcmcdclk0 = {
806 .name = "pcm_cdclk0",
810 static struct clk clk_pcmcdclk1 = {
811 .name = "pcm_cdclk1",
815 static struct clk *clk_src_group1_list[] = {
816 [0] = &clk_mout_epll.clk,
817 [1] = &clk_div_mpll2.clk,
819 [3] = &clk_mout_hpll.clk,
822 struct clksrc_sources clk_src_group1 = {
823 .sources = clk_src_group1_list,
824 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
827 static struct clk *clk_src_group2_list[] = {
828 [0] = &clk_mout_epll.clk,
829 [1] = &clk_div_mpll.clk,
832 struct clksrc_sources clk_src_group2 = {
833 .sources = clk_src_group2_list,
834 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
837 static struct clk *clk_src_group3_list[] = {
838 [0] = &clk_mout_epll.clk,
839 [1] = &clk_div_mpll.clk,
841 [3] = &clk_i2scdclk0,
842 [4] = &clk_pcmcdclk0,
843 [5] = &clk_mout_hpll.clk,
846 struct clksrc_sources clk_src_group3 = {
847 .sources = clk_src_group3_list,
848 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
851 static struct clksrc_clk clk_sclk_audio0 = {
853 .name = "sclk_audio",
856 .enable = s5pc100_sclk1_ctrl,
858 .sources = &clk_src_group3,
859 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
860 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
863 static struct clk *clk_src_group4_list[] = {
864 [0] = &clk_mout_epll.clk,
865 [1] = &clk_div_mpll.clk,
867 [3] = &clk_i2scdclk1,
868 [4] = &clk_pcmcdclk1,
869 [5] = &clk_mout_hpll.clk,
872 struct clksrc_sources clk_src_group4 = {
873 .sources = clk_src_group4_list,
874 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
877 static struct clksrc_clk clk_sclk_audio1 = {
879 .name = "sclk_audio",
882 .enable = s5pc100_sclk1_ctrl,
884 .sources = &clk_src_group4,
885 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
886 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
889 static struct clk *clk_src_group5_list[] = {
890 [0] = &clk_mout_epll.clk,
891 [1] = &clk_div_mpll.clk,
893 [3] = &clk_i2scdclk2,
894 [4] = &clk_mout_hpll.clk,
897 struct clksrc_sources clk_src_group5 = {
898 .sources = clk_src_group5_list,
899 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
902 static struct clksrc_clk clk_sclk_audio2 = {
904 .name = "sclk_audio",
906 .ctrlbit = (1 << 10),
907 .enable = s5pc100_sclk1_ctrl,
909 .sources = &clk_src_group5,
910 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
911 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
914 static struct clk *clk_src_group6_list[] = {
917 [2] = &clk_div_hdmi.clk,
920 struct clksrc_sources clk_src_group6 = {
921 .sources = clk_src_group6_list,
922 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
925 static struct clk *clk_src_group7_list[] = {
926 [0] = &clk_mout_epll.clk,
927 [1] = &clk_div_mpll.clk,
928 [2] = &clk_mout_hpll.clk,
932 struct clksrc_sources clk_src_group7 = {
933 .sources = clk_src_group7_list,
934 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
937 static struct clk *clk_src_mmc0_list[] = {
938 [0] = &clk_mout_epll.clk,
939 [1] = &clk_div_mpll.clk,
943 struct clksrc_sources clk_src_mmc0 = {
944 .sources = clk_src_mmc0_list,
945 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
948 static struct clk *clk_src_mmc12_list[] = {
949 [0] = &clk_mout_epll.clk,
950 [1] = &clk_div_mpll.clk,
952 [3] = &clk_mout_hpll.clk,
955 struct clksrc_sources clk_src_mmc12 = {
956 .sources = clk_src_mmc12_list,
957 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
960 static struct clk *clk_src_irda_usb_list[] = {
961 [0] = &clk_mout_epll.clk,
962 [1] = &clk_div_mpll.clk,
964 [3] = &clk_mout_hpll.clk,
967 struct clksrc_sources clk_src_irda_usb = {
968 .sources = clk_src_irda_usb_list,
969 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
972 static struct clk *clk_src_pwi_list[] = {
974 [1] = &clk_mout_epll.clk,
975 [2] = &clk_div_mpll.clk,
978 struct clksrc_sources clk_src_pwi = {
979 .sources = clk_src_pwi_list,
980 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
983 static struct clksrc_clk clksrcs[] = {
989 .enable = s5pc100_sclk0_ctrl,
992 .sources = &clk_src_group1,
993 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
994 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1000 .enable = s5pc100_sclk0_ctrl,
1003 .sources = &clk_src_group1,
1004 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1005 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1010 .ctrlbit = (1 << 6),
1011 .enable = s5pc100_sclk0_ctrl,
1014 .sources = &clk_src_group1,
1015 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1016 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1021 .ctrlbit = (1 << 3),
1022 .enable = s5pc100_sclk0_ctrl,
1025 .sources = &clk_src_group2,
1026 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1027 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1030 .name = "sclk_mixer",
1032 .ctrlbit = (1 << 6),
1033 .enable = s5pc100_sclk0_ctrl,
1036 .sources = &clk_src_group6,
1037 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
1042 .ctrlbit = (1 << 0),
1043 .enable = s5pc100_sclk1_ctrl,
1046 .sources = &clk_src_group7,
1047 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
1048 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
1051 .name = "sclk_fimc",
1053 .ctrlbit = (1 << 1),
1054 .enable = s5pc100_sclk1_ctrl,
1057 .sources = &clk_src_group7,
1058 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
1059 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
1062 .name = "sclk_fimc",
1064 .ctrlbit = (1 << 2),
1065 .enable = s5pc100_sclk1_ctrl,
1068 .sources = &clk_src_group7,
1069 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1070 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1073 .name = "sclk_fimc",
1075 .ctrlbit = (1 << 3),
1076 .enable = s5pc100_sclk1_ctrl,
1079 .sources = &clk_src_group7,
1080 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1081 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1086 .ctrlbit = (1 << 12),
1087 .enable = s5pc100_sclk1_ctrl,
1090 .sources = &clk_src_mmc0,
1091 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1092 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1097 .ctrlbit = (1 << 13),
1098 .enable = s5pc100_sclk1_ctrl,
1101 .sources = &clk_src_mmc12,
1102 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1103 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1108 .ctrlbit = (1 << 14),
1109 .enable = s5pc100_sclk1_ctrl,
1112 .sources = &clk_src_mmc12,
1113 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1114 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1117 .name = "sclk_irda",
1119 .ctrlbit = (1 << 10),
1120 .enable = s5pc100_sclk0_ctrl,
1123 .sources = &clk_src_irda_usb,
1124 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1125 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1128 .name = "sclk_irda",
1130 .ctrlbit = (1 << 10),
1131 .enable = s5pc100_sclk0_ctrl,
1134 .sources = &clk_src_mmc12,
1135 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1136 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1141 .ctrlbit = (1 << 1),
1142 .enable = s5pc100_sclk0_ctrl,
1145 .sources = &clk_src_pwi,
1146 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1147 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1150 .name = "sclk_uhost",
1152 .ctrlbit = (1 << 11),
1153 .enable = s5pc100_sclk0_ctrl,
1156 .sources = &clk_src_irda_usb,
1157 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1158 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1162 /* Clock initialisation code */
1163 static struct clksrc_clk *sysclks[] = {
1190 void __init_or_cpufreq s5pc100_setup_clocks(void)
1194 unsigned long hclkd0;
1195 unsigned long hclkd1;
1196 unsigned long pclkd0;
1197 unsigned long pclkd1;
1204 /* Set S5PC100 functions for clk_fout_epll */
1205 clk_fout_epll.enable = s5pc100_epll_enable;
1206 clk_fout_epll.ops = &s5pc100_epll_ops;
1208 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1210 xtal = clk_get_rate(&clk_xtal);
1212 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1214 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1215 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1216 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1217 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1219 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1220 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1222 clk_fout_apll.rate = apll;
1223 clk_fout_mpll.rate = mpll;
1224 clk_fout_epll.rate = epll;
1225 clk_mout_hpll.clk.rate = hpll;
1227 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1228 s3c_set_clksrc(&clksrcs[ptr], true);
1230 arm = clk_get_rate(&clk_div_arm.clk);
1231 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1232 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1233 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1234 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1236 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1237 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1240 clk_h.rate = hclkd1;
1241 clk_p.rate = pclkd1;
1245 * The following clocks will be enabled during clock initialization.
1247 static struct clk init_clocks[] = {
1251 .parent = &clk_div_d0_bus.clk,
1252 .enable = s5pc100_d0_0_ctrl,
1253 .ctrlbit = (1 << 1),
1257 .parent = &clk_div_d0_bus.clk,
1258 .enable = s5pc100_d0_0_ctrl,
1259 .ctrlbit = (1 << 0),
1263 .parent = &clk_div_d0_bus.clk,
1264 .enable = s5pc100_d0_1_ctrl,
1265 .ctrlbit = (1 << 5),
1269 .parent = &clk_div_d0_bus.clk,
1270 .enable = s5pc100_d0_1_ctrl,
1271 .ctrlbit = (1 << 4),
1275 .parent = &clk_div_d0_bus.clk,
1276 .enable = s5pc100_d0_1_ctrl,
1277 .ctrlbit = (1 << 1),
1281 .parent = &clk_div_d0_bus.clk,
1282 .enable = s5pc100_d0_1_ctrl,
1283 .ctrlbit = (1 << 0),
1287 .parent = &clk_div_d0_bus.clk,
1288 .enable = s5pc100_d0_1_ctrl,
1289 .ctrlbit = (1 << 0),
1293 .parent = &clk_div_d1_bus.clk,
1294 .enable = s5pc100_d1_3_ctrl,
1295 .ctrlbit = (1 << 1),
1299 .parent = &clk_div_d1_bus.clk,
1300 .enable = s5pc100_d1_4_ctrl,
1301 .ctrlbit = (1 << 0),
1305 .parent = &clk_div_d1_bus.clk,
1306 .enable = s5pc100_d1_4_ctrl,
1307 .ctrlbit = (1 << 1),
1311 .parent = &clk_div_d1_bus.clk,
1312 .enable = s5pc100_d1_4_ctrl,
1313 .ctrlbit = (1 << 2),
1317 .parent = &clk_div_d1_bus.clk,
1318 .enable = s5pc100_d1_4_ctrl,
1319 .ctrlbit = (1 << 3),
1323 .parent = &clk_div_d1_bus.clk,
1324 .enable = s5pc100_d1_3_ctrl,
1325 .ctrlbit = (1 << 6),
1329 static struct clk *clks[] __initdata = {
1338 void __init s5pc100_register_clocks(void)
1344 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1346 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1347 s3c_register_clksrc(sysclks[ptr], 1);
1349 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1350 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1352 clkp = init_clocks_disable;
1353 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1355 ret = s3c24xx_register_clock(clkp);
1357 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1360 (clkp->enable)(clkp, 0);