1 /* linux/arch/arm/mach-s5pc100/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PC100 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
23 #include <plat/cpu-freq.h>
24 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
28 #include <plat/s5p-clock.h>
29 #include <plat/clock-clksrc.h>
33 static struct clk s5p_clk_otgphy = {
37 static struct clk dummy_apb_pclk = {
42 static struct clk *clk_src_mout_href_list[] = {
47 static struct clksrc_sources clk_src_mout_href = {
48 .sources = clk_src_mout_href_list,
49 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
52 static struct clksrc_clk clk_mout_href = {
56 .sources = &clk_src_mout_href,
57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
60 static struct clk *clk_src_mout_48m_list[] = {
62 [1] = &s5p_clk_otgphy,
65 static struct clksrc_sources clk_src_mout_48m = {
66 .sources = clk_src_mout_48m_list,
67 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
70 static struct clksrc_clk clk_mout_48m = {
74 .sources = &clk_src_mout_48m,
75 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
78 static struct clksrc_clk clk_mout_mpll = {
82 .sources = &clk_src_mpll,
83 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
87 static struct clksrc_clk clk_mout_apll = {
91 .sources = &clk_src_apll,
92 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
95 static struct clksrc_clk clk_mout_epll = {
99 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
103 static struct clk *clk_src_mout_hpll_list[] = {
107 static struct clksrc_sources clk_src_mout_hpll = {
108 .sources = clk_src_mout_hpll_list,
109 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
112 static struct clksrc_clk clk_mout_hpll = {
116 .sources = &clk_src_mout_hpll,
117 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
120 static struct clksrc_clk clk_div_apll = {
123 .parent = &clk_mout_apll.clk,
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
128 static struct clksrc_clk clk_div_arm = {
131 .parent = &clk_div_apll.clk,
133 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
136 static struct clksrc_clk clk_div_d0_bus = {
138 .name = "div_d0_bus",
139 .parent = &clk_div_arm.clk,
141 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
144 static struct clksrc_clk clk_div_pclkd0 = {
146 .name = "div_pclkd0",
147 .parent = &clk_div_d0_bus.clk,
149 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
152 static struct clksrc_clk clk_div_secss = {
155 .parent = &clk_div_d0_bus.clk,
157 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
160 static struct clksrc_clk clk_div_apll2 = {
163 .parent = &clk_mout_apll.clk,
165 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
168 static struct clk *clk_src_mout_am_list[] = {
169 [0] = &clk_mout_mpll.clk,
170 [1] = &clk_div_apll2.clk,
173 static struct clksrc_sources clk_src_mout_am = {
174 .sources = clk_src_mout_am_list,
175 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
178 static struct clksrc_clk clk_mout_am = {
182 .sources = &clk_src_mout_am,
183 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
186 static struct clksrc_clk clk_div_d1_bus = {
188 .name = "div_d1_bus",
189 .parent = &clk_mout_am.clk,
191 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
194 static struct clksrc_clk clk_div_mpll2 = {
197 .parent = &clk_mout_am.clk,
199 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
202 static struct clksrc_clk clk_div_mpll = {
205 .parent = &clk_mout_am.clk,
207 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
210 static struct clk *clk_src_mout_onenand_list[] = {
211 [0] = &clk_div_d0_bus.clk,
212 [1] = &clk_div_d1_bus.clk,
215 static struct clksrc_sources clk_src_mout_onenand = {
216 .sources = clk_src_mout_onenand_list,
217 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
220 static struct clksrc_clk clk_mout_onenand = {
222 .name = "mout_onenand",
224 .sources = &clk_src_mout_onenand,
225 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
228 static struct clksrc_clk clk_div_onenand = {
230 .name = "div_onenand",
231 .parent = &clk_mout_onenand.clk,
233 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
236 static struct clksrc_clk clk_div_pclkd1 = {
238 .name = "div_pclkd1",
239 .parent = &clk_div_d1_bus.clk,
241 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
244 static struct clksrc_clk clk_div_cam = {
247 .parent = &clk_div_mpll2.clk,
249 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
252 static struct clksrc_clk clk_div_hdmi = {
255 .parent = &clk_mout_hpll.clk,
257 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
260 static u32 epll_div[][4] = {
261 { 32750000, 131, 3, 4 },
262 { 32768000, 131, 3, 4 },
263 { 36000000, 72, 3, 3 },
264 { 45000000, 90, 3, 3 },
265 { 45158000, 90, 3, 3 },
266 { 45158400, 90, 3, 3 },
267 { 48000000, 96, 3, 3 },
268 { 49125000, 131, 4, 3 },
269 { 49152000, 131, 4, 3 },
270 { 60000000, 120, 3, 3 },
271 { 67737600, 226, 5, 3 },
272 { 67738000, 226, 5, 3 },
273 { 73800000, 246, 5, 3 },
274 { 73728000, 246, 5, 3 },
275 { 72000000, 144, 3, 3 },
276 { 84000000, 168, 3, 3 },
277 { 96000000, 96, 3, 2 },
278 { 144000000, 144, 3, 2 },
279 { 192000000, 96, 3, 1 }
282 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
284 unsigned int epll_con;
287 if (clk->rate == rate) /* Return if nothing changed */
290 epll_con = __raw_readl(S5P_EPLL_CON);
292 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
294 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
295 if (epll_div[i][0] == rate) {
296 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
297 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
298 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
303 if (i == ARRAY_SIZE(epll_div)) {
304 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
308 __raw_writel(epll_con, S5P_EPLL_CON);
310 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
318 static struct clk_ops s5pc100_epll_ops = {
319 .get_rate = s5p_epll_get_rate,
320 .set_rate = s5pc100_epll_set_rate,
323 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
325 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
328 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
330 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
333 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
335 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
338 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
340 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
343 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
345 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
348 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
350 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
353 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
355 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
358 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
360 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
363 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
365 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
368 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
370 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
373 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
375 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
379 * The following clocks will be disabled during clock initialization. It is
380 * recommended to keep the following clocks disabled until the driver requests
381 * for enabling the clock.
383 static struct clk init_clocks_off[] = {
386 .parent = &clk_div_d0_bus.clk,
387 .enable = s5pc100_d0_0_ctrl,
391 .parent = &clk_div_d0_bus.clk,
392 .enable = s5pc100_d0_0_ctrl,
396 .parent = &clk_div_d0_bus.clk,
397 .enable = s5pc100_d0_0_ctrl,
401 .parent = &clk_div_d0_bus.clk,
402 .enable = s5pc100_d0_0_ctrl,
406 .parent = &clk_div_d0_bus.clk,
407 .enable = s5pc100_d0_0_ctrl,
411 .parent = &clk_div_d0_bus.clk,
412 .enable = s5pc100_d0_1_ctrl,
416 .parent = &clk_div_d0_bus.clk,
417 .enable = s5pc100_d0_1_ctrl,
421 .parent = &clk_div_d0_bus.clk,
422 .enable = s5pc100_d0_2_ctrl,
426 .parent = &clk_div_d0_bus.clk,
427 .enable = s5pc100_d0_2_ctrl,
431 .parent = &clk_div_d1_bus.clk,
432 .enable = s5pc100_d1_0_ctrl,
436 .parent = &clk_div_d1_bus.clk,
437 .enable = s5pc100_d1_0_ctrl,
441 .parent = &clk_div_d1_bus.clk,
442 .enable = s5pc100_d1_0_ctrl,
446 .devname = "dma-pl330.1",
447 .parent = &clk_div_d1_bus.clk,
448 .enable = s5pc100_d1_0_ctrl,
452 .devname = "dma-pl330.0",
453 .parent = &clk_div_d1_bus.clk,
454 .enable = s5pc100_d1_0_ctrl,
458 .parent = &clk_div_d1_bus.clk,
459 .enable = s5pc100_d1_1_ctrl,
463 .parent = &clk_div_d1_bus.clk,
464 .enable = s5pc100_d1_1_ctrl,
468 .devname = "s5p-fimc.0",
469 .parent = &clk_div_d1_bus.clk,
470 .enable = s5pc100_d1_1_ctrl,
474 .devname = "s5p-fimc.1",
475 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_1_ctrl,
480 .devname = "s5p-fimc.2",
481 .enable = s5pc100_d1_1_ctrl,
485 .parent = &clk_div_d1_bus.clk,
486 .enable = s5pc100_d1_1_ctrl,
490 .parent = &clk_div_d1_bus.clk,
491 .enable = s5pc100_d1_1_ctrl,
495 .parent = &clk_div_d1_bus.clk,
496 .enable = s5pc100_d1_1_ctrl,
500 .parent = &clk_div_d1_bus.clk,
501 .enable = s5pc100_d1_0_ctrl,
505 .parent = &clk_div_d1_bus.clk,
506 .enable = s5pc100_d1_2_ctrl,
510 .parent = &clk_div_d1_bus.clk,
511 .enable = s5pc100_d1_2_ctrl,
515 .parent = &clk_div_d1_bus.clk,
516 .enable = s5pc100_d1_2_ctrl,
520 .parent = &clk_div_d1_bus.clk,
521 .enable = s5pc100_d1_2_ctrl,
525 .parent = &clk_div_d1_bus.clk,
526 .enable = s5pc100_d1_2_ctrl,
530 .parent = &clk_div_d1_bus.clk,
531 .enable = s5pc100_d1_3_ctrl,
535 .parent = &clk_div_d1_bus.clk,
536 .enable = s5pc100_d1_3_ctrl,
540 .parent = &clk_div_d1_bus.clk,
541 .enable = s5pc100_d1_3_ctrl,
545 .parent = &clk_div_d1_bus.clk,
546 .enable = s5pc100_d1_3_ctrl,
550 .parent = &clk_div_d1_bus.clk,
551 .enable = s5pc100_d1_3_ctrl,
555 .devname = "s3c2440-i2c.0",
556 .parent = &clk_div_d1_bus.clk,
557 .enable = s5pc100_d1_4_ctrl,
561 .devname = "s3c2440-i2c.1",
562 .parent = &clk_div_d1_bus.clk,
563 .enable = s5pc100_d1_4_ctrl,
567 .devname = "s5pc100-spi.0",
568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_4_ctrl,
573 .devname = "s5pc100-spi.1",
574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_4_ctrl,
579 .devname = "s5pc100-spi.2",
580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_4_ctrl,
585 .parent = &clk_div_d1_bus.clk,
586 .enable = s5pc100_d1_4_ctrl,
590 .parent = &clk_div_d1_bus.clk,
591 .enable = s5pc100_d1_4_ctrl,
592 .ctrlbit = (1 << 10),
595 .parent = &clk_div_d1_bus.clk,
596 .enable = s5pc100_d1_4_ctrl,
597 .ctrlbit = (1 << 11),
600 .parent = &clk_div_d1_bus.clk,
601 .enable = s5pc100_d1_4_ctrl,
602 .ctrlbit = (1 << 12),
605 .parent = &clk_div_d1_bus.clk,
606 .enable = s5pc100_d1_4_ctrl,
607 .ctrlbit = (1 << 13),
610 .parent = &clk_div_pclkd1.clk,
611 .enable = s5pc100_d1_5_ctrl,
615 .devname = "samsung-pcm.0",
616 .parent = &clk_div_pclkd1.clk,
617 .enable = s5pc100_d1_5_ctrl,
621 .devname = "samsung-pcm.1",
622 .parent = &clk_div_pclkd1.clk,
623 .enable = s5pc100_d1_5_ctrl,
627 .parent = &clk_div_pclkd1.clk,
628 .enable = s5pc100_d1_5_ctrl,
632 .parent = &clk_div_pclkd1.clk,
633 .enable = s5pc100_d1_5_ctrl,
637 .parent = &clk_div_pclkd1.clk,
638 .enable = s5pc100_d1_5_ctrl,
642 .devname = "s3c-sdhci.0",
643 .parent = &clk_mout_48m.clk,
644 .enable = s5pc100_sclk0_ctrl,
645 .ctrlbit = (1 << 15),
648 .devname = "s3c-sdhci.1",
649 .parent = &clk_mout_48m.clk,
650 .enable = s5pc100_sclk0_ctrl,
651 .ctrlbit = (1 << 16),
654 .devname = "s3c-sdhci.2",
655 .parent = &clk_mout_48m.clk,
656 .enable = s5pc100_sclk0_ctrl,
657 .ctrlbit = (1 << 17),
661 static struct clk clk_hsmmc2 = {
663 .devname = "s3c-sdhci.2",
664 .parent = &clk_div_d1_bus.clk,
665 .enable = s5pc100_d1_0_ctrl,
669 static struct clk clk_hsmmc1 = {
671 .devname = "s3c-sdhci.1",
672 .parent = &clk_div_d1_bus.clk,
673 .enable = s5pc100_d1_0_ctrl,
677 static struct clk clk_hsmmc0 = {
679 .devname = "s3c-sdhci.0",
680 .parent = &clk_div_d1_bus.clk,
681 .enable = s5pc100_d1_0_ctrl,
685 static struct clk clk_48m_spi0 = {
687 .devname = "s5pc100-spi.0",
688 .parent = &clk_mout_48m.clk,
689 .enable = s5pc100_sclk0_ctrl,
693 static struct clk clk_48m_spi1 = {
695 .devname = "s5pc100-spi.1",
696 .parent = &clk_mout_48m.clk,
697 .enable = s5pc100_sclk0_ctrl,
701 static struct clk clk_48m_spi2 = {
703 .devname = "s5pc100-spi.2",
704 .parent = &clk_mout_48m.clk,
705 .enable = s5pc100_sclk0_ctrl,
709 static struct clk clk_i2s0 = {
711 .devname = "samsung-i2s.0",
712 .parent = &clk_div_pclkd1.clk,
713 .enable = s5pc100_d1_5_ctrl,
717 static struct clk clk_i2s1 = {
719 .devname = "samsung-i2s.1",
720 .parent = &clk_div_pclkd1.clk,
721 .enable = s5pc100_d1_5_ctrl,
725 static struct clk clk_i2s2 = {
727 .devname = "samsung-i2s.2",
728 .parent = &clk_div_pclkd1.clk,
729 .enable = s5pc100_d1_5_ctrl,
733 static struct clk clk_vclk54m = {
738 static struct clk clk_i2scdclk0 = {
739 .name = "i2s_cdclk0",
742 static struct clk clk_i2scdclk1 = {
743 .name = "i2s_cdclk1",
746 static struct clk clk_i2scdclk2 = {
747 .name = "i2s_cdclk2",
750 static struct clk clk_pcmcdclk0 = {
751 .name = "pcm_cdclk0",
754 static struct clk clk_pcmcdclk1 = {
755 .name = "pcm_cdclk1",
758 static struct clk *clk_src_group1_list[] = {
759 [0] = &clk_mout_epll.clk,
760 [1] = &clk_div_mpll2.clk,
762 [3] = &clk_mout_hpll.clk,
765 static struct clksrc_sources clk_src_group1 = {
766 .sources = clk_src_group1_list,
767 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
770 static struct clk *clk_src_group2_list[] = {
771 [0] = &clk_mout_epll.clk,
772 [1] = &clk_div_mpll.clk,
775 static struct clksrc_sources clk_src_group2 = {
776 .sources = clk_src_group2_list,
777 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
780 static struct clk *clk_src_group3_list[] = {
781 [0] = &clk_mout_epll.clk,
782 [1] = &clk_div_mpll.clk,
784 [3] = &clk_i2scdclk0,
785 [4] = &clk_pcmcdclk0,
786 [5] = &clk_mout_hpll.clk,
789 static struct clksrc_sources clk_src_group3 = {
790 .sources = clk_src_group3_list,
791 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
794 static struct clksrc_clk clk_sclk_audio0 = {
796 .name = "sclk_audio",
797 .devname = "samsung-pcm.0",
799 .enable = s5pc100_sclk1_ctrl,
801 .sources = &clk_src_group3,
802 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
803 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
806 static struct clk *clk_src_group4_list[] = {
807 [0] = &clk_mout_epll.clk,
808 [1] = &clk_div_mpll.clk,
810 [3] = &clk_i2scdclk1,
811 [4] = &clk_pcmcdclk1,
812 [5] = &clk_mout_hpll.clk,
815 static struct clksrc_sources clk_src_group4 = {
816 .sources = clk_src_group4_list,
817 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
820 static struct clksrc_clk clk_sclk_audio1 = {
822 .name = "sclk_audio",
823 .devname = "samsung-pcm.1",
825 .enable = s5pc100_sclk1_ctrl,
827 .sources = &clk_src_group4,
828 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
829 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
832 static struct clk *clk_src_group5_list[] = {
833 [0] = &clk_mout_epll.clk,
834 [1] = &clk_div_mpll.clk,
836 [3] = &clk_i2scdclk2,
837 [4] = &clk_mout_hpll.clk,
840 static struct clksrc_sources clk_src_group5 = {
841 .sources = clk_src_group5_list,
842 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
845 static struct clksrc_clk clk_sclk_audio2 = {
847 .name = "sclk_audio",
848 .devname = "samsung-pcm.2",
849 .ctrlbit = (1 << 10),
850 .enable = s5pc100_sclk1_ctrl,
852 .sources = &clk_src_group5,
853 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
854 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
857 static struct clk *clk_src_group6_list[] = {
860 [2] = &clk_div_hdmi.clk,
863 static struct clksrc_sources clk_src_group6 = {
864 .sources = clk_src_group6_list,
865 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
868 static struct clk *clk_src_group7_list[] = {
869 [0] = &clk_mout_epll.clk,
870 [1] = &clk_div_mpll.clk,
871 [2] = &clk_mout_hpll.clk,
875 static struct clksrc_sources clk_src_group7 = {
876 .sources = clk_src_group7_list,
877 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
880 static struct clk *clk_src_mmc0_list[] = {
881 [0] = &clk_mout_epll.clk,
882 [1] = &clk_div_mpll.clk,
886 static struct clksrc_sources clk_src_mmc0 = {
887 .sources = clk_src_mmc0_list,
888 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
891 static struct clk *clk_src_mmc12_list[] = {
892 [0] = &clk_mout_epll.clk,
893 [1] = &clk_div_mpll.clk,
895 [3] = &clk_mout_hpll.clk,
898 static struct clksrc_sources clk_src_mmc12 = {
899 .sources = clk_src_mmc12_list,
900 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
903 static struct clk *clk_src_irda_usb_list[] = {
904 [0] = &clk_mout_epll.clk,
905 [1] = &clk_div_mpll.clk,
907 [3] = &clk_mout_hpll.clk,
910 static struct clksrc_sources clk_src_irda_usb = {
911 .sources = clk_src_irda_usb_list,
912 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
915 static struct clk *clk_src_pwi_list[] = {
917 [1] = &clk_mout_epll.clk,
918 [2] = &clk_div_mpll.clk,
921 static struct clksrc_sources clk_src_pwi = {
922 .sources = clk_src_pwi_list,
923 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
926 static struct clk *clk_sclk_spdif_list[] = {
927 [0] = &clk_sclk_audio0.clk,
928 [1] = &clk_sclk_audio1.clk,
929 [2] = &clk_sclk_audio2.clk,
932 static struct clksrc_sources clk_src_sclk_spdif = {
933 .sources = clk_sclk_spdif_list,
934 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
937 static struct clksrc_clk clk_sclk_spdif = {
939 .name = "sclk_spdif",
940 .ctrlbit = (1 << 11),
941 .enable = s5pc100_sclk1_ctrl,
942 .ops = &s5p_sclk_spdif_ops,
944 .sources = &clk_src_sclk_spdif,
945 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
948 static struct clksrc_clk clksrcs[] = {
951 .name = "sclk_mixer",
953 .enable = s5pc100_sclk0_ctrl,
956 .sources = &clk_src_group6,
957 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
962 .enable = s5pc100_sclk1_ctrl,
965 .sources = &clk_src_group7,
966 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
967 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
971 .devname = "s5p-fimc.0",
973 .enable = s5pc100_sclk1_ctrl,
976 .sources = &clk_src_group7,
977 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
978 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
982 .devname = "s5p-fimc.1",
984 .enable = s5pc100_sclk1_ctrl,
987 .sources = &clk_src_group7,
988 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
989 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
993 .devname = "s5p-fimc.2",
995 .enable = s5pc100_sclk1_ctrl,
998 .sources = &clk_src_group7,
999 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1000 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1003 .name = "sclk_irda",
1004 .ctrlbit = (1 << 10),
1005 .enable = s5pc100_sclk0_ctrl,
1008 .sources = &clk_src_irda_usb,
1009 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1010 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1013 .name = "sclk_irda",
1014 .ctrlbit = (1 << 10),
1015 .enable = s5pc100_sclk0_ctrl,
1018 .sources = &clk_src_mmc12,
1019 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1020 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1024 .ctrlbit = (1 << 1),
1025 .enable = s5pc100_sclk0_ctrl,
1028 .sources = &clk_src_pwi,
1029 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1030 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1033 .name = "sclk_uhost",
1034 .ctrlbit = (1 << 11),
1035 .enable = s5pc100_sclk0_ctrl,
1038 .sources = &clk_src_irda_usb,
1039 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1040 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1044 static struct clksrc_clk clk_sclk_uart = {
1047 .ctrlbit = (1 << 3),
1048 .enable = s5pc100_sclk0_ctrl,
1050 .sources = &clk_src_group2,
1051 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1052 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1055 static struct clksrc_clk clk_sclk_mmc0 = {
1058 .devname = "s3c-sdhci.0",
1059 .ctrlbit = (1 << 12),
1060 .enable = s5pc100_sclk1_ctrl,
1062 .sources = &clk_src_mmc0,
1063 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1064 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1067 static struct clksrc_clk clk_sclk_mmc1 = {
1070 .devname = "s3c-sdhci.1",
1071 .ctrlbit = (1 << 13),
1072 .enable = s5pc100_sclk1_ctrl,
1074 .sources = &clk_src_mmc12,
1075 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1076 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1079 static struct clksrc_clk clk_sclk_mmc2 = {
1082 .devname = "s3c-sdhci.2",
1083 .ctrlbit = (1 << 14),
1084 .enable = s5pc100_sclk1_ctrl,
1086 .sources = &clk_src_mmc12,
1087 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1088 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1091 static struct clksrc_clk clk_sclk_spi0 = {
1094 .devname = "s5pc100-spi.0",
1095 .ctrlbit = (1 << 4),
1096 .enable = s5pc100_sclk0_ctrl,
1098 .sources = &clk_src_group1,
1099 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1100 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1103 static struct clksrc_clk clk_sclk_spi1 = {
1106 .devname = "s5pc100-spi.1",
1107 .ctrlbit = (1 << 5),
1108 .enable = s5pc100_sclk0_ctrl,
1110 .sources = &clk_src_group1,
1111 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1112 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1115 static struct clksrc_clk clk_sclk_spi2 = {
1118 .devname = "s5pc100-spi.2",
1119 .ctrlbit = (1 << 6),
1120 .enable = s5pc100_sclk0_ctrl,
1122 .sources = &clk_src_group1,
1123 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1124 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1127 /* Clock initialisation code */
1128 static struct clksrc_clk *sysclks[] = {
1156 static struct clk *clk_cdev[] = {
1168 static struct clksrc_clk *clksrc_cdev[] = {
1178 void __init_or_cpufreq s5pc100_setup_clocks(void)
1182 unsigned long hclkd0;
1183 unsigned long hclkd1;
1184 unsigned long pclkd0;
1185 unsigned long pclkd1;
1192 /* Set S5PC100 functions for clk_fout_epll */
1193 clk_fout_epll.enable = s5p_epll_enable;
1194 clk_fout_epll.ops = &s5pc100_epll_ops;
1196 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1198 xtal = clk_get_rate(&clk_xtal);
1200 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1202 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1203 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1204 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1205 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1207 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1208 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1210 clk_fout_apll.rate = apll;
1211 clk_fout_mpll.rate = mpll;
1212 clk_fout_epll.rate = epll;
1213 clk_mout_hpll.clk.rate = hpll;
1215 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1216 s3c_set_clksrc(&clksrcs[ptr], true);
1218 arm = clk_get_rate(&clk_div_arm.clk);
1219 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1220 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1221 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1222 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1224 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1225 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1228 clk_h.rate = hclkd1;
1229 clk_p.rate = pclkd1;
1233 * The following clocks will be enabled during clock initialization.
1235 static struct clk init_clocks[] = {
1238 .parent = &clk_div_d0_bus.clk,
1239 .enable = s5pc100_d0_0_ctrl,
1240 .ctrlbit = (1 << 1),
1243 .parent = &clk_div_d0_bus.clk,
1244 .enable = s5pc100_d0_0_ctrl,
1245 .ctrlbit = (1 << 0),
1248 .parent = &clk_div_d0_bus.clk,
1249 .enable = s5pc100_d0_1_ctrl,
1250 .ctrlbit = (1 << 5),
1253 .parent = &clk_div_d0_bus.clk,
1254 .enable = s5pc100_d0_1_ctrl,
1255 .ctrlbit = (1 << 4),
1258 .parent = &clk_div_d0_bus.clk,
1259 .enable = s5pc100_d0_1_ctrl,
1260 .ctrlbit = (1 << 1),
1263 .parent = &clk_div_d0_bus.clk,
1264 .enable = s5pc100_d0_1_ctrl,
1265 .ctrlbit = (1 << 0),
1268 .parent = &clk_div_d0_bus.clk,
1269 .enable = s5pc100_d0_1_ctrl,
1270 .ctrlbit = (1 << 0),
1273 .parent = &clk_div_d1_bus.clk,
1274 .enable = s5pc100_d1_3_ctrl,
1275 .ctrlbit = (1 << 1),
1278 .devname = "s3c6400-uart.0",
1279 .parent = &clk_div_d1_bus.clk,
1280 .enable = s5pc100_d1_4_ctrl,
1281 .ctrlbit = (1 << 0),
1284 .devname = "s3c6400-uart.1",
1285 .parent = &clk_div_d1_bus.clk,
1286 .enable = s5pc100_d1_4_ctrl,
1287 .ctrlbit = (1 << 1),
1290 .devname = "s3c6400-uart.2",
1291 .parent = &clk_div_d1_bus.clk,
1292 .enable = s5pc100_d1_4_ctrl,
1293 .ctrlbit = (1 << 2),
1296 .devname = "s3c6400-uart.3",
1297 .parent = &clk_div_d1_bus.clk,
1298 .enable = s5pc100_d1_4_ctrl,
1299 .ctrlbit = (1 << 3),
1302 .parent = &clk_div_d1_bus.clk,
1303 .enable = s5pc100_d1_3_ctrl,
1304 .ctrlbit = (1 << 6),
1308 static struct clk *clks[] __initdata = {
1317 static struct clk_lookup s5pc100_clk_lookup[] = {
1318 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1319 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1320 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1321 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1322 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1323 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1324 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1325 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1326 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1327 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
1328 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1329 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
1330 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1331 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
1332 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1333 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
1334 CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
1335 CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
1338 void __init s5pc100_register_clocks(void)
1342 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1344 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1345 s3c_register_clksrc(sysclks[ptr], 1);
1347 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1348 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1349 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1350 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1352 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1353 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1354 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1356 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1357 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1358 s3c_disable_clocks(clk_cdev[ptr], 1);
1360 s3c24xx_register_clock(&dummy_apb_pclk);