1 /* linux/arch/arm/mach-s5pc100/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PC100 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
23 #include <plat/cpu-freq.h>
24 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
28 #include <plat/s5p-clock.h>
29 #include <plat/clock-clksrc.h>
33 static struct clk s5p_clk_otgphy = {
37 static struct clk dummy_apb_pclk = {
42 static struct clk *clk_src_mout_href_list[] = {
47 static struct clksrc_sources clk_src_mout_href = {
48 .sources = clk_src_mout_href_list,
49 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
52 static struct clksrc_clk clk_mout_href = {
56 .sources = &clk_src_mout_href,
57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
60 static struct clk *clk_src_mout_48m_list[] = {
62 [1] = &s5p_clk_otgphy,
65 static struct clksrc_sources clk_src_mout_48m = {
66 .sources = clk_src_mout_48m_list,
67 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
70 static struct clksrc_clk clk_mout_48m = {
74 .sources = &clk_src_mout_48m,
75 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
78 static struct clksrc_clk clk_mout_mpll = {
82 .sources = &clk_src_mpll,
83 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
87 static struct clksrc_clk clk_mout_apll = {
91 .sources = &clk_src_apll,
92 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
95 static struct clksrc_clk clk_mout_epll = {
99 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
103 static struct clk *clk_src_mout_hpll_list[] = {
107 static struct clksrc_sources clk_src_mout_hpll = {
108 .sources = clk_src_mout_hpll_list,
109 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
112 static struct clksrc_clk clk_mout_hpll = {
116 .sources = &clk_src_mout_hpll,
117 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
120 static struct clksrc_clk clk_div_apll = {
123 .parent = &clk_mout_apll.clk,
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
128 static struct clksrc_clk clk_div_arm = {
131 .parent = &clk_div_apll.clk,
133 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
136 static struct clksrc_clk clk_div_d0_bus = {
138 .name = "div_d0_bus",
139 .parent = &clk_div_arm.clk,
141 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
144 static struct clksrc_clk clk_div_pclkd0 = {
146 .name = "div_pclkd0",
147 .parent = &clk_div_d0_bus.clk,
149 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
152 static struct clksrc_clk clk_div_secss = {
155 .parent = &clk_div_d0_bus.clk,
157 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
160 static struct clksrc_clk clk_div_apll2 = {
163 .parent = &clk_mout_apll.clk,
165 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
168 static struct clk *clk_src_mout_am_list[] = {
169 [0] = &clk_mout_mpll.clk,
170 [1] = &clk_div_apll2.clk,
173 struct clksrc_sources clk_src_mout_am = {
174 .sources = clk_src_mout_am_list,
175 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
178 static struct clksrc_clk clk_mout_am = {
182 .sources = &clk_src_mout_am,
183 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
186 static struct clksrc_clk clk_div_d1_bus = {
188 .name = "div_d1_bus",
189 .parent = &clk_mout_am.clk,
191 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
194 static struct clksrc_clk clk_div_mpll2 = {
197 .parent = &clk_mout_am.clk,
199 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
202 static struct clksrc_clk clk_div_mpll = {
205 .parent = &clk_mout_am.clk,
207 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
210 static struct clk *clk_src_mout_onenand_list[] = {
211 [0] = &clk_div_d0_bus.clk,
212 [1] = &clk_div_d1_bus.clk,
215 struct clksrc_sources clk_src_mout_onenand = {
216 .sources = clk_src_mout_onenand_list,
217 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
220 static struct clksrc_clk clk_mout_onenand = {
222 .name = "mout_onenand",
224 .sources = &clk_src_mout_onenand,
225 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
228 static struct clksrc_clk clk_div_onenand = {
230 .name = "div_onenand",
231 .parent = &clk_mout_onenand.clk,
233 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
236 static struct clksrc_clk clk_div_pclkd1 = {
238 .name = "div_pclkd1",
239 .parent = &clk_div_d1_bus.clk,
241 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
244 static struct clksrc_clk clk_div_cam = {
247 .parent = &clk_div_mpll2.clk,
249 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
252 static struct clksrc_clk clk_div_hdmi = {
255 .parent = &clk_mout_hpll.clk,
257 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
260 static u32 epll_div[][4] = {
261 { 32750000, 131, 3, 4 },
262 { 32768000, 131, 3, 4 },
263 { 36000000, 72, 3, 3 },
264 { 45000000, 90, 3, 3 },
265 { 45158000, 90, 3, 3 },
266 { 45158400, 90, 3, 3 },
267 { 48000000, 96, 3, 3 },
268 { 49125000, 131, 4, 3 },
269 { 49152000, 131, 4, 3 },
270 { 60000000, 120, 3, 3 },
271 { 67737600, 226, 5, 3 },
272 { 67738000, 226, 5, 3 },
273 { 73800000, 246, 5, 3 },
274 { 73728000, 246, 5, 3 },
275 { 72000000, 144, 3, 3 },
276 { 84000000, 168, 3, 3 },
277 { 96000000, 96, 3, 2 },
278 { 144000000, 144, 3, 2 },
279 { 192000000, 96, 3, 1 }
282 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
284 unsigned int epll_con;
287 if (clk->rate == rate) /* Return if nothing changed */
290 epll_con = __raw_readl(S5P_EPLL_CON);
292 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
294 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
295 if (epll_div[i][0] == rate) {
296 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
297 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
298 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
303 if (i == ARRAY_SIZE(epll_div)) {
304 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
308 __raw_writel(epll_con, S5P_EPLL_CON);
310 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
318 static struct clk_ops s5pc100_epll_ops = {
319 .get_rate = s5p_epll_get_rate,
320 .set_rate = s5pc100_epll_set_rate,
323 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
325 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
328 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
330 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
333 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
335 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
338 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
340 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
343 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
345 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
348 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
350 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
353 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
355 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
358 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
360 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
363 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
365 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
368 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
370 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
373 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
375 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
379 * The following clocks will be disabled during clock initialization. It is
380 * recommended to keep the following clocks disabled until the driver requests
381 * for enabling the clock.
383 static struct clk init_clocks_off[] = {
386 .parent = &clk_div_d0_bus.clk,
387 .enable = s5pc100_d0_0_ctrl,
391 .parent = &clk_div_d0_bus.clk,
392 .enable = s5pc100_d0_0_ctrl,
396 .parent = &clk_div_d0_bus.clk,
397 .enable = s5pc100_d0_0_ctrl,
401 .parent = &clk_div_d0_bus.clk,
402 .enable = s5pc100_d0_0_ctrl,
406 .parent = &clk_div_d0_bus.clk,
407 .enable = s5pc100_d0_0_ctrl,
411 .parent = &clk_div_d0_bus.clk,
412 .enable = s5pc100_d0_1_ctrl,
416 .parent = &clk_div_d0_bus.clk,
417 .enable = s5pc100_d0_1_ctrl,
421 .parent = &clk_div_d0_bus.clk,
422 .enable = s5pc100_d0_2_ctrl,
426 .parent = &clk_div_d0_bus.clk,
427 .enable = s5pc100_d0_2_ctrl,
431 .devname = "s3c-sdhci.2",
432 .parent = &clk_div_d1_bus.clk,
433 .enable = s5pc100_d1_0_ctrl,
437 .devname = "s3c-sdhci.1",
438 .parent = &clk_div_d1_bus.clk,
439 .enable = s5pc100_d1_0_ctrl,
443 .devname = "s3c-sdhci.0",
444 .parent = &clk_div_d1_bus.clk,
445 .enable = s5pc100_d1_0_ctrl,
449 .parent = &clk_div_d1_bus.clk,
450 .enable = s5pc100_d1_0_ctrl,
454 .parent = &clk_div_d1_bus.clk,
455 .enable = s5pc100_d1_0_ctrl,
459 .parent = &clk_div_d1_bus.clk,
460 .enable = s5pc100_d1_0_ctrl,
464 .devname = "dma-pl330.1",
465 .parent = &clk_div_d1_bus.clk,
466 .enable = s5pc100_d1_0_ctrl,
470 .devname = "dma-pl330.0",
471 .parent = &clk_div_d1_bus.clk,
472 .enable = s5pc100_d1_0_ctrl,
476 .parent = &clk_div_d1_bus.clk,
477 .enable = s5pc100_d1_1_ctrl,
481 .parent = &clk_div_d1_bus.clk,
482 .enable = s5pc100_d1_1_ctrl,
486 .devname = "s5p-fimc.0",
487 .parent = &clk_div_d1_bus.clk,
488 .enable = s5pc100_d1_1_ctrl,
492 .devname = "s5p-fimc.1",
493 .parent = &clk_div_d1_bus.clk,
494 .enable = s5pc100_d1_1_ctrl,
498 .devname = "s5p-fimc.2",
499 .enable = s5pc100_d1_1_ctrl,
503 .parent = &clk_div_d1_bus.clk,
504 .enable = s5pc100_d1_1_ctrl,
508 .parent = &clk_div_d1_bus.clk,
509 .enable = s5pc100_d1_1_ctrl,
513 .parent = &clk_div_d1_bus.clk,
514 .enable = s5pc100_d1_1_ctrl,
518 .parent = &clk_div_d1_bus.clk,
519 .enable = s5pc100_d1_0_ctrl,
523 .parent = &clk_div_d1_bus.clk,
524 .enable = s5pc100_d1_2_ctrl,
528 .parent = &clk_div_d1_bus.clk,
529 .enable = s5pc100_d1_2_ctrl,
533 .parent = &clk_div_d1_bus.clk,
534 .enable = s5pc100_d1_2_ctrl,
538 .parent = &clk_div_d1_bus.clk,
539 .enable = s5pc100_d1_2_ctrl,
543 .parent = &clk_div_d1_bus.clk,
544 .enable = s5pc100_d1_2_ctrl,
548 .parent = &clk_div_d1_bus.clk,
549 .enable = s5pc100_d1_3_ctrl,
553 .parent = &clk_div_d1_bus.clk,
554 .enable = s5pc100_d1_3_ctrl,
558 .parent = &clk_div_d1_bus.clk,
559 .enable = s5pc100_d1_3_ctrl,
563 .parent = &clk_div_d1_bus.clk,
564 .enable = s5pc100_d1_3_ctrl,
568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_3_ctrl,
573 .devname = "s3c2440-i2c.0",
574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_4_ctrl,
579 .devname = "s3c2440-i2c.1",
580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_4_ctrl,
585 .devname = "s3c64xx-spi.0",
586 .parent = &clk_div_d1_bus.clk,
587 .enable = s5pc100_d1_4_ctrl,
591 .devname = "s3c64xx-spi.1",
592 .parent = &clk_div_d1_bus.clk,
593 .enable = s5pc100_d1_4_ctrl,
597 .devname = "s3c64xx-spi.2",
598 .parent = &clk_div_d1_bus.clk,
599 .enable = s5pc100_d1_4_ctrl,
603 .parent = &clk_div_d1_bus.clk,
604 .enable = s5pc100_d1_4_ctrl,
608 .parent = &clk_div_d1_bus.clk,
609 .enable = s5pc100_d1_4_ctrl,
610 .ctrlbit = (1 << 10),
613 .parent = &clk_div_d1_bus.clk,
614 .enable = s5pc100_d1_4_ctrl,
615 .ctrlbit = (1 << 11),
618 .parent = &clk_div_d1_bus.clk,
619 .enable = s5pc100_d1_4_ctrl,
620 .ctrlbit = (1 << 12),
623 .parent = &clk_div_d1_bus.clk,
624 .enable = s5pc100_d1_4_ctrl,
625 .ctrlbit = (1 << 13),
628 .devname = "samsung-i2s.0",
629 .parent = &clk_div_pclkd1.clk,
630 .enable = s5pc100_d1_5_ctrl,
634 .devname = "samsung-i2s.1",
635 .parent = &clk_div_pclkd1.clk,
636 .enable = s5pc100_d1_5_ctrl,
640 .devname = "samsung-i2s.2",
641 .parent = &clk_div_pclkd1.clk,
642 .enable = s5pc100_d1_5_ctrl,
646 .parent = &clk_div_pclkd1.clk,
647 .enable = s5pc100_d1_5_ctrl,
651 .devname = "samsung-pcm.0",
652 .parent = &clk_div_pclkd1.clk,
653 .enable = s5pc100_d1_5_ctrl,
657 .devname = "samsung-pcm.1",
658 .parent = &clk_div_pclkd1.clk,
659 .enable = s5pc100_d1_5_ctrl,
663 .parent = &clk_div_pclkd1.clk,
664 .enable = s5pc100_d1_5_ctrl,
668 .parent = &clk_div_pclkd1.clk,
669 .enable = s5pc100_d1_5_ctrl,
673 .parent = &clk_div_pclkd1.clk,
674 .enable = s5pc100_d1_5_ctrl,
678 .devname = "s3c64xx-spi.0",
679 .parent = &clk_mout_48m.clk,
680 .enable = s5pc100_sclk0_ctrl,
684 .devname = "s3c64xx-spi.1",
685 .parent = &clk_mout_48m.clk,
686 .enable = s5pc100_sclk0_ctrl,
690 .devname = "s3c64xx-spi.2",
691 .parent = &clk_mout_48m.clk,
692 .enable = s5pc100_sclk0_ctrl,
696 .devname = "s3c-sdhci.0",
697 .parent = &clk_mout_48m.clk,
698 .enable = s5pc100_sclk0_ctrl,
699 .ctrlbit = (1 << 15),
702 .devname = "s3c-sdhci.1",
703 .parent = &clk_mout_48m.clk,
704 .enable = s5pc100_sclk0_ctrl,
705 .ctrlbit = (1 << 16),
708 .devname = "s3c-sdhci.2",
709 .parent = &clk_mout_48m.clk,
710 .enable = s5pc100_sclk0_ctrl,
711 .ctrlbit = (1 << 17),
715 static struct clk clk_vclk54m = {
720 static struct clk clk_i2scdclk0 = {
721 .name = "i2s_cdclk0",
724 static struct clk clk_i2scdclk1 = {
725 .name = "i2s_cdclk1",
728 static struct clk clk_i2scdclk2 = {
729 .name = "i2s_cdclk2",
732 static struct clk clk_pcmcdclk0 = {
733 .name = "pcm_cdclk0",
736 static struct clk clk_pcmcdclk1 = {
737 .name = "pcm_cdclk1",
740 static struct clk *clk_src_group1_list[] = {
741 [0] = &clk_mout_epll.clk,
742 [1] = &clk_div_mpll2.clk,
744 [3] = &clk_mout_hpll.clk,
747 struct clksrc_sources clk_src_group1 = {
748 .sources = clk_src_group1_list,
749 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
752 static struct clk *clk_src_group2_list[] = {
753 [0] = &clk_mout_epll.clk,
754 [1] = &clk_div_mpll.clk,
757 struct clksrc_sources clk_src_group2 = {
758 .sources = clk_src_group2_list,
759 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
762 static struct clk *clk_src_group3_list[] = {
763 [0] = &clk_mout_epll.clk,
764 [1] = &clk_div_mpll.clk,
766 [3] = &clk_i2scdclk0,
767 [4] = &clk_pcmcdclk0,
768 [5] = &clk_mout_hpll.clk,
771 struct clksrc_sources clk_src_group3 = {
772 .sources = clk_src_group3_list,
773 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
776 static struct clksrc_clk clk_sclk_audio0 = {
778 .name = "sclk_audio",
779 .devname = "samsung-pcm.0",
781 .enable = s5pc100_sclk1_ctrl,
783 .sources = &clk_src_group3,
784 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
785 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
788 static struct clk *clk_src_group4_list[] = {
789 [0] = &clk_mout_epll.clk,
790 [1] = &clk_div_mpll.clk,
792 [3] = &clk_i2scdclk1,
793 [4] = &clk_pcmcdclk1,
794 [5] = &clk_mout_hpll.clk,
797 struct clksrc_sources clk_src_group4 = {
798 .sources = clk_src_group4_list,
799 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
802 static struct clksrc_clk clk_sclk_audio1 = {
804 .name = "sclk_audio",
805 .devname = "samsung-pcm.1",
807 .enable = s5pc100_sclk1_ctrl,
809 .sources = &clk_src_group4,
810 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
811 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
814 static struct clk *clk_src_group5_list[] = {
815 [0] = &clk_mout_epll.clk,
816 [1] = &clk_div_mpll.clk,
818 [3] = &clk_i2scdclk2,
819 [4] = &clk_mout_hpll.clk,
822 struct clksrc_sources clk_src_group5 = {
823 .sources = clk_src_group5_list,
824 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
827 static struct clksrc_clk clk_sclk_audio2 = {
829 .name = "sclk_audio",
830 .devname = "samsung-pcm.2",
831 .ctrlbit = (1 << 10),
832 .enable = s5pc100_sclk1_ctrl,
834 .sources = &clk_src_group5,
835 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
836 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
839 static struct clk *clk_src_group6_list[] = {
842 [2] = &clk_div_hdmi.clk,
845 struct clksrc_sources clk_src_group6 = {
846 .sources = clk_src_group6_list,
847 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
850 static struct clk *clk_src_group7_list[] = {
851 [0] = &clk_mout_epll.clk,
852 [1] = &clk_div_mpll.clk,
853 [2] = &clk_mout_hpll.clk,
857 struct clksrc_sources clk_src_group7 = {
858 .sources = clk_src_group7_list,
859 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
862 static struct clk *clk_src_mmc0_list[] = {
863 [0] = &clk_mout_epll.clk,
864 [1] = &clk_div_mpll.clk,
868 struct clksrc_sources clk_src_mmc0 = {
869 .sources = clk_src_mmc0_list,
870 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
873 static struct clk *clk_src_mmc12_list[] = {
874 [0] = &clk_mout_epll.clk,
875 [1] = &clk_div_mpll.clk,
877 [3] = &clk_mout_hpll.clk,
880 struct clksrc_sources clk_src_mmc12 = {
881 .sources = clk_src_mmc12_list,
882 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
885 static struct clk *clk_src_irda_usb_list[] = {
886 [0] = &clk_mout_epll.clk,
887 [1] = &clk_div_mpll.clk,
889 [3] = &clk_mout_hpll.clk,
892 struct clksrc_sources clk_src_irda_usb = {
893 .sources = clk_src_irda_usb_list,
894 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
897 static struct clk *clk_src_pwi_list[] = {
899 [1] = &clk_mout_epll.clk,
900 [2] = &clk_div_mpll.clk,
903 struct clksrc_sources clk_src_pwi = {
904 .sources = clk_src_pwi_list,
905 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
908 static struct clk *clk_sclk_spdif_list[] = {
909 [0] = &clk_sclk_audio0.clk,
910 [1] = &clk_sclk_audio1.clk,
911 [2] = &clk_sclk_audio2.clk,
914 struct clksrc_sources clk_src_sclk_spdif = {
915 .sources = clk_sclk_spdif_list,
916 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
919 static struct clksrc_clk clk_sclk_spdif = {
921 .name = "sclk_spdif",
922 .ctrlbit = (1 << 11),
923 .enable = s5pc100_sclk1_ctrl,
924 .ops = &s5p_sclk_spdif_ops,
926 .sources = &clk_src_sclk_spdif,
927 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
930 static struct clksrc_clk clksrcs[] = {
934 .devname = "s3c64xx-spi.0",
936 .enable = s5pc100_sclk0_ctrl,
939 .sources = &clk_src_group1,
940 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
941 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
945 .devname = "s3c64xx-spi.1",
947 .enable = s5pc100_sclk0_ctrl,
950 .sources = &clk_src_group1,
951 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
952 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
956 .devname = "s3c64xx-spi.2",
958 .enable = s5pc100_sclk0_ctrl,
961 .sources = &clk_src_group1,
962 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
963 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
968 .enable = s5pc100_sclk0_ctrl,
971 .sources = &clk_src_group2,
972 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
973 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
976 .name = "sclk_mixer",
978 .enable = s5pc100_sclk0_ctrl,
981 .sources = &clk_src_group6,
982 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
987 .enable = s5pc100_sclk1_ctrl,
990 .sources = &clk_src_group7,
991 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
992 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
996 .devname = "s5p-fimc.0",
998 .enable = s5pc100_sclk1_ctrl,
1001 .sources = &clk_src_group7,
1002 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
1003 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
1006 .name = "sclk_fimc",
1007 .devname = "s5p-fimc.1",
1008 .ctrlbit = (1 << 2),
1009 .enable = s5pc100_sclk1_ctrl,
1012 .sources = &clk_src_group7,
1013 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1014 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1017 .name = "sclk_fimc",
1018 .devname = "s5p-fimc.2",
1019 .ctrlbit = (1 << 3),
1020 .enable = s5pc100_sclk1_ctrl,
1023 .sources = &clk_src_group7,
1024 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1025 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1029 .devname = "s3c-sdhci.0",
1030 .ctrlbit = (1 << 12),
1031 .enable = s5pc100_sclk1_ctrl,
1034 .sources = &clk_src_mmc0,
1035 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1036 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1040 .devname = "s3c-sdhci.1",
1041 .ctrlbit = (1 << 13),
1042 .enable = s5pc100_sclk1_ctrl,
1045 .sources = &clk_src_mmc12,
1046 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1047 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1051 .devname = "s3c-sdhci.2",
1052 .ctrlbit = (1 << 14),
1053 .enable = s5pc100_sclk1_ctrl,
1056 .sources = &clk_src_mmc12,
1057 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1058 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1061 .name = "sclk_irda",
1062 .ctrlbit = (1 << 10),
1063 .enable = s5pc100_sclk0_ctrl,
1066 .sources = &clk_src_irda_usb,
1067 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1068 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1071 .name = "sclk_irda",
1072 .ctrlbit = (1 << 10),
1073 .enable = s5pc100_sclk0_ctrl,
1076 .sources = &clk_src_mmc12,
1077 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1078 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1082 .ctrlbit = (1 << 1),
1083 .enable = s5pc100_sclk0_ctrl,
1086 .sources = &clk_src_pwi,
1087 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1088 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1091 .name = "sclk_uhost",
1092 .ctrlbit = (1 << 11),
1093 .enable = s5pc100_sclk0_ctrl,
1096 .sources = &clk_src_irda_usb,
1097 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1098 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1102 /* Clock initialisation code */
1103 static struct clksrc_clk *sysclks[] = {
1131 void __init_or_cpufreq s5pc100_setup_clocks(void)
1135 unsigned long hclkd0;
1136 unsigned long hclkd1;
1137 unsigned long pclkd0;
1138 unsigned long pclkd1;
1145 /* Set S5PC100 functions for clk_fout_epll */
1146 clk_fout_epll.enable = s5p_epll_enable;
1147 clk_fout_epll.ops = &s5pc100_epll_ops;
1149 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1151 xtal = clk_get_rate(&clk_xtal);
1153 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1155 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1156 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1157 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1158 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1160 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1161 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1163 clk_fout_apll.rate = apll;
1164 clk_fout_mpll.rate = mpll;
1165 clk_fout_epll.rate = epll;
1166 clk_mout_hpll.clk.rate = hpll;
1168 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1169 s3c_set_clksrc(&clksrcs[ptr], true);
1171 arm = clk_get_rate(&clk_div_arm.clk);
1172 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1173 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1174 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1175 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1177 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1178 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1181 clk_h.rate = hclkd1;
1182 clk_p.rate = pclkd1;
1186 * The following clocks will be enabled during clock initialization.
1188 static struct clk init_clocks[] = {
1191 .parent = &clk_div_d0_bus.clk,
1192 .enable = s5pc100_d0_0_ctrl,
1193 .ctrlbit = (1 << 1),
1196 .parent = &clk_div_d0_bus.clk,
1197 .enable = s5pc100_d0_0_ctrl,
1198 .ctrlbit = (1 << 0),
1201 .parent = &clk_div_d0_bus.clk,
1202 .enable = s5pc100_d0_1_ctrl,
1203 .ctrlbit = (1 << 5),
1206 .parent = &clk_div_d0_bus.clk,
1207 .enable = s5pc100_d0_1_ctrl,
1208 .ctrlbit = (1 << 4),
1211 .parent = &clk_div_d0_bus.clk,
1212 .enable = s5pc100_d0_1_ctrl,
1213 .ctrlbit = (1 << 1),
1216 .parent = &clk_div_d0_bus.clk,
1217 .enable = s5pc100_d0_1_ctrl,
1218 .ctrlbit = (1 << 0),
1221 .parent = &clk_div_d0_bus.clk,
1222 .enable = s5pc100_d0_1_ctrl,
1223 .ctrlbit = (1 << 0),
1226 .parent = &clk_div_d1_bus.clk,
1227 .enable = s5pc100_d1_3_ctrl,
1228 .ctrlbit = (1 << 1),
1231 .devname = "s3c6400-uart.0",
1232 .parent = &clk_div_d1_bus.clk,
1233 .enable = s5pc100_d1_4_ctrl,
1234 .ctrlbit = (1 << 0),
1237 .devname = "s3c6400-uart.1",
1238 .parent = &clk_div_d1_bus.clk,
1239 .enable = s5pc100_d1_4_ctrl,
1240 .ctrlbit = (1 << 1),
1243 .devname = "s3c6400-uart.2",
1244 .parent = &clk_div_d1_bus.clk,
1245 .enable = s5pc100_d1_4_ctrl,
1246 .ctrlbit = (1 << 2),
1249 .devname = "s3c6400-uart.3",
1250 .parent = &clk_div_d1_bus.clk,
1251 .enable = s5pc100_d1_4_ctrl,
1252 .ctrlbit = (1 << 3),
1255 .parent = &clk_div_d1_bus.clk,
1256 .enable = s5pc100_d1_3_ctrl,
1257 .ctrlbit = (1 << 6),
1261 static struct clk *clks[] __initdata = {
1270 void __init s5pc100_register_clocks(void)
1274 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1276 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1277 s3c_register_clksrc(sysclks[ptr], 1);
1279 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1280 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1282 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1283 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1285 s3c24xx_register_clock(&dummy_apb_pclk);