1 /* linux/arch/arm/mach-s5pc100/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PC100 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
23 #include <plat/cpu-freq.h>
24 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
28 #include <plat/s5p-clock.h>
29 #include <plat/clock-clksrc.h>
30 #include <plat/s5pc100.h>
32 static struct clk s5p_clk_otgphy = {
37 static struct clk *clk_src_mout_href_list[] = {
42 static struct clksrc_sources clk_src_mout_href = {
43 .sources = clk_src_mout_href_list,
44 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
47 static struct clksrc_clk clk_mout_href = {
52 .sources = &clk_src_mout_href,
53 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
56 static struct clk *clk_src_mout_48m_list[] = {
58 [1] = &s5p_clk_otgphy,
61 static struct clksrc_sources clk_src_mout_48m = {
62 .sources = clk_src_mout_48m_list,
63 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
66 static struct clksrc_clk clk_mout_48m = {
71 .sources = &clk_src_mout_48m,
72 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
75 static struct clksrc_clk clk_mout_mpll = {
80 .sources = &clk_src_mpll,
81 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
85 static struct clksrc_clk clk_mout_apll = {
90 .sources = &clk_src_apll,
91 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
94 static struct clksrc_clk clk_mout_epll = {
99 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
103 static struct clk *clk_src_mout_hpll_list[] = {
107 static struct clksrc_sources clk_src_mout_hpll = {
108 .sources = clk_src_mout_hpll_list,
109 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
112 static struct clksrc_clk clk_mout_hpll = {
117 .sources = &clk_src_mout_hpll,
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
121 static struct clksrc_clk clk_div_apll = {
125 .parent = &clk_mout_apll.clk,
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
130 static struct clksrc_clk clk_div_arm = {
134 .parent = &clk_div_apll.clk,
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
139 static struct clksrc_clk clk_div_d0_bus = {
141 .name = "div_d0_bus",
143 .parent = &clk_div_arm.clk,
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
148 static struct clksrc_clk clk_div_pclkd0 = {
150 .name = "div_pclkd0",
152 .parent = &clk_div_d0_bus.clk,
154 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
157 static struct clksrc_clk clk_div_secss = {
161 .parent = &clk_div_d0_bus.clk,
163 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
166 static struct clksrc_clk clk_div_apll2 = {
170 .parent = &clk_mout_apll.clk,
172 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
175 static struct clk *clk_src_mout_am_list[] = {
176 [0] = &clk_mout_mpll.clk,
177 [1] = &clk_div_apll2.clk,
180 struct clksrc_sources clk_src_mout_am = {
181 .sources = clk_src_mout_am_list,
182 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
185 static struct clksrc_clk clk_mout_am = {
190 .sources = &clk_src_mout_am,
191 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
194 static struct clksrc_clk clk_div_d1_bus = {
196 .name = "div_d1_bus",
198 .parent = &clk_mout_am.clk,
200 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
203 static struct clksrc_clk clk_div_mpll2 = {
207 .parent = &clk_mout_am.clk,
209 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
212 static struct clksrc_clk clk_div_mpll = {
216 .parent = &clk_mout_am.clk,
218 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
221 static struct clk *clk_src_mout_onenand_list[] = {
222 [0] = &clk_div_d0_bus.clk,
223 [1] = &clk_div_d1_bus.clk,
226 struct clksrc_sources clk_src_mout_onenand = {
227 .sources = clk_src_mout_onenand_list,
228 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
231 static struct clksrc_clk clk_mout_onenand = {
233 .name = "mout_onenand",
236 .sources = &clk_src_mout_onenand,
237 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
240 static struct clksrc_clk clk_div_onenand = {
242 .name = "div_onenand",
244 .parent = &clk_mout_onenand.clk,
246 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
249 static struct clksrc_clk clk_div_pclkd1 = {
251 .name = "div_pclkd1",
253 .parent = &clk_div_d1_bus.clk,
255 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
258 static struct clksrc_clk clk_div_cam = {
262 .parent = &clk_div_mpll2.clk,
264 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
267 static struct clksrc_clk clk_div_hdmi = {
271 .parent = &clk_mout_hpll.clk,
273 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
276 static u32 epll_div[][4] = {
277 { 32750000, 131, 3, 4 },
278 { 32768000, 131, 3, 4 },
279 { 36000000, 72, 3, 3 },
280 { 45000000, 90, 3, 3 },
281 { 45158000, 90, 3, 3 },
282 { 45158400, 90, 3, 3 },
283 { 48000000, 96, 3, 3 },
284 { 49125000, 131, 4, 3 },
285 { 49152000, 131, 4, 3 },
286 { 60000000, 120, 3, 3 },
287 { 67737600, 226, 5, 3 },
288 { 67738000, 226, 5, 3 },
289 { 73800000, 246, 5, 3 },
290 { 73728000, 246, 5, 3 },
291 { 72000000, 144, 3, 3 },
292 { 84000000, 168, 3, 3 },
293 { 96000000, 96, 3, 2 },
294 { 144000000, 144, 3, 2 },
295 { 192000000, 96, 3, 1 }
298 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
300 unsigned int epll_con;
303 if (clk->rate == rate) /* Return if nothing changed */
306 epll_con = __raw_readl(S5P_EPLL_CON);
308 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
310 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
311 if (epll_div[i][0] == rate) {
312 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
313 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
314 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
319 if (i == ARRAY_SIZE(epll_div)) {
320 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
324 __raw_writel(epll_con, S5P_EPLL_CON);
326 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
334 static struct clk_ops s5pc100_epll_ops = {
335 .get_rate = s5p_epll_get_rate,
336 .set_rate = s5pc100_epll_set_rate,
339 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
341 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
344 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
346 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
349 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
351 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
354 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
356 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
359 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
361 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
364 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
366 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
369 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
371 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
374 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
376 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
379 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
381 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
384 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
386 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
389 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
391 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
395 * The following clocks will be disabled during clock initialization. It is
396 * recommended to keep the following clocks disabled until the driver requests
397 * for enabling the clock.
399 static struct clk init_clocks_disable[] = {
403 .parent = &clk_div_d0_bus.clk,
404 .enable = s5pc100_d0_0_ctrl,
409 .parent = &clk_div_d0_bus.clk,
410 .enable = s5pc100_d0_0_ctrl,
415 .parent = &clk_div_d0_bus.clk,
416 .enable = s5pc100_d0_0_ctrl,
421 .parent = &clk_div_d0_bus.clk,
422 .enable = s5pc100_d0_0_ctrl,
427 .parent = &clk_div_d0_bus.clk,
428 .enable = s5pc100_d0_0_ctrl,
433 .parent = &clk_div_d0_bus.clk,
434 .enable = s5pc100_d0_1_ctrl,
439 .parent = &clk_div_d0_bus.clk,
440 .enable = s5pc100_d0_1_ctrl,
445 .parent = &clk_div_d0_bus.clk,
446 .enable = s5pc100_d0_2_ctrl,
451 .parent = &clk_div_d0_bus.clk,
452 .enable = s5pc100_d0_2_ctrl,
457 .parent = &clk_div_d1_bus.clk,
458 .enable = s5pc100_d1_0_ctrl,
463 .parent = &clk_div_d1_bus.clk,
464 .enable = s5pc100_d1_0_ctrl,
469 .parent = &clk_div_d1_bus.clk,
470 .enable = s5pc100_d1_0_ctrl,
475 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_0_ctrl,
481 .parent = &clk_div_d1_bus.clk,
482 .enable = s5pc100_d1_0_ctrl,
487 .parent = &clk_div_d1_bus.clk,
488 .enable = s5pc100_d1_0_ctrl,
493 .parent = &clk_div_d1_bus.clk,
494 .enable = s5pc100_d1_0_ctrl,
499 .parent = &clk_div_d1_bus.clk,
500 .enable = s5pc100_d1_0_ctrl,
505 .parent = &clk_div_d1_bus.clk,
506 .enable = s5pc100_d1_1_ctrl,
511 .parent = &clk_div_d1_bus.clk,
512 .enable = s5pc100_d1_1_ctrl,
517 .parent = &clk_div_d1_bus.clk,
518 .enable = s5pc100_d1_1_ctrl,
523 .parent = &clk_div_d1_bus.clk,
524 .enable = s5pc100_d1_1_ctrl,
529 .parent = &clk_div_d1_bus.clk,
530 .enable = s5pc100_d1_1_ctrl,
535 .parent = &clk_div_d1_bus.clk,
536 .enable = s5pc100_d1_1_ctrl,
541 .parent = &clk_div_d1_bus.clk,
542 .enable = s5pc100_d1_1_ctrl,
547 .parent = &clk_div_d1_bus.clk,
548 .enable = s5pc100_d1_1_ctrl,
553 .parent = &clk_div_d1_bus.clk,
554 .enable = s5pc100_d1_0_ctrl,
559 .parent = &clk_div_d1_bus.clk,
560 .enable = s5pc100_d1_2_ctrl,
565 .parent = &clk_div_d1_bus.clk,
566 .enable = s5pc100_d1_2_ctrl,
571 .parent = &clk_div_d1_bus.clk,
572 .enable = s5pc100_d1_2_ctrl,
577 .parent = &clk_div_d1_bus.clk,
578 .enable = s5pc100_d1_2_ctrl,
583 .parent = &clk_div_d1_bus.clk,
584 .enable = s5pc100_d1_2_ctrl,
589 .parent = &clk_div_d1_bus.clk,
590 .enable = s5pc100_d1_3_ctrl,
595 .parent = &clk_div_d1_bus.clk,
596 .enable = s5pc100_d1_3_ctrl,
601 .parent = &clk_div_d1_bus.clk,
602 .enable = s5pc100_d1_3_ctrl,
607 .parent = &clk_div_d1_bus.clk,
608 .enable = s5pc100_d1_3_ctrl,
613 .parent = &clk_div_d1_bus.clk,
614 .enable = s5pc100_d1_3_ctrl,
619 .parent = &clk_div_d1_bus.clk,
620 .enable = s5pc100_d1_4_ctrl,
625 .parent = &clk_div_d1_bus.clk,
626 .enable = s5pc100_d1_4_ctrl,
631 .parent = &clk_div_d1_bus.clk,
632 .enable = s5pc100_d1_4_ctrl,
637 .parent = &clk_div_d1_bus.clk,
638 .enable = s5pc100_d1_4_ctrl,
643 .parent = &clk_div_d1_bus.clk,
644 .enable = s5pc100_d1_4_ctrl,
649 .parent = &clk_div_d1_bus.clk,
650 .enable = s5pc100_d1_4_ctrl,
655 .parent = &clk_div_d1_bus.clk,
656 .enable = s5pc100_d1_4_ctrl,
657 .ctrlbit = (1 << 10),
661 .parent = &clk_div_d1_bus.clk,
662 .enable = s5pc100_d1_4_ctrl,
663 .ctrlbit = (1 << 11),
667 .parent = &clk_div_d1_bus.clk,
668 .enable = s5pc100_d1_4_ctrl,
669 .ctrlbit = (1 << 12),
673 .parent = &clk_div_d1_bus.clk,
674 .enable = s5pc100_d1_4_ctrl,
675 .ctrlbit = (1 << 13),
679 .parent = &clk_div_d1_bus.clk,
680 .enable = s5pc100_d1_5_ctrl,
685 .parent = &clk_div_d1_bus.clk,
686 .enable = s5pc100_d1_5_ctrl,
691 .parent = &clk_div_d1_bus.clk,
692 .enable = s5pc100_d1_5_ctrl,
697 .parent = &clk_div_d1_bus.clk,
698 .enable = s5pc100_d1_5_ctrl,
703 .parent = &clk_div_d1_bus.clk,
704 .enable = s5pc100_d1_5_ctrl,
709 .parent = &clk_div_d1_bus.clk,
710 .enable = s5pc100_d1_5_ctrl,
715 .parent = &clk_div_d1_bus.clk,
716 .enable = s5pc100_d1_5_ctrl,
721 .parent = &clk_div_d1_bus.clk,
722 .enable = s5pc100_d1_5_ctrl,
727 .parent = &clk_div_d1_bus.clk,
728 .enable = s5pc100_d1_5_ctrl,
733 .parent = &clk_mout_48m.clk,
734 .enable = s5pc100_sclk0_ctrl,
739 .parent = &clk_mout_48m.clk,
740 .enable = s5pc100_sclk0_ctrl,
745 .parent = &clk_mout_48m.clk,
746 .enable = s5pc100_sclk0_ctrl,
751 .parent = &clk_mout_48m.clk,
752 .enable = s5pc100_sclk0_ctrl,
753 .ctrlbit = (1 << 15),
757 .parent = &clk_mout_48m.clk,
758 .enable = s5pc100_sclk0_ctrl,
759 .ctrlbit = (1 << 16),
763 .parent = &clk_mout_48m.clk,
764 .enable = s5pc100_sclk0_ctrl,
765 .ctrlbit = (1 << 17),
769 static struct clk clk_vclk54m = {
775 static struct clk clk_i2scdclk0 = {
776 .name = "i2s_cdclk0",
780 static struct clk clk_i2scdclk1 = {
781 .name = "i2s_cdclk1",
785 static struct clk clk_i2scdclk2 = {
786 .name = "i2s_cdclk2",
790 static struct clk clk_pcmcdclk0 = {
791 .name = "pcm_cdclk0",
795 static struct clk clk_pcmcdclk1 = {
796 .name = "pcm_cdclk1",
800 static struct clk *clk_src_group1_list[] = {
801 [0] = &clk_mout_epll.clk,
802 [1] = &clk_div_mpll2.clk,
804 [3] = &clk_mout_hpll.clk,
807 struct clksrc_sources clk_src_group1 = {
808 .sources = clk_src_group1_list,
809 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
812 static struct clk *clk_src_group2_list[] = {
813 [0] = &clk_mout_epll.clk,
814 [1] = &clk_div_mpll.clk,
817 struct clksrc_sources clk_src_group2 = {
818 .sources = clk_src_group2_list,
819 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
822 static struct clk *clk_src_group3_list[] = {
823 [0] = &clk_mout_epll.clk,
824 [1] = &clk_div_mpll.clk,
826 [3] = &clk_i2scdclk0,
827 [4] = &clk_pcmcdclk0,
828 [5] = &clk_mout_hpll.clk,
831 struct clksrc_sources clk_src_group3 = {
832 .sources = clk_src_group3_list,
833 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
836 static struct clksrc_clk clk_sclk_audio0 = {
838 .name = "sclk_audio",
841 .enable = s5pc100_sclk1_ctrl,
843 .sources = &clk_src_group3,
844 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
845 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
848 static struct clk *clk_src_group4_list[] = {
849 [0] = &clk_mout_epll.clk,
850 [1] = &clk_div_mpll.clk,
852 [3] = &clk_i2scdclk1,
853 [4] = &clk_pcmcdclk1,
854 [5] = &clk_mout_hpll.clk,
857 struct clksrc_sources clk_src_group4 = {
858 .sources = clk_src_group4_list,
859 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
862 static struct clksrc_clk clk_sclk_audio1 = {
864 .name = "sclk_audio",
867 .enable = s5pc100_sclk1_ctrl,
869 .sources = &clk_src_group4,
870 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
871 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
874 static struct clk *clk_src_group5_list[] = {
875 [0] = &clk_mout_epll.clk,
876 [1] = &clk_div_mpll.clk,
878 [3] = &clk_i2scdclk2,
879 [4] = &clk_mout_hpll.clk,
882 struct clksrc_sources clk_src_group5 = {
883 .sources = clk_src_group5_list,
884 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
887 static struct clksrc_clk clk_sclk_audio2 = {
889 .name = "sclk_audio",
891 .ctrlbit = (1 << 10),
892 .enable = s5pc100_sclk1_ctrl,
894 .sources = &clk_src_group5,
895 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
896 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
899 static struct clk *clk_src_group6_list[] = {
902 [2] = &clk_div_hdmi.clk,
905 struct clksrc_sources clk_src_group6 = {
906 .sources = clk_src_group6_list,
907 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
910 static struct clk *clk_src_group7_list[] = {
911 [0] = &clk_mout_epll.clk,
912 [1] = &clk_div_mpll.clk,
913 [2] = &clk_mout_hpll.clk,
917 struct clksrc_sources clk_src_group7 = {
918 .sources = clk_src_group7_list,
919 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
922 static struct clk *clk_src_mmc0_list[] = {
923 [0] = &clk_mout_epll.clk,
924 [1] = &clk_div_mpll.clk,
928 struct clksrc_sources clk_src_mmc0 = {
929 .sources = clk_src_mmc0_list,
930 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
933 static struct clk *clk_src_mmc12_list[] = {
934 [0] = &clk_mout_epll.clk,
935 [1] = &clk_div_mpll.clk,
937 [3] = &clk_mout_hpll.clk,
940 struct clksrc_sources clk_src_mmc12 = {
941 .sources = clk_src_mmc12_list,
942 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
945 static struct clk *clk_src_irda_usb_list[] = {
946 [0] = &clk_mout_epll.clk,
947 [1] = &clk_div_mpll.clk,
949 [3] = &clk_mout_hpll.clk,
952 struct clksrc_sources clk_src_irda_usb = {
953 .sources = clk_src_irda_usb_list,
954 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
957 static struct clk *clk_src_pwi_list[] = {
959 [1] = &clk_mout_epll.clk,
960 [2] = &clk_div_mpll.clk,
963 struct clksrc_sources clk_src_pwi = {
964 .sources = clk_src_pwi_list,
965 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
968 static struct clk *clk_sclk_spdif_list[] = {
969 [0] = &clk_sclk_audio0.clk,
970 [1] = &clk_sclk_audio1.clk,
971 [2] = &clk_sclk_audio2.clk,
974 struct clksrc_sources clk_src_sclk_spdif = {
975 .sources = clk_sclk_spdif_list,
976 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
979 static int s5pc100_spdif_set_rate(struct clk *clk, unsigned long rate)
984 pclk = clk_get_parent(clk);
988 ret = pclk->ops->set_rate(pclk, rate);
994 static unsigned long s5pc100_spdif_get_rate(struct clk *clk)
999 pclk = clk_get_parent(clk);
1003 rate = pclk->ops->get_rate(clk);
1009 static struct clk_ops s5pc100_sclk_spdif_ops = {
1010 .set_rate = s5pc100_spdif_set_rate,
1011 .get_rate = s5pc100_spdif_get_rate,
1014 static struct clksrc_clk clk_sclk_spdif = {
1016 .name = "sclk_spdif",
1018 .ctrlbit = (1 << 11),
1019 .enable = s5pc100_sclk1_ctrl,
1020 .ops = &s5pc100_sclk_spdif_ops,
1022 .sources = &clk_src_sclk_spdif,
1023 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
1026 static struct clksrc_clk clksrcs[] = {
1031 .ctrlbit = (1 << 4),
1032 .enable = s5pc100_sclk0_ctrl,
1035 .sources = &clk_src_group1,
1036 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1037 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1042 .ctrlbit = (1 << 5),
1043 .enable = s5pc100_sclk0_ctrl,
1046 .sources = &clk_src_group1,
1047 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1048 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1053 .ctrlbit = (1 << 6),
1054 .enable = s5pc100_sclk0_ctrl,
1057 .sources = &clk_src_group1,
1058 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1059 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1064 .ctrlbit = (1 << 3),
1065 .enable = s5pc100_sclk0_ctrl,
1068 .sources = &clk_src_group2,
1069 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1070 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1073 .name = "sclk_mixer",
1075 .ctrlbit = (1 << 6),
1076 .enable = s5pc100_sclk0_ctrl,
1079 .sources = &clk_src_group6,
1080 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
1085 .ctrlbit = (1 << 0),
1086 .enable = s5pc100_sclk1_ctrl,
1089 .sources = &clk_src_group7,
1090 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
1091 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
1094 .name = "sclk_fimc",
1096 .ctrlbit = (1 << 1),
1097 .enable = s5pc100_sclk1_ctrl,
1100 .sources = &clk_src_group7,
1101 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
1102 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
1105 .name = "sclk_fimc",
1107 .ctrlbit = (1 << 2),
1108 .enable = s5pc100_sclk1_ctrl,
1111 .sources = &clk_src_group7,
1112 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1113 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1116 .name = "sclk_fimc",
1118 .ctrlbit = (1 << 3),
1119 .enable = s5pc100_sclk1_ctrl,
1122 .sources = &clk_src_group7,
1123 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1124 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1129 .ctrlbit = (1 << 12),
1130 .enable = s5pc100_sclk1_ctrl,
1133 .sources = &clk_src_mmc0,
1134 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1135 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1140 .ctrlbit = (1 << 13),
1141 .enable = s5pc100_sclk1_ctrl,
1144 .sources = &clk_src_mmc12,
1145 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1146 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1151 .ctrlbit = (1 << 14),
1152 .enable = s5pc100_sclk1_ctrl,
1155 .sources = &clk_src_mmc12,
1156 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1157 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1160 .name = "sclk_irda",
1162 .ctrlbit = (1 << 10),
1163 .enable = s5pc100_sclk0_ctrl,
1166 .sources = &clk_src_irda_usb,
1167 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1168 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1171 .name = "sclk_irda",
1173 .ctrlbit = (1 << 10),
1174 .enable = s5pc100_sclk0_ctrl,
1177 .sources = &clk_src_mmc12,
1178 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1179 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1184 .ctrlbit = (1 << 1),
1185 .enable = s5pc100_sclk0_ctrl,
1188 .sources = &clk_src_pwi,
1189 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1190 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1193 .name = "sclk_uhost",
1195 .ctrlbit = (1 << 11),
1196 .enable = s5pc100_sclk0_ctrl,
1199 .sources = &clk_src_irda_usb,
1200 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1201 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1205 /* Clock initialisation code */
1206 static struct clksrc_clk *sysclks[] = {
1234 void __init_or_cpufreq s5pc100_setup_clocks(void)
1238 unsigned long hclkd0;
1239 unsigned long hclkd1;
1240 unsigned long pclkd0;
1241 unsigned long pclkd1;
1248 /* Set S5PC100 functions for clk_fout_epll */
1249 clk_fout_epll.enable = s5p_epll_enable;
1250 clk_fout_epll.ops = &s5pc100_epll_ops;
1252 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1254 xtal = clk_get_rate(&clk_xtal);
1256 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1258 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1259 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1260 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1261 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1263 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1264 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1266 clk_fout_apll.rate = apll;
1267 clk_fout_mpll.rate = mpll;
1268 clk_fout_epll.rate = epll;
1269 clk_mout_hpll.clk.rate = hpll;
1271 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1272 s3c_set_clksrc(&clksrcs[ptr], true);
1274 arm = clk_get_rate(&clk_div_arm.clk);
1275 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1276 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1277 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1278 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1280 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1281 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1284 clk_h.rate = hclkd1;
1285 clk_p.rate = pclkd1;
1289 * The following clocks will be enabled during clock initialization.
1291 static struct clk init_clocks[] = {
1295 .parent = &clk_div_d0_bus.clk,
1296 .enable = s5pc100_d0_0_ctrl,
1297 .ctrlbit = (1 << 1),
1301 .parent = &clk_div_d0_bus.clk,
1302 .enable = s5pc100_d0_0_ctrl,
1303 .ctrlbit = (1 << 0),
1307 .parent = &clk_div_d0_bus.clk,
1308 .enable = s5pc100_d0_1_ctrl,
1309 .ctrlbit = (1 << 5),
1313 .parent = &clk_div_d0_bus.clk,
1314 .enable = s5pc100_d0_1_ctrl,
1315 .ctrlbit = (1 << 4),
1319 .parent = &clk_div_d0_bus.clk,
1320 .enable = s5pc100_d0_1_ctrl,
1321 .ctrlbit = (1 << 1),
1325 .parent = &clk_div_d0_bus.clk,
1326 .enable = s5pc100_d0_1_ctrl,
1327 .ctrlbit = (1 << 0),
1331 .parent = &clk_div_d0_bus.clk,
1332 .enable = s5pc100_d0_1_ctrl,
1333 .ctrlbit = (1 << 0),
1337 .parent = &clk_div_d1_bus.clk,
1338 .enable = s5pc100_d1_3_ctrl,
1339 .ctrlbit = (1 << 1),
1343 .parent = &clk_div_d1_bus.clk,
1344 .enable = s5pc100_d1_4_ctrl,
1345 .ctrlbit = (1 << 0),
1349 .parent = &clk_div_d1_bus.clk,
1350 .enable = s5pc100_d1_4_ctrl,
1351 .ctrlbit = (1 << 1),
1355 .parent = &clk_div_d1_bus.clk,
1356 .enable = s5pc100_d1_4_ctrl,
1357 .ctrlbit = (1 << 2),
1361 .parent = &clk_div_d1_bus.clk,
1362 .enable = s5pc100_d1_4_ctrl,
1363 .ctrlbit = (1 << 3),
1367 .parent = &clk_div_d1_bus.clk,
1368 .enable = s5pc100_d1_3_ctrl,
1369 .ctrlbit = (1 << 6),
1373 static struct clk *clks[] __initdata = {
1382 void __init s5pc100_register_clocks(void)
1388 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1390 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1391 s3c_register_clksrc(sysclks[ptr], 1);
1393 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1394 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1396 clkp = init_clocks_disable;
1397 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1399 ret = s3c24xx_register_clock(clkp);
1401 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1404 (clkp->enable)(clkp, 0);