arch/arm/mach-s5pc100/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Copyright 2009 Samsung Electronics Co.
   6  *      Byungho Min <bhmin@samsung.com>
   7  *
   8  * Common Codes for S5PC100
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/list.h>
  19 #include <linux/timer.h>
  20 #include <linux/init.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/device.h>
  24 #include <linux/serial_core.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/irq.h>
  29 #include <asm/proc-fns.h>
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33
  34 #include <mach/map.h>
  35 #include <mach/hardware.h>
  36 #include <mach/regs-clock.h>
  37
  38 #include <plat/cpu.h>
  39 #include <plat/devs.h>
  40 #include <plat/clock.h>
  41 #include <plat/sdhci.h>
  42 #include <plat/adc-core.h>
  43 #include <plat/ata-core.h>
  44 #include <plat/fb-core.h>
  45 #include <plat/iic-core.h>
  46 #include <plat/onenand-core.h>
  47 #include <plat/regs-serial.h>
  48 #include <plat/watchdog-reset.h>
  49
  50 #include "common.h"
  51
  52 static const char name_s5pc100[] = "S5PC100";
  53
  54 static struct cpu_table cpu_ids[] __initdata = {
  55         {
  56                 .idcode         = S5PC100_CPU_ID,
  57                 .idmask         = S5PC100_CPU_MASK,
  58                 .map_io         = s5pc100_map_io,
  59                 .init_clocks    = s5pc100_init_clocks,
  60                 .init_uarts     = s5pc100_init_uarts,
  61                 .init           = s5pc100_init,
  62                 .name           = name_s5pc100,
  63         },
  64 };
  65
  66 /* Initial IO mappings */
  67
  68 static struct map_desc s5pc100_iodesc[] __initdata = {
  69         {
  70                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  71                 .pfn            = __phys_to_pfn(S5PC100_PA_CHIPID),
  72                 .length         = SZ_4K,
  73                 .type           = MT_DEVICE,
  74         }, {
  75                 .virtual        = (unsigned long)S3C_VA_SYS,
  76                 .pfn            = __phys_to_pfn(S5PC100_PA_SYSCON),
  77                 .length         = SZ_64K,
  78                 .type           = MT_DEVICE,
  79         }, {
  80                 .virtual        = (unsigned long)S3C_VA_TIMER,
  81                 .pfn            = __phys_to_pfn(S5PC100_PA_TIMER),
  82                 .length         = SZ_16K,
  83                 .type           = MT_DEVICE,
  84         }, {
  85                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  86                 .pfn            = __phys_to_pfn(S5PC100_PA_WATCHDOG),
  87                 .length         = SZ_4K,
  88                 .type           = MT_DEVICE,
  89         }, {
  90                 .virtual        = (unsigned long)S5P_VA_SROMC,
  91                 .pfn            = __phys_to_pfn(S5PC100_PA_SROMC),
  92                 .length         = SZ_4K,
  93                 .type           = MT_DEVICE,
  94         }, {
  95                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  96                 .pfn            = __phys_to_pfn(S5PC100_PA_SYSTIMER),
  97                 .length         = SZ_16K,
  98                 .type           = MT_DEVICE,
  99         }, {
 100                 .virtual        = (unsigned long)S5P_VA_GPIO,
 101                 .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
 102                 .length         = SZ_4K,
 103                 .type           = MT_DEVICE,
 104         }, {
 105                 .virtual        = (unsigned long)VA_VIC0,
 106                 .pfn            = __phys_to_pfn(S5PC100_PA_VIC0),
 107                 .length         = SZ_16K,
 108                 .type           = MT_DEVICE,
 109         }, {
 110                 .virtual        = (unsigned long)VA_VIC1,
 111                 .pfn            = __phys_to_pfn(S5PC100_PA_VIC1),
 112                 .length         = SZ_16K,
 113                 .type           = MT_DEVICE,
 114         }, {
 115                 .virtual        = (unsigned long)VA_VIC2,
 116                 .pfn            = __phys_to_pfn(S5PC100_PA_VIC2),
 117                 .length         = SZ_16K,
 118                 .type           = MT_DEVICE,
 119         }, {
 120                 .virtual        = (unsigned long)S3C_VA_UART,
 121                 .pfn            = __phys_to_pfn(S3C_PA_UART),
 122                 .length         = SZ_512K,
 123                 .type           = MT_DEVICE,
 124         }, {
 125                 .virtual        = (unsigned long)S5PC100_VA_OTHERS,
 126                 .pfn            = __phys_to_pfn(S5PC100_PA_OTHERS),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE,
 129         }
 130 };
 131
 132 /*
 133  * s5pc100_map_io
 134  *
 135  * register the standard CPU IO areas
 136  */
 137
 138 void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
 139 {
 140         /* initialize the io descriptors we need for initialization */
 141         iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
 142         if (mach_desc)
 143                 iotable_init(mach_desc, size);
 144
 145         /* detect cpu id and rev. */
 146         s5p_init_cpu(S5P_VA_CHIPID);
 147
 148         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 149 }
 150
 151 void __init s5pc100_map_io(void)
 152 {
 153         /* initialise device information early */
 154         s5pc100_default_sdhci0();
 155         s5pc100_default_sdhci1();
 156         s5pc100_default_sdhci2();
 157
 158         s3c_adc_setname("s3c64xx-adc");
 159
 160         /* the i2c devices are directly compatible with s3c2440 */
 161         s3c_i2c0_setname("s3c2440-i2c");
 162         s3c_i2c1_setname("s3c2440-i2c");
 163
 164         s3c_onenand_setname("s5pc100-onenand");
 165         s3c_fb_setname("s5pc100-fb");
 166         s3c_cfcon_setname("s5pc100-pata");
 167 }
 168
 169 void __init s5pc100_init_clocks(int xtal)
 170 {
 171         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 172
 173         s3c24xx_register_baseclocks(xtal);
 174         s5p_register_clocks(xtal);
 175         s5pc100_register_clocks();
 176         s5pc100_setup_clocks();
 177 }
 178
 179 void __init s5pc100_init_irq(void)
 180 {
 181         u32 vic[] = {~0, ~0, ~0};
 182
 183         /* VIC0, VIC1, and VIC2 are fully populated. */
 184         s5p_init_irq(vic, ARRAY_SIZE(vic));
 185 }
 186
 187 static struct bus_type s5pc100_subsys = {
 188         .name           = "s5pc100-core",
 189         .dev_name       = "s5pc100-core",
 190 };
 191
 192 static struct device s5pc100_dev = {
 193         .bus    = &s5pc100_subsys,
 194 };
 195
 196 static int __init s5pc100_core_init(void)
 197 {
 198         return subsys_system_register(&s5pc100_subsys, NULL);
 199 }
 200 core_initcall(s5pc100_core_init);
 201
 202 int __init s5pc100_init(void)
 203 {
 204         printk(KERN_INFO "S5PC100: Initializing architecture\n");
 205         return device_register(&s5pc100_dev);
 206 }
 207
 208 /* uart registration process */
 209
 210 void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 211 {
 212         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 213 }
 214
 215 void s5pc100_restart(char mode, const char *cmd)
 216 {
 217         if (mode != 's')
 218                 arch_wdt_reset();
 219
 220         soft_restart(0);
 221 }