1 /* linux/arch/arm/mach-s5pv210/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PV210 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
25 #include <plat/cpu-freq.h>
26 #include <mach/regs-clock.h>
27 #include <plat/clock.h>
30 #include <plat/s5p-clock.h>
31 #include <plat/clock-clksrc.h>
32 #include <plat/s5pv210.h>
34 static struct clksrc_clk clk_mout_apll = {
39 .sources = &clk_src_apll,
40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43 static struct clksrc_clk clk_mout_epll = {
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
52 static struct clksrc_clk clk_mout_mpll = {
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
61 static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
66 static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
71 static struct clksrc_clk clk_armclk = {
76 .sources = &clkset_armclk,
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
81 static struct clksrc_clk clk_hclk_msys = {
85 .parent = &clk_armclk.clk,
87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
90 static struct clksrc_clk clk_pclk_msys = {
94 .parent = &clk_hclk_msys.clk,
96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
99 static struct clksrc_clk clk_sclk_a2m = {
103 .parent = &clk_mout_apll.clk,
105 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
108 static struct clk *clkset_hclk_sys_list[] = {
109 [0] = &clk_mout_mpll.clk,
110 [1] = &clk_sclk_a2m.clk,
113 static struct clksrc_sources clkset_hclk_sys = {
114 .sources = clkset_hclk_sys_list,
115 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
118 static struct clksrc_clk clk_hclk_dsys = {
123 .sources = &clkset_hclk_sys,
124 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
128 static struct clksrc_clk clk_pclk_dsys = {
132 .parent = &clk_hclk_dsys.clk,
134 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
137 static struct clksrc_clk clk_hclk_psys = {
142 .sources = &clkset_hclk_sys,
143 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
147 static struct clksrc_clk clk_pclk_psys = {
151 .parent = &clk_hclk_psys.clk,
153 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
156 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
158 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
161 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
163 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
166 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
168 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
171 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
173 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
176 static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
178 return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
181 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
183 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
186 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
188 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
191 static struct clk clk_sclk_hdmi27m = {
192 .name = "sclk_hdmi27m",
197 static struct clk clk_sclk_hdmiphy = {
198 .name = "sclk_hdmiphy",
202 static struct clk clk_sclk_usbphy0 = {
203 .name = "sclk_usbphy0",
207 static struct clk clk_sclk_usbphy1 = {
208 .name = "sclk_usbphy1",
212 static struct clk clk_pcmcdclk0 = {
217 static struct clk clk_pcmcdclk1 = {
222 static struct clk clk_pcmcdclk2 = {
227 static struct clk *clkset_vpllsrc_list[] = {
229 [1] = &clk_sclk_hdmi27m,
232 static struct clksrc_sources clkset_vpllsrc = {
233 .sources = clkset_vpllsrc_list,
234 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
237 static struct clksrc_clk clk_vpllsrc = {
241 .enable = s5pv210_clk_mask0_ctrl,
244 .sources = &clkset_vpllsrc,
245 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
248 static struct clk *clkset_sclk_vpll_list[] = {
249 [0] = &clk_vpllsrc.clk,
250 [1] = &clk_fout_vpll,
253 static struct clksrc_sources clkset_sclk_vpll = {
254 .sources = clkset_sclk_vpll_list,
255 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
258 static struct clksrc_clk clk_sclk_vpll = {
263 .sources = &clkset_sclk_vpll,
264 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
267 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
269 return clk_get_rate(clk->parent) / 2;
272 static struct clk_ops clk_hclk_imem_ops = {
273 .get_rate = s5pv210_clk_imem_get_rate,
276 static struct clk init_clocks_disable[] = {
280 .parent = &clk_hclk_dsys.clk,
281 .enable = s5pv210_clk_ip0_ctrl,
286 .parent = &clk_hclk_psys.clk,
287 .enable = s5pv210_clk_ip1_ctrl,
292 .parent = &clk_hclk_psys.clk,
293 .enable = s5pv210_clk_ip1_ctrl,
298 .parent = &clk_hclk_dsys.clk,
299 .enable = s5pv210_clk_ip1_ctrl,
304 .parent = &clk_hclk_psys.clk,
305 .enable = s5pv210_clk_ip1_ctrl,
310 .parent = &clk_hclk_psys.clk,
311 .enable = s5pv210_clk_ip2_ctrl,
316 .parent = &clk_hclk_psys.clk,
317 .enable = s5pv210_clk_ip2_ctrl,
322 .parent = &clk_hclk_psys.clk,
323 .enable = s5pv210_clk_ip2_ctrl,
328 .parent = &clk_hclk_psys.clk,
329 .enable = s5pv210_clk_ip2_ctrl,
334 .parent = &clk_pclk_psys.clk,
335 .enable = s5pv210_clk_ip3_ctrl,
340 .parent = &clk_pclk_psys.clk,
341 .enable = s5pv210_clk_ip3_ctrl,
346 .parent = &clk_pclk_psys.clk,
347 .enable = s5pv210_clk_ip3_ctrl,
352 .parent = &clk_pclk_psys.clk,
353 .enable = s5pv210_clk_ip3_ctrl,
358 .parent = &clk_pclk_psys.clk,
359 .enable = s5pv210_clk_ip3_ctrl,
364 .parent = &clk_pclk_psys.clk,
365 .enable = s5pv210_clk_ip3_ctrl,
370 .parent = &clk_pclk_psys.clk,
371 .enable = s5pv210_clk_ip3_ctrl,
376 .parent = &clk_pclk_psys.clk,
377 .enable = s5pv210_clk_ip3_ctrl,
382 .parent = &clk_pclk_psys.clk,
383 .enable = s5pv210_clk_ip3_ctrl,
388 .parent = &clk_pclk_psys.clk,
389 .enable = s5pv210_clk_ip3_ctrl,
394 .parent = &clk_pclk_psys.clk,
395 .enable = s5pv210_clk_ip3_ctrl,
400 .parent = &clk_pclk_psys.clk,
401 .enable = s5pv210_clk_ip3_ctrl,
407 .enable = s5pv210_clk_ip3_ctrl,
413 .enable = s5pv210_clk_ip3_ctrl,
419 .enable = s5pv210_clk_ip3_ctrl,
424 static struct clk init_clocks[] = {
428 .parent = &clk_hclk_msys.clk,
430 .enable = s5pv210_clk_ip0_ctrl,
431 .ops = &clk_hclk_imem_ops,
435 .parent = &clk_pclk_psys.clk,
436 .enable = s5pv210_clk_ip3_ctrl,
437 .ctrlbit = (1 << 17),
441 .parent = &clk_pclk_psys.clk,
442 .enable = s5pv210_clk_ip3_ctrl,
443 .ctrlbit = (1 << 18),
447 .parent = &clk_pclk_psys.clk,
448 .enable = s5pv210_clk_ip3_ctrl,
449 .ctrlbit = (1 << 19),
453 .parent = &clk_pclk_psys.clk,
454 .enable = s5pv210_clk_ip3_ctrl,
455 .ctrlbit = (1 << 20),
459 static struct clk *clkset_uart_list[] = {
460 [6] = &clk_mout_mpll.clk,
461 [7] = &clk_mout_epll.clk,
464 static struct clksrc_sources clkset_uart = {
465 .sources = clkset_uart_list,
466 .nr_sources = ARRAY_SIZE(clkset_uart_list),
469 static struct clk *clkset_group1_list[] = {
470 [0] = &clk_sclk_a2m.clk,
471 [1] = &clk_mout_mpll.clk,
472 [2] = &clk_mout_epll.clk,
473 [3] = &clk_sclk_vpll.clk,
476 static struct clksrc_sources clkset_group1 = {
477 .sources = clkset_group1_list,
478 .nr_sources = ARRAY_SIZE(clkset_group1_list),
481 static struct clk *clkset_sclk_onenand_list[] = {
482 [0] = &clk_hclk_psys.clk,
483 [1] = &clk_hclk_dsys.clk,
486 static struct clksrc_sources clkset_sclk_onenand = {
487 .sources = clkset_sclk_onenand_list,
488 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
491 static struct clk *clkset_sclk_dac_list[] = {
492 [0] = &clk_sclk_vpll.clk,
493 [1] = &clk_sclk_hdmiphy,
496 static struct clksrc_sources clkset_sclk_dac = {
497 .sources = clkset_sclk_dac_list,
498 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
501 static struct clksrc_clk clk_sclk_dac = {
505 .enable = s5pv210_clk_mask0_ctrl,
508 .sources = &clkset_sclk_dac,
509 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
512 static struct clksrc_clk clk_sclk_pixel = {
514 .name = "sclk_pixel",
516 .parent = &clk_sclk_vpll.clk,
518 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
521 static struct clk *clkset_sclk_hdmi_list[] = {
522 [0] = &clk_sclk_pixel.clk,
523 [1] = &clk_sclk_hdmiphy,
526 static struct clksrc_sources clkset_sclk_hdmi = {
527 .sources = clkset_sclk_hdmi_list,
528 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
531 static struct clksrc_clk clk_sclk_hdmi = {
535 .enable = s5pv210_clk_mask0_ctrl,
538 .sources = &clkset_sclk_hdmi,
539 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
542 static struct clk *clkset_sclk_mixer_list[] = {
543 [0] = &clk_sclk_dac.clk,
544 [1] = &clk_sclk_hdmi.clk,
547 static struct clksrc_sources clkset_sclk_mixer = {
548 .sources = clkset_sclk_mixer_list,
549 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
552 static struct clk *clkset_sclk_audio0_list[] = {
553 [0] = &clk_ext_xtal_mux,
554 [1] = &clk_pcmcdclk0,
555 [2] = &clk_sclk_hdmi27m,
556 [3] = &clk_sclk_usbphy0,
557 [4] = &clk_sclk_usbphy1,
558 [5] = &clk_sclk_hdmiphy,
559 [6] = &clk_mout_mpll.clk,
560 [7] = &clk_mout_epll.clk,
561 [8] = &clk_sclk_vpll.clk,
564 static struct clksrc_sources clkset_sclk_audio0 = {
565 .sources = clkset_sclk_audio0_list,
566 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
569 static struct clksrc_clk clk_sclk_audio0 = {
571 .name = "sclk_audio",
573 .enable = s5pv210_clk_mask0_ctrl,
574 .ctrlbit = (1 << 24),
576 .sources = &clkset_sclk_audio0,
577 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
578 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
581 static struct clk *clkset_sclk_audio1_list[] = {
582 [0] = &clk_ext_xtal_mux,
583 [1] = &clk_pcmcdclk1,
584 [2] = &clk_sclk_hdmi27m,
585 [3] = &clk_sclk_usbphy0,
586 [4] = &clk_sclk_usbphy1,
587 [5] = &clk_sclk_hdmiphy,
588 [6] = &clk_mout_mpll.clk,
589 [7] = &clk_mout_epll.clk,
590 [8] = &clk_sclk_vpll.clk,
593 static struct clksrc_sources clkset_sclk_audio1 = {
594 .sources = clkset_sclk_audio1_list,
595 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
598 static struct clksrc_clk clk_sclk_audio1 = {
600 .name = "sclk_audio",
602 .enable = s5pv210_clk_mask0_ctrl,
603 .ctrlbit = (1 << 25),
605 .sources = &clkset_sclk_audio1,
606 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
607 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
610 static struct clk *clkset_sclk_audio2_list[] = {
611 [0] = &clk_ext_xtal_mux,
612 [1] = &clk_pcmcdclk0,
613 [2] = &clk_sclk_hdmi27m,
614 [3] = &clk_sclk_usbphy0,
615 [4] = &clk_sclk_usbphy1,
616 [5] = &clk_sclk_hdmiphy,
617 [6] = &clk_mout_mpll.clk,
618 [7] = &clk_mout_epll.clk,
619 [8] = &clk_sclk_vpll.clk,
622 static struct clksrc_sources clkset_sclk_audio2 = {
623 .sources = clkset_sclk_audio2_list,
624 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
627 static struct clksrc_clk clk_sclk_audio2 = {
629 .name = "sclk_audio",
631 .enable = s5pv210_clk_mask0_ctrl,
632 .ctrlbit = (1 << 26),
634 .sources = &clkset_sclk_audio2,
635 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
636 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
639 static struct clk *clkset_sclk_spdif_list[] = {
640 [0] = &clk_sclk_audio0.clk,
641 [1] = &clk_sclk_audio1.clk,
642 [2] = &clk_sclk_audio2.clk,
645 static struct clksrc_sources clkset_sclk_spdif = {
646 .sources = clkset_sclk_spdif_list,
647 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
650 static struct clk *clkset_group2_list[] = {
651 [0] = &clk_ext_xtal_mux,
653 [2] = &clk_sclk_hdmi27m,
654 [3] = &clk_sclk_usbphy0,
655 [4] = &clk_sclk_usbphy1,
656 [5] = &clk_sclk_hdmiphy,
657 [6] = &clk_mout_mpll.clk,
658 [7] = &clk_mout_epll.clk,
659 [8] = &clk_sclk_vpll.clk,
662 static struct clksrc_sources clkset_group2 = {
663 .sources = clkset_group2_list,
664 .nr_sources = ARRAY_SIZE(clkset_group2_list),
667 static struct clksrc_clk clksrcs[] = {
673 .sources = &clkset_group1,
674 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
675 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
678 .name = "sclk_onenand",
681 .sources = &clkset_sclk_onenand,
682 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
683 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
688 .enable = s5pv210_clk_mask0_ctrl,
689 .ctrlbit = (1 << 12),
691 .sources = &clkset_uart,
692 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
693 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
698 .enable = s5pv210_clk_mask0_ctrl,
699 .ctrlbit = (1 << 13),
701 .sources = &clkset_uart,
702 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
703 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
708 .enable = s5pv210_clk_mask0_ctrl,
709 .ctrlbit = (1 << 14),
711 .sources = &clkset_uart,
712 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
713 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
718 .enable = s5pv210_clk_mask0_ctrl,
719 .ctrlbit = (1 << 15),
721 .sources = &clkset_uart,
722 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
723 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
726 .name = "sclk_mixer",
728 .enable = s5pv210_clk_mask0_ctrl,
731 .sources = &clkset_sclk_mixer,
732 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
735 .name = "sclk_spdif",
737 .enable = s5pv210_clk_mask0_ctrl,
738 .ctrlbit = (1 << 27),
740 .sources = &clkset_sclk_spdif,
741 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
746 .enable = s5pv210_clk_mask1_ctrl,
749 .sources = &clkset_group2,
750 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
751 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
756 .enable = s5pv210_clk_mask1_ctrl,
759 .sources = &clkset_group2,
760 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
761 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
766 .enable = s5pv210_clk_mask1_ctrl,
769 .sources = &clkset_group2,
770 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
771 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
776 .enable = s5pv210_clk_mask0_ctrl,
779 .sources = &clkset_group2,
780 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
781 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
786 .enable = s5pv210_clk_mask0_ctrl,
789 .sources = &clkset_group2,
790 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
791 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
796 .enable = s5pv210_clk_mask0_ctrl,
799 .sources = &clkset_group2,
800 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
801 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
806 .enable = s5pv210_clk_mask0_ctrl,
809 .sources = &clkset_group2,
810 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
811 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
816 .enable = s5pv210_clk_mask0_ctrl,
819 .sources = &clkset_group2,
820 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
821 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
826 .enable = s5pv210_clk_mask0_ctrl,
827 .ctrlbit = (1 << 10),
829 .sources = &clkset_group2,
830 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
831 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
836 .enable = s5pv210_clk_mask0_ctrl,
837 .ctrlbit = (1 << 11),
839 .sources = &clkset_group2,
840 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
841 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
846 .enable = s5pv210_clk_ip0_ctrl,
847 .ctrlbit = (1 << 16),
849 .sources = &clkset_group1,
850 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
851 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
856 .enable = s5pv210_clk_ip0_ctrl,
857 .ctrlbit = (1 << 12),
859 .sources = &clkset_group1,
860 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
861 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
866 .enable = s5pv210_clk_ip0_ctrl,
869 .sources = &clkset_group1,
870 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
871 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
876 .enable = s5pv210_clk_mask0_ctrl,
879 .sources = &clkset_group2,
880 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
881 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
886 .enable = s5pv210_clk_mask0_ctrl,
887 .ctrlbit = (1 << 16),
889 .sources = &clkset_group2,
890 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
891 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
896 .enable = s5pv210_clk_mask0_ctrl,
897 .ctrlbit = (1 << 17),
899 .sources = &clkset_group2,
900 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
901 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
906 .enable = s5pv210_clk_mask0_ctrl,
907 .ctrlbit = (1 << 29),
909 .sources = &clkset_group2,
910 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
911 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
916 .enable = s5pv210_clk_mask0_ctrl,
917 .ctrlbit = (1 << 19),
919 .sources = &clkset_group2,
920 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
921 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
925 /* Clock initialisation code */
926 static struct clksrc_clk *sysclks[] = {
945 void __init_or_cpufreq s5pv210_setup_clocks(void)
947 struct clk *xtal_clk;
949 unsigned long vpllsrc;
950 unsigned long armclk;
951 unsigned long hclk_msys;
952 unsigned long hclk_dsys;
953 unsigned long hclk_psys;
954 unsigned long pclk_msys;
955 unsigned long pclk_dsys;
956 unsigned long pclk_psys;
962 u32 clkdiv0, clkdiv1;
964 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
966 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
967 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
969 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
970 __func__, clkdiv0, clkdiv1);
972 xtal_clk = clk_get(NULL, "xtal");
973 BUG_ON(IS_ERR(xtal_clk));
975 xtal = clk_get_rate(xtal_clk);
978 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
980 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
981 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
982 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
983 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
984 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
986 clk_fout_apll.rate = apll;
987 clk_fout_mpll.rate = mpll;
988 clk_fout_epll.rate = epll;
989 clk_fout_vpll.rate = vpll;
991 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
992 apll, mpll, epll, vpll);
994 armclk = clk_get_rate(&clk_armclk.clk);
995 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
996 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
997 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
998 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
999 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1000 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1002 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1003 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1004 armclk, hclk_msys, hclk_dsys, hclk_psys,
1005 pclk_msys, pclk_dsys, pclk_psys);
1007 clk_f.rate = armclk;
1008 clk_h.rate = hclk_psys;
1009 clk_p.rate = pclk_psys;
1011 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1012 s3c_set_clksrc(&clksrcs[ptr], true);
1015 static struct clk *clks[] __initdata = {
1025 void __init s5pv210_register_clocks(void)
1031 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1033 printk(KERN_ERR "Failed to register %u clocks\n", ret);
1035 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1036 s3c_register_clksrc(sysclks[ptr], 1);
1038 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1039 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1041 clkp = init_clocks_disable;
1042 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1043 ret = s3c24xx_register_clock(clkp);
1045 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1048 (clkp->enable)(clkp, 0);