1 /* linux/arch/arm/mach-s5pv210/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PV210 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
25 #include <plat/cpu-freq.h>
26 #include <mach/regs-clock.h>
27 #include <plat/clock.h>
30 #include <plat/s5p-clock.h>
31 #include <plat/clock-clksrc.h>
32 #include <plat/s5pv210.h>
34 static struct clksrc_clk clk_mout_apll = {
39 .sources = &clk_src_apll,
40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43 static struct clksrc_clk clk_mout_epll = {
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
52 static struct clksrc_clk clk_mout_mpll = {
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
61 static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
66 static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
71 static struct clksrc_clk clk_armclk = {
76 .sources = &clkset_armclk,
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
81 static struct clksrc_clk clk_hclk_msys = {
85 .parent = &clk_armclk.clk,
87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
90 static struct clksrc_clk clk_pclk_msys = {
94 .parent = &clk_hclk_msys.clk,
96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
99 static struct clksrc_clk clk_sclk_a2m = {
103 .parent = &clk_mout_apll.clk,
105 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
108 static struct clk *clkset_hclk_sys_list[] = {
109 [0] = &clk_mout_mpll.clk,
110 [1] = &clk_sclk_a2m.clk,
113 static struct clksrc_sources clkset_hclk_sys = {
114 .sources = clkset_hclk_sys_list,
115 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
118 static struct clksrc_clk clk_hclk_dsys = {
123 .sources = &clkset_hclk_sys,
124 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
128 static struct clksrc_clk clk_pclk_dsys = {
132 .parent = &clk_hclk_dsys.clk,
134 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
137 static struct clksrc_clk clk_hclk_psys = {
142 .sources = &clkset_hclk_sys,
143 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
147 static struct clksrc_clk clk_pclk_psys = {
151 .parent = &clk_hclk_psys.clk,
153 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
156 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
158 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
161 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
163 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
166 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
168 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
171 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
173 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
176 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
178 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
181 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
183 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
186 static struct clk clk_sclk_hdmi27m = {
187 .name = "sclk_hdmi27m",
192 static struct clk clk_sclk_hdmiphy = {
193 .name = "sclk_hdmiphy",
197 static struct clk clk_sclk_usbphy0 = {
198 .name = "sclk_usbphy0",
202 static struct clk clk_sclk_usbphy1 = {
203 .name = "sclk_usbphy1",
207 static struct clk clk_pcmcdclk0 = {
212 static struct clk clk_pcmcdclk1 = {
217 static struct clk clk_pcmcdclk2 = {
222 static struct clk *clkset_vpllsrc_list[] = {
224 [1] = &clk_sclk_hdmi27m,
227 static struct clksrc_sources clkset_vpllsrc = {
228 .sources = clkset_vpllsrc_list,
229 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
232 static struct clksrc_clk clk_vpllsrc = {
236 .enable = s5pv210_clk_mask0_ctrl,
239 .sources = &clkset_vpllsrc,
240 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
243 static struct clk *clkset_sclk_vpll_list[] = {
244 [0] = &clk_vpllsrc.clk,
245 [1] = &clk_fout_vpll,
248 static struct clksrc_sources clkset_sclk_vpll = {
249 .sources = clkset_sclk_vpll_list,
250 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
253 static struct clksrc_clk clk_sclk_vpll = {
258 .sources = &clkset_sclk_vpll,
259 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
262 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
264 return clk_get_rate(clk->parent) / 2;
267 static struct clk_ops clk_hclk_imem_ops = {
268 .get_rate = s5pv210_clk_imem_get_rate,
271 static struct clk init_clocks_disable[] = {
275 .parent = &clk_hclk_dsys.clk,
276 .enable = s5pv210_clk_ip0_ctrl,
281 .parent = &clk_hclk_dsys.clk,
282 .enable = s5pv210_clk_ip0_ctrl,
283 .ctrlbit = (1 << 24),
287 .parent = &clk_hclk_dsys.clk,
288 .enable = s5pv210_clk_ip0_ctrl,
289 .ctrlbit = (1 << 25),
293 .parent = &clk_hclk_dsys.clk,
294 .enable = s5pv210_clk_ip0_ctrl,
295 .ctrlbit = (1 << 26),
299 .parent = &clk_hclk_psys.clk,
300 .enable = s5pv210_clk_ip1_ctrl,
305 .parent = &clk_hclk_psys.clk,
306 .enable = s5pv210_clk_ip1_ctrl,
311 .parent = &clk_hclk_dsys.clk,
312 .enable = s5pv210_clk_ip1_ctrl,
317 .parent = &clk_hclk_psys.clk,
318 .enable = s5pv210_clk_ip1_ctrl,
323 .parent = &clk_hclk_psys.clk,
324 .enable = s5pv210_clk_ip2_ctrl,
329 .parent = &clk_hclk_psys.clk,
330 .enable = s5pv210_clk_ip2_ctrl,
335 .parent = &clk_hclk_psys.clk,
336 .enable = s5pv210_clk_ip2_ctrl,
341 .parent = &clk_hclk_psys.clk,
342 .enable = s5pv210_clk_ip2_ctrl,
347 .parent = &clk_pclk_psys.clk,
348 .enable = s5pv210_clk_ip3_ctrl,
353 .parent = &clk_pclk_psys.clk,
354 .enable = s5pv210_clk_ip3_ctrl,
359 .parent = &clk_pclk_psys.clk,
360 .enable = s5pv210_clk_ip3_ctrl,
365 .parent = &clk_pclk_psys.clk,
366 .enable = s5pv210_clk_ip3_ctrl,
371 .parent = &clk_pclk_psys.clk,
372 .enable = s5pv210_clk_ip3_ctrl,
373 .ctrlbit = (1 << 10),
377 .parent = &clk_pclk_psys.clk,
378 .enable = s5pv210_clk_ip3_ctrl,
383 .parent = &clk_pclk_psys.clk,
384 .enable = s5pv210_clk_ip3_ctrl,
389 .parent = &clk_pclk_psys.clk,
390 .enable = s5pv210_clk_ip3_ctrl,
395 .parent = &clk_pclk_psys.clk,
396 .enable = s5pv210_clk_ip3_ctrl,
401 .parent = &clk_pclk_psys.clk,
402 .enable = s5pv210_clk_ip3_ctrl,
407 .parent = &clk_pclk_psys.clk,
408 .enable = s5pv210_clk_ip3_ctrl,
413 .parent = &clk_pclk_psys.clk,
414 .enable = s5pv210_clk_ip3_ctrl,
420 .enable = s5pv210_clk_ip3_ctrl,
426 .enable = s5pv210_clk_ip3_ctrl,
432 .enable = s5pv210_clk_ip3_ctrl,
437 static struct clk init_clocks[] = {
441 .parent = &clk_hclk_msys.clk,
443 .enable = s5pv210_clk_ip0_ctrl,
444 .ops = &clk_hclk_imem_ops,
448 .parent = &clk_pclk_psys.clk,
449 .enable = s5pv210_clk_ip3_ctrl,
450 .ctrlbit = (1 << 17),
454 .parent = &clk_pclk_psys.clk,
455 .enable = s5pv210_clk_ip3_ctrl,
456 .ctrlbit = (1 << 18),
460 .parent = &clk_pclk_psys.clk,
461 .enable = s5pv210_clk_ip3_ctrl,
462 .ctrlbit = (1 << 19),
466 .parent = &clk_pclk_psys.clk,
467 .enable = s5pv210_clk_ip3_ctrl,
468 .ctrlbit = (1 << 20),
472 static struct clk *clkset_uart_list[] = {
473 [6] = &clk_mout_mpll.clk,
474 [7] = &clk_mout_epll.clk,
477 static struct clksrc_sources clkset_uart = {
478 .sources = clkset_uart_list,
479 .nr_sources = ARRAY_SIZE(clkset_uart_list),
482 static struct clk *clkset_group1_list[] = {
483 [0] = &clk_sclk_a2m.clk,
484 [1] = &clk_mout_mpll.clk,
485 [2] = &clk_mout_epll.clk,
486 [3] = &clk_sclk_vpll.clk,
489 static struct clksrc_sources clkset_group1 = {
490 .sources = clkset_group1_list,
491 .nr_sources = ARRAY_SIZE(clkset_group1_list),
494 static struct clk *clkset_sclk_onenand_list[] = {
495 [0] = &clk_hclk_psys.clk,
496 [1] = &clk_hclk_dsys.clk,
499 static struct clksrc_sources clkset_sclk_onenand = {
500 .sources = clkset_sclk_onenand_list,
501 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
504 static struct clk *clkset_sclk_dac_list[] = {
505 [0] = &clk_sclk_vpll.clk,
506 [1] = &clk_sclk_hdmiphy,
509 static struct clksrc_sources clkset_sclk_dac = {
510 .sources = clkset_sclk_dac_list,
511 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
514 static struct clksrc_clk clk_sclk_dac = {
518 .enable = s5pv210_clk_mask0_ctrl,
521 .sources = &clkset_sclk_dac,
522 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
525 static struct clksrc_clk clk_sclk_pixel = {
527 .name = "sclk_pixel",
529 .parent = &clk_sclk_vpll.clk,
531 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
534 static struct clk *clkset_sclk_hdmi_list[] = {
535 [0] = &clk_sclk_pixel.clk,
536 [1] = &clk_sclk_hdmiphy,
539 static struct clksrc_sources clkset_sclk_hdmi = {
540 .sources = clkset_sclk_hdmi_list,
541 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
544 static struct clksrc_clk clk_sclk_hdmi = {
548 .enable = s5pv210_clk_mask0_ctrl,
551 .sources = &clkset_sclk_hdmi,
552 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
555 static struct clk *clkset_sclk_mixer_list[] = {
556 [0] = &clk_sclk_dac.clk,
557 [1] = &clk_sclk_hdmi.clk,
560 static struct clksrc_sources clkset_sclk_mixer = {
561 .sources = clkset_sclk_mixer_list,
562 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
565 static struct clk *clkset_sclk_audio0_list[] = {
566 [0] = &clk_ext_xtal_mux,
567 [1] = &clk_pcmcdclk0,
568 [2] = &clk_sclk_hdmi27m,
569 [3] = &clk_sclk_usbphy0,
570 [4] = &clk_sclk_usbphy1,
571 [5] = &clk_sclk_hdmiphy,
572 [6] = &clk_mout_mpll.clk,
573 [7] = &clk_mout_epll.clk,
574 [8] = &clk_sclk_vpll.clk,
577 static struct clksrc_sources clkset_sclk_audio0 = {
578 .sources = clkset_sclk_audio0_list,
579 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
582 static struct clksrc_clk clk_sclk_audio0 = {
584 .name = "sclk_audio",
586 .enable = s5pv210_clk_mask0_ctrl,
587 .ctrlbit = (1 << 24),
589 .sources = &clkset_sclk_audio0,
590 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
591 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
594 static struct clk *clkset_sclk_audio1_list[] = {
595 [0] = &clk_ext_xtal_mux,
596 [1] = &clk_pcmcdclk1,
597 [2] = &clk_sclk_hdmi27m,
598 [3] = &clk_sclk_usbphy0,
599 [4] = &clk_sclk_usbphy1,
600 [5] = &clk_sclk_hdmiphy,
601 [6] = &clk_mout_mpll.clk,
602 [7] = &clk_mout_epll.clk,
603 [8] = &clk_sclk_vpll.clk,
606 static struct clksrc_sources clkset_sclk_audio1 = {
607 .sources = clkset_sclk_audio1_list,
608 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
611 static struct clksrc_clk clk_sclk_audio1 = {
613 .name = "sclk_audio",
615 .enable = s5pv210_clk_mask0_ctrl,
616 .ctrlbit = (1 << 25),
618 .sources = &clkset_sclk_audio1,
619 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
620 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
623 static struct clk *clkset_sclk_audio2_list[] = {
624 [0] = &clk_ext_xtal_mux,
625 [1] = &clk_pcmcdclk0,
626 [2] = &clk_sclk_hdmi27m,
627 [3] = &clk_sclk_usbphy0,
628 [4] = &clk_sclk_usbphy1,
629 [5] = &clk_sclk_hdmiphy,
630 [6] = &clk_mout_mpll.clk,
631 [7] = &clk_mout_epll.clk,
632 [8] = &clk_sclk_vpll.clk,
635 static struct clksrc_sources clkset_sclk_audio2 = {
636 .sources = clkset_sclk_audio2_list,
637 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
640 static struct clksrc_clk clk_sclk_audio2 = {
642 .name = "sclk_audio",
644 .enable = s5pv210_clk_mask0_ctrl,
645 .ctrlbit = (1 << 26),
647 .sources = &clkset_sclk_audio2,
648 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
649 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
652 static struct clk *clkset_sclk_spdif_list[] = {
653 [0] = &clk_sclk_audio0.clk,
654 [1] = &clk_sclk_audio1.clk,
655 [2] = &clk_sclk_audio2.clk,
658 static struct clksrc_sources clkset_sclk_spdif = {
659 .sources = clkset_sclk_spdif_list,
660 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
663 static struct clk *clkset_group2_list[] = {
664 [0] = &clk_ext_xtal_mux,
666 [2] = &clk_sclk_hdmi27m,
667 [3] = &clk_sclk_usbphy0,
668 [4] = &clk_sclk_usbphy1,
669 [5] = &clk_sclk_hdmiphy,
670 [6] = &clk_mout_mpll.clk,
671 [7] = &clk_mout_epll.clk,
672 [8] = &clk_sclk_vpll.clk,
675 static struct clksrc_sources clkset_group2 = {
676 .sources = clkset_group2_list,
677 .nr_sources = ARRAY_SIZE(clkset_group2_list),
680 static struct clksrc_clk clksrcs[] = {
686 .sources = &clkset_group1,
687 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
688 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
691 .name = "sclk_onenand",
694 .sources = &clkset_sclk_onenand,
695 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
696 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
701 .enable = s5pv210_clk_mask0_ctrl,
702 .ctrlbit = (1 << 12),
704 .sources = &clkset_uart,
705 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
706 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
711 .enable = s5pv210_clk_mask0_ctrl,
712 .ctrlbit = (1 << 13),
714 .sources = &clkset_uart,
715 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
716 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
721 .enable = s5pv210_clk_mask0_ctrl,
722 .ctrlbit = (1 << 14),
724 .sources = &clkset_uart,
725 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
726 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
731 .enable = s5pv210_clk_mask0_ctrl,
732 .ctrlbit = (1 << 15),
734 .sources = &clkset_uart,
735 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
736 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
739 .name = "sclk_mixer",
741 .enable = s5pv210_clk_mask0_ctrl,
744 .sources = &clkset_sclk_mixer,
745 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
748 .name = "sclk_spdif",
750 .enable = s5pv210_clk_mask0_ctrl,
751 .ctrlbit = (1 << 27),
753 .sources = &clkset_sclk_spdif,
754 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
759 .enable = s5pv210_clk_mask1_ctrl,
762 .sources = &clkset_group2,
763 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
764 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
769 .enable = s5pv210_clk_mask1_ctrl,
772 .sources = &clkset_group2,
773 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
774 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
779 .enable = s5pv210_clk_mask1_ctrl,
782 .sources = &clkset_group2,
783 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
784 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
789 .enable = s5pv210_clk_mask0_ctrl,
792 .sources = &clkset_group2,
793 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
794 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
799 .enable = s5pv210_clk_mask0_ctrl,
802 .sources = &clkset_group2,
803 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
804 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
809 .enable = s5pv210_clk_mask0_ctrl,
812 .sources = &clkset_group2,
813 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
814 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
819 .enable = s5pv210_clk_mask0_ctrl,
822 .sources = &clkset_group2,
823 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
824 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
829 .enable = s5pv210_clk_mask0_ctrl,
832 .sources = &clkset_group2,
833 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
834 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
839 .enable = s5pv210_clk_mask0_ctrl,
840 .ctrlbit = (1 << 10),
842 .sources = &clkset_group2,
843 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
844 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
849 .enable = s5pv210_clk_mask0_ctrl,
850 .ctrlbit = (1 << 11),
852 .sources = &clkset_group2,
853 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
854 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
859 .enable = s5pv210_clk_ip0_ctrl,
860 .ctrlbit = (1 << 16),
862 .sources = &clkset_group1,
863 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
864 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
869 .enable = s5pv210_clk_ip0_ctrl,
870 .ctrlbit = (1 << 12),
872 .sources = &clkset_group1,
873 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
874 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
879 .enable = s5pv210_clk_ip0_ctrl,
882 .sources = &clkset_group1,
883 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
884 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
889 .enable = s5pv210_clk_mask0_ctrl,
892 .sources = &clkset_group2,
893 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
894 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
899 .enable = s5pv210_clk_mask0_ctrl,
900 .ctrlbit = (1 << 16),
902 .sources = &clkset_group2,
903 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
904 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
909 .enable = s5pv210_clk_mask0_ctrl,
910 .ctrlbit = (1 << 17),
912 .sources = &clkset_group2,
913 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
914 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
919 .enable = s5pv210_clk_mask0_ctrl,
920 .ctrlbit = (1 << 29),
922 .sources = &clkset_group2,
923 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
924 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
929 .enable = s5pv210_clk_mask0_ctrl,
930 .ctrlbit = (1 << 19),
932 .sources = &clkset_group2,
933 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
934 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
938 /* Clock initialisation code */
939 static struct clksrc_clk *sysclks[] = {
958 void __init_or_cpufreq s5pv210_setup_clocks(void)
960 struct clk *xtal_clk;
962 unsigned long vpllsrc;
963 unsigned long armclk;
964 unsigned long hclk_msys;
965 unsigned long hclk_dsys;
966 unsigned long hclk_psys;
967 unsigned long pclk_msys;
968 unsigned long pclk_dsys;
969 unsigned long pclk_psys;
975 u32 clkdiv0, clkdiv1;
977 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
979 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
980 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
982 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
983 __func__, clkdiv0, clkdiv1);
985 xtal_clk = clk_get(NULL, "xtal");
986 BUG_ON(IS_ERR(xtal_clk));
988 xtal = clk_get_rate(xtal_clk);
991 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
993 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
994 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
995 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
996 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
997 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
999 clk_fout_apll.rate = apll;
1000 clk_fout_mpll.rate = mpll;
1001 clk_fout_epll.rate = epll;
1002 clk_fout_vpll.rate = vpll;
1004 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1005 apll, mpll, epll, vpll);
1007 armclk = clk_get_rate(&clk_armclk.clk);
1008 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1009 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1010 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1011 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1012 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1013 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1015 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1016 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1017 armclk, hclk_msys, hclk_dsys, hclk_psys,
1018 pclk_msys, pclk_dsys, pclk_psys);
1020 clk_f.rate = armclk;
1021 clk_h.rate = hclk_psys;
1022 clk_p.rate = pclk_psys;
1024 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1025 s3c_set_clksrc(&clksrcs[ptr], true);
1028 static struct clk *clks[] __initdata = {
1038 void __init s5pv210_register_clocks(void)
1044 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1046 printk(KERN_ERR "Failed to register %u clocks\n", ret);
1048 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1049 s3c_register_clksrc(sysclks[ptr], 1);
1051 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1052 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1054 clkp = init_clocks_disable;
1055 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1056 ret = s3c24xx_register_clock(clkp);
1058 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1061 (clkp->enable)(clkp, 0);