2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundationr
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/err.h>
14 #include <linux/platform_device.h>
19 #include <plat/regs-usb-hsotg-phy.h>
20 #include <plat/usb-phy.h>
22 #define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C)
23 #define S5PV210_USB_PHY0_EN (1 << 0)
24 #define S5PV210_USB_PHY1_EN (1 << 1)
26 static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
31 writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN,
34 /* set clock frequency for PLL */
35 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
37 xusbxti = clk_get(&pdev->dev, "xusbxti");
38 if (xusbxti && !IS_ERR(xusbxti)) {
39 switch (clk_get_rate(xusbxti)) {
41 phyclk |= S3C_PHYCLK_CLKSEL_12M;
44 phyclk |= S3C_PHYCLK_CLKSEL_24M;
48 /* default reference clock */
54 /* TODO: select external clock/oscillator */
55 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
57 /* set to normal OTG PHY */
58 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
61 /* reset OTG PHY and Link */
62 writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
64 udelay(20); /* at-least 10uS */
65 writel(0, S3C_RSTCON);
70 static int s5pv210_usb_otgphy_exit(struct platform_device *pdev)
72 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
73 S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
75 writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN,
81 int s5p_usb_phy_init(struct platform_device *pdev, int type)
83 if (type == USB_PHY_TYPE_DEVICE)
84 return s5pv210_usb_otgphy_init(pdev);
89 int s5p_usb_phy_exit(struct platform_device *pdev, int type)
91 if (type == USB_PHY_TYPE_DEVICE)
92 return s5pv210_usb_otgphy_exit(pdev);