arch/arm/mach-s5pv310/clock.c

   1 /* linux/arch/arm/mach-s5pv310/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV310 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23
  24 #include <mach/map.h>
  25 #include <mach/regs-clock.h>
  26
  27 static struct clk clk_sclk_hdmi27m = {
  28         .name           = "sclk_hdmi27m",
  29         .id             = -1,
  30         .rate           = 27000000,
  31 };
  32
  33 static struct clk clk_sclk_hdmiphy = {
  34         .name           = "sclk_hdmiphy",
  35         .id             = -1,
  36 };
  37
  38 static struct clk clk_sclk_usbphy0 = {
  39         .name           = "sclk_usbphy0",
  40         .id             = -1,
  41         .rate           = 27000000,
  42 };
  43
  44 static struct clk clk_sclk_usbphy1 = {
  45         .name           = "sclk_usbphy1",
  46         .id             = -1,
  47 };
  48
  49 static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
  50 {
  51         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
  52 }
  53
  54 static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
  55 {
  56         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
  57 }
  58
  59 static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
  60 {
  61         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
  62 }
  63
  64 static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
  65 {
  66         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
  67 }
  68
  69 static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
  70 {
  71         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
  72 }
  73
  74 static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
  75 {
  76         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
  77 }
  78
  79 static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
  80 {
  81         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
  82 }
  83
  84 static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
  85 {
  86         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
  87 }
  88
  89 static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
  90 {
  91         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
  92 }
  93
  94 static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
  95 {
  96         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
  97 }
  98
  99 static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 100 {
 101         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 102 }
 103
 104 static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 105 {
 106         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 107 }
 108
 109 static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
 110 {
 111         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 112 }
 113
 114 static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
 115 {
 116         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 117 }
 118
 119 /* Core list of CMU_CPU side */
 120
 121 static struct clksrc_clk clk_mout_apll = {
 122         .clk    = {
 123                 .name           = "mout_apll",
 124                 .id             = -1,
 125         },
 126         .sources        = &clk_src_apll,
 127         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 128 };
 129
 130 static struct clksrc_clk clk_sclk_apll = {
 131         .clk    = {
 132                 .name           = "sclk_apll",
 133                 .id             = -1,
 134                 .parent         = &clk_mout_apll.clk,
 135         },
 136         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 137 };
 138
 139 static struct clksrc_clk clk_mout_epll = {
 140         .clk    = {
 141                 .name           = "mout_epll",
 142                 .id             = -1,
 143         },
 144         .sources        = &clk_src_epll,
 145         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 146 };
 147
 148 static struct clksrc_clk clk_mout_mpll = {
 149         .clk = {
 150                 .name           = "mout_mpll",
 151                 .id             = -1,
 152         },
 153         .sources        = &clk_src_mpll,
 154         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
 155 };
 156
 157 static struct clk *clkset_moutcore_list[] = {
 158         [0] = &clk_mout_apll.clk,
 159         [1] = &clk_mout_mpll.clk,
 160 };
 161
 162 static struct clksrc_sources clkset_moutcore = {
 163         .sources        = clkset_moutcore_list,
 164         .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
 165 };
 166
 167 static struct clksrc_clk clk_moutcore = {
 168         .clk    = {
 169                 .name           = "moutcore",
 170                 .id             = -1,
 171         },
 172         .sources        = &clkset_moutcore,
 173         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
 174 };
 175
 176 static struct clksrc_clk clk_coreclk = {
 177         .clk    = {
 178                 .name           = "core_clk",
 179                 .id             = -1,
 180                 .parent         = &clk_moutcore.clk,
 181         },
 182         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
 183 };
 184
 185 static struct clksrc_clk clk_armclk = {
 186         .clk    = {
 187                 .name           = "armclk",
 188                 .id             = -1,
 189                 .parent         = &clk_coreclk.clk,
 190         },
 191 };
 192
 193 static struct clksrc_clk clk_aclk_corem0 = {
 194         .clk    = {
 195                 .name           = "aclk_corem0",
 196                 .id             = -1,
 197                 .parent         = &clk_coreclk.clk,
 198         },
 199         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 200 };
 201
 202 static struct clksrc_clk clk_aclk_cores = {
 203         .clk    = {
 204                 .name           = "aclk_cores",
 205                 .id             = -1,
 206                 .parent         = &clk_coreclk.clk,
 207         },
 208         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 209 };
 210
 211 static struct clksrc_clk clk_aclk_corem1 = {
 212         .clk    = {
 213                 .name           = "aclk_corem1",
 214                 .id             = -1,
 215                 .parent         = &clk_coreclk.clk,
 216         },
 217         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
 218 };
 219
 220 static struct clksrc_clk clk_periphclk = {
 221         .clk    = {
 222                 .name           = "periphclk",
 223                 .id             = -1,
 224                 .parent         = &clk_coreclk.clk,
 225         },
 226         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 227 };
 228
 229 /* Core list of CMU_CORE side */
 230
 231 static struct clk *clkset_corebus_list[] = {
 232         [0] = &clk_mout_mpll.clk,
 233         [1] = &clk_sclk_apll.clk,
 234 };
 235
 236 static struct clksrc_sources clkset_mout_corebus = {
 237         .sources        = clkset_corebus_list,
 238         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 239 };
 240
 241 static struct clksrc_clk clk_mout_corebus = {
 242         .clk    = {
 243                 .name           = "mout_corebus",
 244                 .id             = -1,
 245         },
 246         .sources        = &clkset_mout_corebus,
 247         .reg_src        = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 },
 248 };
 249
 250 static struct clksrc_clk clk_sclk_dmc = {
 251         .clk    = {
 252                 .name           = "sclk_dmc",
 253                 .id             = -1,
 254                 .parent         = &clk_mout_corebus.clk,
 255         },
 256         .reg_div        = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
 257 };
 258
 259 static struct clksrc_clk clk_aclk_cored = {
 260         .clk    = {
 261                 .name           = "aclk_cored",
 262                 .id             = -1,
 263                 .parent         = &clk_sclk_dmc.clk,
 264         },
 265         .reg_div        = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
 266 };
 267
 268 static struct clksrc_clk clk_aclk_corep = {
 269         .clk    = {
 270                 .name           = "aclk_corep",
 271                 .id             = -1,
 272                 .parent         = &clk_aclk_cored.clk,
 273         },
 274         .reg_div        = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
 275 };
 276
 277 static struct clksrc_clk clk_aclk_acp = {
 278         .clk    = {
 279                 .name           = "aclk_acp",
 280                 .id             = -1,
 281                 .parent         = &clk_mout_corebus.clk,
 282         },
 283         .reg_div        = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
 284 };
 285
 286 static struct clksrc_clk clk_pclk_acp = {
 287         .clk    = {
 288                 .name           = "pclk_acp",
 289                 .id             = -1,
 290                 .parent         = &clk_aclk_acp.clk,
 291         },
 292         .reg_div        = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
 293 };
 294
 295 /* Core list of CMU_TOP side */
 296
 297 static struct clk *clkset_aclk_top_list[] = {
 298         [0] = &clk_mout_mpll.clk,
 299         [1] = &clk_sclk_apll.clk,
 300 };
 301
 302 static struct clksrc_sources clkset_aclk = {
 303         .sources        = clkset_aclk_top_list,
 304         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 305 };
 306
 307 static struct clksrc_clk clk_aclk_200 = {
 308         .clk    = {
 309                 .name           = "aclk_200",
 310                 .id             = -1,
 311         },
 312         .sources        = &clkset_aclk,
 313         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
 314         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 315 };
 316
 317 static struct clksrc_clk clk_aclk_100 = {
 318         .clk    = {
 319                 .name           = "aclk_100",
 320                 .id             = -1,
 321         },
 322         .sources        = &clkset_aclk,
 323         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
 324         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 325 };
 326
 327 static struct clksrc_clk clk_aclk_160 = {
 328         .clk    = {
 329                 .name           = "aclk_160",
 330                 .id             = -1,
 331         },
 332         .sources        = &clkset_aclk,
 333         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
 334         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 335 };
 336
 337 static struct clksrc_clk clk_aclk_133 = {
 338         .clk    = {
 339                 .name           = "aclk_133",
 340                 .id             = -1,
 341         },
 342         .sources        = &clkset_aclk,
 343         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
 344         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 345 };
 346
 347 static struct clk *clkset_vpllsrc_list[] = {
 348         [0] = &clk_fin_vpll,
 349         [1] = &clk_sclk_hdmi27m,
 350 };
 351
 352 static struct clksrc_sources clkset_vpllsrc = {
 353         .sources        = clkset_vpllsrc_list,
 354         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 355 };
 356
 357 static struct clksrc_clk clk_vpllsrc = {
 358         .clk    = {
 359                 .name           = "vpll_src",
 360                 .id             = -1,
 361                 .enable         = s5pv310_clksrc_mask_top_ctrl,
 362                 .ctrlbit        = (1 << 0),
 363         },
 364         .sources        = &clkset_vpllsrc,
 365         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
 366 };
 367
 368 static struct clk *clkset_sclk_vpll_list[] = {
 369         [0] = &clk_vpllsrc.clk,
 370         [1] = &clk_fout_vpll,
 371 };
 372
 373 static struct clksrc_sources clkset_sclk_vpll = {
 374         .sources        = clkset_sclk_vpll_list,
 375         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 376 };
 377
 378 static struct clksrc_clk clk_sclk_vpll = {
 379         .clk    = {
 380                 .name           = "sclk_vpll",
 381                 .id             = -1,
 382         },
 383         .sources        = &clkset_sclk_vpll,
 384         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 385 };
 386
 387 static struct clk init_clocks_disable[] = {
 388         {
 389                 .name           = "timers",
 390                 .id             = -1,
 391                 .parent         = &clk_aclk_100.clk,
 392                 .enable         = s5pv310_clk_ip_peril_ctrl,
 393                 .ctrlbit        = (1<<24),
 394         }, {
 395                 .name           = "csis",
 396                 .id             = 0,
 397                 .enable         = s5pv310_clk_ip_cam_ctrl,
 398                 .ctrlbit        = (1 << 4),
 399         }, {
 400                 .name           = "csis",
 401                 .id             = 1,
 402                 .enable         = s5pv310_clk_ip_cam_ctrl,
 403                 .ctrlbit        = (1 << 5),
 404         }, {
 405                 .name           = "fimc",
 406                 .id             = 0,
 407                 .enable         = s5pv310_clk_ip_cam_ctrl,
 408                 .ctrlbit        = (1 << 0),
 409         }, {
 410                 .name           = "fimc",
 411                 .id             = 1,
 412                 .enable         = s5pv310_clk_ip_cam_ctrl,
 413                 .ctrlbit        = (1 << 1),
 414         }, {
 415                 .name           = "fimc",
 416                 .id             = 2,
 417                 .enable         = s5pv310_clk_ip_cam_ctrl,
 418                 .ctrlbit        = (1 << 2),
 419         }, {
 420                 .name           = "fimc",
 421                 .id             = 3,
 422                 .enable         = s5pv310_clk_ip_cam_ctrl,
 423                 .ctrlbit        = (1 << 3),
 424         }, {
 425                 .name           = "fimd",
 426                 .id             = 0,
 427                 .enable         = s5pv310_clk_ip_lcd0_ctrl,
 428                 .ctrlbit        = (1 << 0),
 429         }, {
 430                 .name           = "fimd",
 431                 .id             = 1,
 432                 .enable         = s5pv310_clk_ip_lcd1_ctrl,
 433                 .ctrlbit        = (1 << 0),
 434         }, {
 435                 .name           = "hsmmc",
 436                 .id             = 0,
 437                 .parent         = &clk_aclk_133.clk,
 438                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 439                 .ctrlbit        = (1 << 5),
 440         }, {
 441                 .name           = "hsmmc",
 442                 .id             = 1,
 443                 .parent         = &clk_aclk_133.clk,
 444                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 445                 .ctrlbit        = (1 << 6),
 446         }, {
 447                 .name           = "hsmmc",
 448                 .id             = 2,
 449                 .parent         = &clk_aclk_133.clk,
 450                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 451                 .ctrlbit        = (1 << 7),
 452         }, {
 453                 .name           = "hsmmc",
 454                 .id             = 3,
 455                 .parent         = &clk_aclk_133.clk,
 456                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 457                 .ctrlbit        = (1 << 8),
 458         }, {
 459                 .name           = "hsmmc",
 460                 .id             = 4,
 461                 .parent         = &clk_aclk_133.clk,
 462                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 463                 .ctrlbit        = (1 << 9),
 464         }, {
 465                 .name           = "sata",
 466                 .id             = -1,
 467                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 468                 .ctrlbit        = (1 << 10),
 469         }, {
 470                 .name           = "pdma",
 471                 .id             = 0,
 472                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 473                 .ctrlbit        = (1 << 0),
 474         }, {
 475                 .name           = "pdma",
 476                 .id             = 1,
 477                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 478                 .ctrlbit        = (1 << 1),
 479         }, {
 480                 .name           = "adc",
 481                 .id             = -1,
 482                 .enable         = s5pv310_clk_ip_peril_ctrl,
 483                 .ctrlbit        = (1 << 15),
 484         }, {
 485                 .name           = "rtc",
 486                 .id             = -1,
 487                 .enable         = s5pv310_clk_ip_perir_ctrl,
 488                 .ctrlbit        = (1 << 15),
 489         }, {
 490                 .name           = "watchdog",
 491                 .id             = -1,
 492                 .enable         = s5pv310_clk_ip_perir_ctrl,
 493                 .ctrlbit        = (1 << 14),
 494         }, {
 495                 .name           = "usbhost",
 496                 .id             = -1,
 497                 .enable         = s5pv310_clk_ip_fsys_ctrl ,
 498                 .ctrlbit        = (1 << 12),
 499         }, {
 500                 .name           = "otg",
 501                 .id             = -1,
 502                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 503                 .ctrlbit        = (1 << 13),
 504         }, {
 505                 .name           = "spi",
 506                 .id             = 0,
 507                 .enable         = s5pv310_clk_ip_peril_ctrl,
 508                 .ctrlbit        = (1 << 16),
 509         }, {
 510                 .name           = "spi",
 511                 .id             = 1,
 512                 .enable         = s5pv310_clk_ip_peril_ctrl,
 513                 .ctrlbit        = (1 << 17),
 514         }, {
 515                 .name           = "spi",
 516                 .id             = 2,
 517                 .enable         = s5pv310_clk_ip_peril_ctrl,
 518                 .ctrlbit        = (1 << 18),
 519         }, {
 520                 .name           = "ac97",
 521                 .id             = -1,
 522                 .enable         = s5pv310_clk_ip_peril_ctrl,
 523                 .ctrlbit        = (1 << 27),
 524         }, {
 525                 .name           = "fimg2d",
 526                 .id             = -1,
 527                 .enable         = s5pv310_clk_ip_image_ctrl,
 528                 .ctrlbit        = (1 << 0),
 529         }, {
 530                 .name           = "i2c",
 531                 .id             = 0,
 532                 .parent         = &clk_aclk_100.clk,
 533                 .enable         = s5pv310_clk_ip_peril_ctrl,
 534                 .ctrlbit        = (1 << 6),
 535         }, {
 536                 .name           = "i2c",
 537                 .id             = 1,
 538                 .parent         = &clk_aclk_100.clk,
 539                 .enable         = s5pv310_clk_ip_peril_ctrl,
 540                 .ctrlbit        = (1 << 7),
 541         }, {
 542                 .name           = "i2c",
 543                 .id             = 2,
 544                 .parent         = &clk_aclk_100.clk,
 545                 .enable         = s5pv310_clk_ip_peril_ctrl,
 546                 .ctrlbit        = (1 << 8),
 547         }, {
 548                 .name           = "i2c",
 549                 .id             = 3,
 550                 .parent         = &clk_aclk_100.clk,
 551                 .enable         = s5pv310_clk_ip_peril_ctrl,
 552                 .ctrlbit        = (1 << 9),
 553         }, {
 554                 .name           = "i2c",
 555                 .id             = 4,
 556                 .parent         = &clk_aclk_100.clk,
 557                 .enable         = s5pv310_clk_ip_peril_ctrl,
 558                 .ctrlbit        = (1 << 10),
 559         }, {
 560                 .name           = "i2c",
 561                 .id             = 5,
 562                 .parent         = &clk_aclk_100.clk,
 563                 .enable         = s5pv310_clk_ip_peril_ctrl,
 564                 .ctrlbit        = (1 << 11),
 565         }, {
 566                 .name           = "i2c",
 567                 .id             = 6,
 568                 .parent         = &clk_aclk_100.clk,
 569                 .enable         = s5pv310_clk_ip_peril_ctrl,
 570                 .ctrlbit        = (1 << 12),
 571         }, {
 572                 .name           = "i2c",
 573                 .id             = 7,
 574                 .parent         = &clk_aclk_100.clk,
 575                 .enable         = s5pv310_clk_ip_peril_ctrl,
 576                 .ctrlbit        = (1 << 13),
 577         },
 578 };
 579
 580 static struct clk init_clocks[] = {
 581         {
 582                 .name           = "uart",
 583                 .id             = 0,
 584                 .enable         = s5pv310_clk_ip_peril_ctrl,
 585                 .ctrlbit        = (1 << 0),
 586         }, {
 587                 .name           = "uart",
 588                 .id             = 1,
 589                 .enable         = s5pv310_clk_ip_peril_ctrl,
 590                 .ctrlbit        = (1 << 1),
 591         }, {
 592                 .name           = "uart",
 593                 .id             = 2,
 594                 .enable         = s5pv310_clk_ip_peril_ctrl,
 595                 .ctrlbit        = (1 << 2),
 596         }, {
 597                 .name           = "uart",
 598                 .id             = 3,
 599                 .enable         = s5pv310_clk_ip_peril_ctrl,
 600                 .ctrlbit        = (1 << 3),
 601         }, {
 602                 .name           = "uart",
 603                 .id             = 4,
 604                 .enable         = s5pv310_clk_ip_peril_ctrl,
 605                 .ctrlbit        = (1 << 4),
 606         }, {
 607                 .name           = "uart",
 608                 .id             = 5,
 609                 .enable         = s5pv310_clk_ip_peril_ctrl,
 610                 .ctrlbit        = (1 << 5),
 611         }
 612 };
 613
 614 static struct clk *clkset_group_list[] = {
 615         [0] = &clk_ext_xtal_mux,
 616         [1] = &clk_xusbxti,
 617         [2] = &clk_sclk_hdmi27m,
 618         [3] = &clk_sclk_usbphy0,
 619         [4] = &clk_sclk_usbphy1,
 620         [5] = &clk_sclk_hdmiphy,
 621         [6] = &clk_mout_mpll.clk,
 622         [7] = &clk_mout_epll.clk,
 623         [8] = &clk_sclk_vpll.clk,
 624 };
 625
 626 static struct clksrc_sources clkset_group = {
 627         .sources        = clkset_group_list,
 628         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 629 };
 630
 631 static struct clk *clkset_mout_g2d0_list[] = {
 632         [0] = &clk_mout_mpll.clk,
 633         [1] = &clk_sclk_apll.clk,
 634 };
 635
 636 static struct clksrc_sources clkset_mout_g2d0 = {
 637         .sources        = clkset_mout_g2d0_list,
 638         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
 639 };
 640
 641 static struct clksrc_clk clk_mout_g2d0 = {
 642         .clk    = {
 643                 .name           = "mout_g2d0",
 644                 .id             = -1,
 645         },
 646         .sources        = &clkset_mout_g2d0,
 647         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 648 };
 649
 650 static struct clk *clkset_mout_g2d1_list[] = {
 651         [0] = &clk_mout_epll.clk,
 652         [1] = &clk_sclk_vpll.clk,
 653 };
 654
 655 static struct clksrc_sources clkset_mout_g2d1 = {
 656         .sources        = clkset_mout_g2d1_list,
 657         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
 658 };
 659
 660 static struct clksrc_clk clk_mout_g2d1 = {
 661         .clk    = {
 662                 .name           = "mout_g2d1",
 663                 .id             = -1,
 664         },
 665         .sources        = &clkset_mout_g2d1,
 666         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 667 };
 668
 669 static struct clk *clkset_mout_g2d_list[] = {
 670         [0] = &clk_mout_g2d0.clk,
 671         [1] = &clk_mout_g2d1.clk,
 672 };
 673
 674 static struct clksrc_sources clkset_mout_g2d = {
 675         .sources        = clkset_mout_g2d_list,
 676         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
 677 };
 678
 679 static struct clksrc_clk clk_dout_mmc0 = {
 680         .clk            = {
 681                 .name           = "dout_mmc0",
 682                 .id             = -1,
 683         },
 684         .sources = &clkset_group,
 685         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
 686         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 687 };
 688
 689 static struct clksrc_clk clk_dout_mmc1 = {
 690         .clk            = {
 691                 .name           = "dout_mmc1",
 692                 .id             = -1,
 693         },
 694         .sources = &clkset_group,
 695         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
 696         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 697 };
 698
 699 static struct clksrc_clk clk_dout_mmc2 = {
 700         .clk            = {
 701                 .name           = "dout_mmc2",
 702                 .id             = -1,
 703         },
 704         .sources = &clkset_group,
 705         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
 706         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 707 };
 708
 709 static struct clksrc_clk clk_dout_mmc3 = {
 710         .clk            = {
 711                 .name           = "dout_mmc3",
 712                 .id             = -1,
 713         },
 714         .sources = &clkset_group,
 715         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
 716         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
 717 };
 718
 719 static struct clksrc_clk clk_dout_mmc4 = {
 720         .clk            = {
 721                 .name           = "dout_mmc4",
 722                 .id             = -1,
 723         },
 724         .sources = &clkset_group,
 725         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
 726         .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
 727 };
 728
 729 static struct clksrc_clk clksrcs[] = {
 730         {
 731                 .clk    = {
 732                         .name           = "uclk1",
 733                         .id             = 0,
 734                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
 735                         .ctrlbit        = (1 << 0),
 736                 },
 737                 .sources = &clkset_group,
 738                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
 739                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
 740         }, {
 741                 .clk            = {
 742                         .name           = "uclk1",
 743                         .id             = 1,
 744                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
 745                         .ctrlbit        = (1 << 4),
 746                 },
 747                 .sources = &clkset_group,
 748                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
 749                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
 750         }, {
 751                 .clk            = {
 752                         .name           = "uclk1",
 753                         .id             = 2,
 754                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
 755                         .ctrlbit        = (1 << 8),
 756                 },
 757                 .sources = &clkset_group,
 758                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
 759                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
 760         }, {
 761                 .clk            = {
 762                         .name           = "uclk1",
 763                         .id             = 3,
 764                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
 765                         .ctrlbit        = (1 << 12),
 766                 },
 767                 .sources = &clkset_group,
 768                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
 769                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
 770         }, {
 771                 .clk            = {
 772                         .name           = "sclk_pwm",
 773                         .id             = -1,
 774                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
 775                         .ctrlbit        = (1 << 24),
 776                 },
 777                 .sources = &clkset_group,
 778                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
 779                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
 780         }, {
 781                 .clk            = {
 782                         .name           = "sclk_csis",
 783                         .id             = 0,
 784                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
 785                         .ctrlbit        = (1 << 24),
 786                 },
 787                 .sources = &clkset_group,
 788                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
 789                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
 790         }, {
 791                 .clk            = {
 792                         .name           = "sclk_csis",
 793                         .id             = 1,
 794                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
 795                         .ctrlbit        = (1 << 28),
 796                 },
 797                 .sources = &clkset_group,
 798                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
 799                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
 800         }, {
 801                 .clk            = {
 802                         .name           = "sclk_cam",
 803                         .id             = 0,
 804                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
 805                         .ctrlbit        = (1 << 16),
 806                 },
 807                 .sources = &clkset_group,
 808                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
 809                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
 810         }, {
 811                 .clk            = {
 812                         .name           = "sclk_cam",
 813                         .id             = 1,
 814                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
 815                         .ctrlbit        = (1 << 20),
 816                 },
 817                 .sources = &clkset_group,
 818                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
 819                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
 820         }, {
 821                 .clk            = {
 822                         .name           = "sclk_fimc",
 823                         .id             = 0,
 824                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
 825                         .ctrlbit        = (1 << 0),
 826                 },
 827                 .sources = &clkset_group,
 828                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
 829                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
 830         }, {
 831                 .clk            = {
 832                         .name           = "sclk_fimc",
 833                         .id             = 1,
 834                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
 835                         .ctrlbit        = (1 << 4),
 836                 },
 837                 .sources = &clkset_group,
 838                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
 839                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
 840         }, {
 841                 .clk            = {
 842                         .name           = "sclk_fimc",
 843                         .id             = 2,
 844                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
 845                         .ctrlbit        = (1 << 8),
 846                 },
 847                 .sources = &clkset_group,
 848                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
 849                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
 850         }, {
 851                 .clk            = {
 852                         .name           = "sclk_fimc",
 853                         .id             = 3,
 854                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
 855                         .ctrlbit        = (1 << 12),
 856                 },
 857                 .sources = &clkset_group,
 858                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
 859                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
 860         }, {
 861                 .clk            = {
 862                         .name           = "sclk_fimd",
 863                         .id             = 0,
 864                         .enable         = s5pv310_clksrc_mask_lcd0_ctrl,
 865                         .ctrlbit        = (1 << 0),
 866                 },
 867                 .sources = &clkset_group,
 868                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
 869                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
 870         }, {
 871                 .clk            = {
 872                         .name           = "sclk_fimd",
 873                         .id             = 1,
 874                         .enable         = s5pv310_clksrc_mask_lcd1_ctrl,
 875                         .ctrlbit        = (1 << 0),
 876                 },
 877                 .sources = &clkset_group,
 878                 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
 879                 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
 880         }, {
 881                 .clk            = {
 882                         .name           = "sclk_sata",
 883                         .id             = -1,
 884                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
 885                         .ctrlbit        = (1 << 24),
 886                 },
 887                 .sources = &clkset_mout_corebus,
 888                 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
 889                 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
 890         }, {
 891                 .clk            = {
 892                         .name           = "sclk_spi",
 893                         .id             = 0,
 894                         .enable         = s5pv310_clksrc_mask_peril1_ctrl,
 895                         .ctrlbit        = (1 << 16),
 896                 },
 897                 .sources = &clkset_group,
 898                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
 899                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
 900         }, {
 901                 .clk            = {
 902                         .name           = "sclk_spi",
 903                         .id             = 1,
 904                         .enable         = s5pv310_clksrc_mask_peril1_ctrl,
 905                         .ctrlbit        = (1 << 20),
 906                 },
 907                 .sources = &clkset_group,
 908                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
 909                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
 910         }, {
 911                 .clk            = {
 912                         .name           = "sclk_spi",
 913                         .id             = 2,
 914                         .enable         = s5pv310_clksrc_mask_peril1_ctrl,
 915                         .ctrlbit        = (1 << 24),
 916                 },
 917                 .sources = &clkset_group,
 918                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
 919                 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
 920         }, {
 921                 .clk            = {
 922                         .name           = "sclk_fimg2d",
 923                         .id             = -1,
 924                 },
 925                 .sources = &clkset_mout_g2d,
 926                 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
 927                 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
 928         }, {
 929                 .clk            = {
 930                         .name           = "sclk_mmc",
 931                         .id             = 0,
 932                         .parent         = &clk_dout_mmc0.clk,
 933                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
 934                         .ctrlbit        = (1 << 0),
 935                 },
 936                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
 937         }, {
 938                 .clk            = {
 939                         .name           = "sclk_mmc",
 940                         .id             = 1,
 941                         .parent         = &clk_dout_mmc1.clk,
 942                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
 943                         .ctrlbit        = (1 << 4),
 944                 },
 945                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
 946         }, {
 947                 .clk            = {
 948                         .name           = "sclk_mmc",
 949                         .id             = 2,
 950                         .parent         = &clk_dout_mmc2.clk,
 951                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
 952                         .ctrlbit        = (1 << 8),
 953                 },
 954                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
 955         }, {
 956                 .clk            = {
 957                         .name           = "sclk_mmc",
 958                         .id             = 3,
 959                         .parent         = &clk_dout_mmc3.clk,
 960                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
 961                         .ctrlbit        = (1 << 12),
 962                 },
 963                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
 964         }, {
 965                 .clk            = {
 966                         .name           = "sclk_mmc",
 967                         .id             = 4,
 968                         .parent         = &clk_dout_mmc4.clk,
 969                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
 970                         .ctrlbit        = (1 << 16),
 971                 },
 972                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
 973         }
 974 };
 975
 976 /* Clock initialization code */
 977 static struct clksrc_clk *sysclks[] = {
 978         &clk_mout_apll,
 979         &clk_sclk_apll,
 980         &clk_mout_epll,
 981         &clk_mout_mpll,
 982         &clk_moutcore,
 983         &clk_coreclk,
 984         &clk_armclk,
 985         &clk_aclk_corem0,
 986         &clk_aclk_cores,
 987         &clk_aclk_corem1,
 988         &clk_periphclk,
 989         &clk_mout_corebus,
 990         &clk_sclk_dmc,
 991         &clk_aclk_cored,
 992         &clk_aclk_corep,
 993         &clk_aclk_acp,
 994         &clk_pclk_acp,
 995         &clk_vpllsrc,
 996         &clk_sclk_vpll,
 997         &clk_aclk_200,
 998         &clk_aclk_100,
 999         &clk_aclk_160,
1000         &clk_aclk_133,
1001         &clk_dout_mmc0,
1002         &clk_dout_mmc1,
1003         &clk_dout_mmc2,
1004         &clk_dout_mmc3,
1005         &clk_dout_mmc4,
1006 };
1007
1008 void __init_or_cpufreq s5pv310_setup_clocks(void)
1009 {
1010         struct clk *xtal_clk;
1011         unsigned long apll;
1012         unsigned long mpll;
1013         unsigned long epll;
1014         unsigned long vpll;
1015         unsigned long vpllsrc;
1016         unsigned long xtal;
1017         unsigned long armclk;
1018         unsigned long sclk_dmc;
1019         unsigned long aclk_200;
1020         unsigned long aclk_100;
1021         unsigned long aclk_160;
1022         unsigned long aclk_133;
1023         unsigned int ptr;
1024
1025         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1026
1027         xtal_clk = clk_get(NULL, "xtal");
1028         BUG_ON(IS_ERR(xtal_clk));
1029
1030         xtal = clk_get_rate(xtal_clk);
1031         clk_put(xtal_clk);
1032
1033         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1034
1035         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
1036         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
1037         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1038                                 __raw_readl(S5P_EPLL_CON1), pll_4600);
1039
1040         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1041         vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1042                                 __raw_readl(S5P_VPLL_CON1), pll_4650);
1043
1044         clk_fout_apll.rate = apll;
1045         clk_fout_mpll.rate = mpll;
1046         clk_fout_epll.rate = epll;
1047         clk_fout_vpll.rate = vpll;
1048
1049         printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1050                         apll, mpll, epll, vpll);
1051
1052         armclk = clk_get_rate(&clk_armclk.clk);
1053         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1054
1055         aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1056         aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1057         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1058         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1059
1060         printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1061                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1062                         armclk, sclk_dmc, aclk_200,
1063                         aclk_100, aclk_160, aclk_133);
1064
1065         clk_f.rate = armclk;
1066         clk_h.rate = sclk_dmc;
1067         clk_p.rate = aclk_100;
1068
1069         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1070                 s3c_set_clksrc(&clksrcs[ptr], true);
1071 }
1072
1073 static struct clk *clks[] __initdata = {
1074         /* Nothing here yet */
1075 };
1076
1077 void __init s5pv310_register_clocks(void)
1078 {
1079         struct clk *clkp;
1080         int ret;
1081         int ptr;
1082
1083         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1084         if (ret > 0)
1085                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
1086
1087         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1088                 s3c_register_clksrc(sysclks[ptr], 1);
1089
1090         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1091         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1092
1093         clkp = init_clocks_disable;
1094         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1095                 ret = s3c24xx_register_clock(clkp);
1096                 if (ret < 0) {
1097                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
1098                                clkp->name, ret);
1099                 }
1100                 (clkp->enable)(clkp, 0);
1101         }
1102
1103         s3c_pwmclk_init();
1104 }