2 * linux/arch/arm/mach-sa1100/irq.c
4 * Copyright (C) 2015 Dmitry Eremin-Solenikov
5 * Copyright (C) 1999-2001 Nicolas Pitre
7 * Generic IRQ handling for the SA11x0.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/syscore_ops.h>
20 #include <linux/irqchip/irq-sa11x0.h>
22 #include <soc/sa1100/pwer.h>
24 #include <asm/exception.h>
26 #define ICIP 0x00 /* IC IRQ Pending reg. */
27 #define ICMR 0x04 /* IC Mask Reg. */
28 #define ICLR 0x08 /* IC Level Reg. */
29 #define ICCR 0x0C /* IC Control Reg. */
30 #define ICFP 0x10 /* IC FIQ Pending reg. */
31 #define ICPR 0x20 /* IC Pending Reg. */
33 static void __iomem *iobase;
36 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
37 * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
39 static void sa1100_mask_irq(struct irq_data *d)
43 reg = readl_relaxed(iobase + ICMR);
44 reg &= ~BIT(d->hwirq);
45 writel_relaxed(reg, iobase + ICMR);
48 static void sa1100_unmask_irq(struct irq_data *d)
52 reg = readl_relaxed(iobase + ICMR);
54 writel_relaxed(reg, iobase + ICMR);
57 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
59 return sa11x0_sc_set_wake(d->hwirq, on);
62 static struct irq_chip sa1100_normal_chip = {
64 .irq_ack = sa1100_mask_irq,
65 .irq_mask = sa1100_mask_irq,
66 .irq_unmask = sa1100_unmask_irq,
67 .irq_set_wake = sa1100_set_wake,
70 static int sa1100_normal_irqdomain_map(struct irq_domain *d,
71 unsigned int irq, irq_hw_number_t hwirq)
73 irq_set_chip_and_handler(irq, &sa1100_normal_chip,
75 set_irq_flags(irq, IRQF_VALID);
80 static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
81 .map = sa1100_normal_irqdomain_map,
82 .xlate = irq_domain_xlate_onetwocell,
85 static struct irq_domain *sa1100_normal_irqdomain;
87 static struct sa1100irq_state {
94 static int sa1100irq_suspend(void)
96 struct sa1100irq_state *st = &sa1100irq_state;
99 st->icmr = readl_relaxed(iobase + ICMR);
100 st->iclr = readl_relaxed(iobase + ICLR);
101 st->iccr = readl_relaxed(iobase + ICCR);
104 * Disable all GPIO-based interrupts.
106 writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR);
111 static void sa1100irq_resume(void)
113 struct sa1100irq_state *st = &sa1100irq_state;
116 writel_relaxed(st->iccr, iobase + ICCR);
117 writel_relaxed(st->iclr, iobase + ICLR);
119 writel_relaxed(st->icmr, iobase + ICMR);
123 static struct syscore_ops sa1100irq_syscore_ops = {
124 .suspend = sa1100irq_suspend,
125 .resume = sa1100irq_resume,
128 static int __init sa1100irq_init_devicefs(void)
130 register_syscore_ops(&sa1100irq_syscore_ops);
134 device_initcall(sa1100irq_init_devicefs);
136 static asmlinkage void __exception_irq_entry
137 sa1100_handle_irq(struct pt_regs *regs)
139 uint32_t icip, icmr, mask;
142 icip = readl_relaxed(iobase + ICIP);
143 icmr = readl_relaxed(iobase + ICMR);
149 handle_domain_irq(sa1100_normal_irqdomain,
150 ffs(mask) - 1, regs);
154 void __init sa11x0_init_irq_nodt(int irq_start, resource_size_t io_start)
156 iobase = ioremap(io_start, SZ_64K);
157 if (WARN_ON(!iobase))
160 /* disable all IRQs */
161 writel_relaxed(0, iobase + ICMR);
163 /* all IRQs are IRQ, not FIQ */
164 writel_relaxed(0, iobase + ICLR);
167 * Whatever the doc says, this has to be set for the wait-on-irq
168 * instruction to work... on a SA1100 rev 9 at least.
170 writel_relaxed(1, iobase + ICCR);
172 sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
174 &sa1100_normal_irqdomain_ops, NULL);
176 set_handle_irq(sa1100_handle_irq);