2 * linux/arch/arm/mach-sa1100/irq.c
4 * Copyright (C) 1999-2001 Nicolas Pitre
6 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/ioport.h>
17 #include <linux/syscore_ops.h>
19 #include <mach/hardware.h>
20 #include <mach/irqs.h>
21 #include <asm/mach/irq.h>
27 * SA1100 GPIO edge detection for IRQs:
28 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
29 * Use this instead of directly setting GRER/GFER.
31 static int GPIO_IRQ_rising_edge;
32 static int GPIO_IRQ_falling_edge;
33 static int GPIO_IRQ_mask = (1 << 11) - 1;
36 * To get the GPIO number from an IRQ number
38 #define GPIO_11_27_IRQ(i) ((i) - 21)
39 #define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq))
41 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
48 mask = GPIO11_27_MASK(d->irq);
50 if (type == IRQ_TYPE_PROBE) {
51 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
53 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
56 if (type & IRQ_TYPE_EDGE_RISING) {
57 GPIO_IRQ_rising_edge |= mask;
59 GPIO_IRQ_rising_edge &= ~mask;
60 if (type & IRQ_TYPE_EDGE_FALLING) {
61 GPIO_IRQ_falling_edge |= mask;
63 GPIO_IRQ_falling_edge &= ~mask;
65 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
66 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
72 * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10.
74 static void sa1100_low_gpio_ack(struct irq_data *d)
79 static void sa1100_low_gpio_mask(struct irq_data *d)
81 ICMR &= ~(1 << d->irq);
84 static void sa1100_low_gpio_unmask(struct irq_data *d)
89 static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
94 PWER &= ~(1 << d->irq);
98 static struct irq_chip sa1100_low_gpio_chip = {
100 .irq_ack = sa1100_low_gpio_ack,
101 .irq_mask = sa1100_low_gpio_mask,
102 .irq_unmask = sa1100_low_gpio_unmask,
103 .irq_set_type = sa1100_gpio_type,
104 .irq_set_wake = sa1100_low_gpio_wake,
108 * IRQ11 (GPIO11 through 27) handler. We enter here with the
109 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
110 * and call the handler.
113 sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
117 mask = GEDR & 0xfffff800;
120 * clear down all currently active IRQ sources.
121 * We will be processing them all.
129 generic_handle_irq(irq);
134 mask = GEDR & 0xfffff800;
139 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
140 * In addition, the IRQs are all collected up into one bit in the
141 * interrupt controller registers.
143 static void sa1100_high_gpio_ack(struct irq_data *d)
145 unsigned int mask = GPIO11_27_MASK(d->irq);
150 static void sa1100_high_gpio_mask(struct irq_data *d)
152 unsigned int mask = GPIO11_27_MASK(d->irq);
154 GPIO_IRQ_mask &= ~mask;
160 static void sa1100_high_gpio_unmask(struct irq_data *d)
162 unsigned int mask = GPIO11_27_MASK(d->irq);
164 GPIO_IRQ_mask |= mask;
166 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
167 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
170 static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
173 PWER |= GPIO11_27_MASK(d->irq);
175 PWER &= ~GPIO11_27_MASK(d->irq);
179 static struct irq_chip sa1100_high_gpio_chip = {
181 .irq_ack = sa1100_high_gpio_ack,
182 .irq_mask = sa1100_high_gpio_mask,
183 .irq_unmask = sa1100_high_gpio_unmask,
184 .irq_set_type = sa1100_gpio_type,
185 .irq_set_wake = sa1100_high_gpio_wake,
189 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
190 * this is for internal IRQs i.e. from 11 to 31.
192 static void sa1100_mask_irq(struct irq_data *d)
194 ICMR &= ~(1 << d->irq);
197 static void sa1100_unmask_irq(struct irq_data *d)
199 ICMR |= (1 << d->irq);
203 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
205 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
207 if (d->irq == IRQ_RTCAlrm) {
217 static struct irq_chip sa1100_normal_chip = {
219 .irq_ack = sa1100_mask_irq,
220 .irq_mask = sa1100_mask_irq,
221 .irq_unmask = sa1100_unmask_irq,
222 .irq_set_wake = sa1100_set_wake,
225 static struct resource irq_resource =
226 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
228 static struct sa1100irq_state {
235 static int sa1100irq_suspend(void)
237 struct sa1100irq_state *st = &sa1100irq_state;
245 * Disable all GPIO-based interrupts.
247 ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
248 IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
252 * Set the appropriate edges for wakeup.
254 GRER = PWER & GPIO_IRQ_rising_edge;
255 GFER = PWER & GPIO_IRQ_falling_edge;
258 * Clear any pending GPIO interrupts.
265 static void sa1100irq_resume(void)
267 struct sa1100irq_state *st = &sa1100irq_state;
273 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
274 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
280 static struct syscore_ops sa1100irq_syscore_ops = {
281 .suspend = sa1100irq_suspend,
282 .resume = sa1100irq_resume,
285 static int __init sa1100irq_init_devicefs(void)
287 register_syscore_ops(&sa1100irq_syscore_ops);
291 device_initcall(sa1100irq_init_devicefs);
293 void __init sa1100_init_irq(void)
297 request_resource(&iomem_resource, &irq_resource);
299 /* disable all IRQs */
302 /* all IRQs are IRQ, not FIQ */
305 /* clear all GPIO edge detects */
311 * Whatever the doc says, this has to be set for the wait-on-irq
312 * instruction to work... on a SA1100 rev 9 at least.
316 for (irq = 0; irq <= 10; irq++) {
317 irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
319 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
322 for (irq = 12; irq <= 31; irq++) {
323 irq_set_chip_and_handler(irq, &sa1100_normal_chip,
325 set_irq_flags(irq, IRQF_VALID);
328 for (irq = 32; irq <= 48; irq++) {
329 irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
331 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
335 * Install handler for GPIO 11-27 edge detect interrupts
337 irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
338 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);