arch/arm/mach-shmobile/board-bockw.c

   1 /*
   2  * Bock-W board support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/mfd/tmio.h>
  22 #include <linux/mmc/host.h>
  23 #include <linux/mtd/partitions.h>
  24 #include <linux/pinctrl/machine.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/regulator/fixed.h>
  27 #include <linux/regulator/machine.h>
  28 #include <linux/smsc911x.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/spi/flash.h>
  31 #include <mach/common.h>
  32 #include <mach/irqs.h>
  33 #include <mach/r8a7778.h>
  34 #include <asm/mach/arch.h>
  35
  36 /*
  37  *      CN9(Upper side) SCIF/RCAN selection
  38  *
  39  *              1,4     3,6
  40  * SW40         SCIF    RCAN
  41  * SW41         SCIF    RCAN
  42  */
  43
  44 /*
  45  * MMC (CN26) pin
  46  *
  47  * SW6  (D2)    3 pin
  48  * SW7  (D5)    ON
  49  * SW8  (D3)    3 pin
  50  * SW10 (D4)    1 pin
  51  * SW12 (CLK)   1 pin
  52  * SW13 (D6)    3 pin
  53  * SW14 (CMD)   ON
  54  * SW15 (D6)    1 pin
  55  * SW16 (D0)    ON
  56  * SW17 (D1)    ON
  57  * SW18 (D7)    3 pin
  58  * SW19 (MMC)   1 pin
  59  */
  60
  61 /* Dummy supplies, where voltage doesn't matter */
  62 static struct regulator_consumer_supply dummy_supplies[] = {
  63         REGULATOR_SUPPLY("vddvario", "smsc911x"),
  64         REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  65 };
  66
  67 static struct smsc911x_platform_config smsc911x_data = {
  68         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  69         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
  70         .flags          = SMSC911X_USE_32BIT,
  71         .phy_interface  = PHY_INTERFACE_MODE_MII,
  72 };
  73
  74 static struct resource smsc911x_resources[] = {
  75         DEFINE_RES_MEM(0x18300000, 0x1000),
  76         DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
  77 };
  78
  79 /* SDHI */
  80 static struct sh_mobile_sdhi_info sdhi0_info = {
  81         .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
  82         .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  83         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
  84 };
  85
  86 static struct sh_eth_plat_data ether_platform_data __initdata = {
  87         .phy            = 0x01,
  88         .edmac_endian   = EDMAC_LITTLE_ENDIAN,
  89         .register_type  = SH_ETH_REG_FAST_RCAR,
  90         .phy_interface  = PHY_INTERFACE_MODE_RMII,
  91         /*
  92          * Although the LINK signal is available on the board, it's connected to
  93          * the link/activity LED output of the PHY, thus the link disappears and
  94          * reappears after each packet.  We'd be better off ignoring such signal
  95          * and getting the link state from the PHY indirectly.
  96          */
  97         .no_ether_link  = 1,
  98 };
  99
 100 /* I2C */
 101 static struct i2c_board_info i2c0_devices[] = {
 102         {
 103                 I2C_BOARD_INFO("rx8581", 0x51),
 104         },
 105 };
 106
 107 /* HSPI*/
 108 static struct mtd_partition m25p80_spi_flash_partitions[] = {
 109         {
 110                 .name   = "data(spi)",
 111                 .size   = 0x0100000,
 112                 .offset = 0,
 113         },
 114 };
 115
 116 static struct flash_platform_data spi_flash_data = {
 117         .name           = "m25p80",
 118         .type           = "s25fl008k",
 119         .parts          = m25p80_spi_flash_partitions,
 120         .nr_parts       = ARRAY_SIZE(m25p80_spi_flash_partitions),
 121 };
 122
 123 static struct spi_board_info spi_board_info[] __initdata = {
 124         {
 125                 .modalias       = "m25p80",
 126                 .max_speed_hz   = 104000000,
 127                 .chip_select    = 0,
 128                 .bus_num        = 0,
 129                 .mode           = SPI_MODE_0,
 130                 .platform_data  = &spi_flash_data,
 131         },
 132 };
 133
 134 /* MMC */
 135 static struct sh_mmcif_plat_data sh_mmcif_plat = {
 136         .sup_pclk       = 0,
 137         .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
 138         .caps           = MMC_CAP_4_BIT_DATA |
 139                           MMC_CAP_8_BIT_DATA |
 140                           MMC_CAP_NEEDS_POLL,
 141 };
 142
 143 static const struct pinctrl_map bockw_pinctrl_map[] = {
 144         /* Ether */
 145         PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7778",
 146                                   "ether_rmii", "ether"),
 147         /* HSPI0 */
 148         PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778",
 149                                   "hspi0_a", "hspi0"),
 150         /* MMC */
 151         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
 152                                   "mmc_data8", "mmc"),
 153         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
 154                                   "mmc_ctrl", "mmc"),
 155         /* SCIF0 */
 156         PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
 157                                   "scif0_data_a", "scif0"),
 158         PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
 159                                   "scif0_ctrl", "scif0"),
 160         /* SDHI0 */
 161         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
 162                                   "sdhi0", "sdhi0"),
 163 };
 164
 165 #define FPGA    0x18200000
 166 #define IRQ0MR  0x30
 167 #define PFC     0xfffc0000
 168 #define PUPR4   0x110
 169 static void __init bockw_init(void)
 170 {
 171         void __iomem *base;
 172
 173         r8a7778_clock_init();
 174         r8a7778_init_irq_extpin(1);
 175         r8a7778_add_standard_devices();
 176         r8a7778_add_ether_device(&ether_platform_data);
 177         r8a7778_add_i2c_device(0);
 178         r8a7778_add_hspi_device(0);
 179         r8a7778_add_mmc_device(&sh_mmcif_plat);
 180
 181         i2c_register_board_info(0, i2c0_devices,
 182                                 ARRAY_SIZE(i2c0_devices));
 183         spi_register_board_info(spi_board_info,
 184                                 ARRAY_SIZE(spi_board_info));
 185         pinctrl_register_mappings(bockw_pinctrl_map,
 186                                   ARRAY_SIZE(bockw_pinctrl_map));
 187         r8a7778_pinmux_init();
 188
 189         /* for SMSC */
 190         base = ioremap_nocache(FPGA, SZ_1M);
 191         if (base) {
 192                 /*
 193                  * CAUTION
 194                  *
 195                  * IRQ0/1 is cascaded interrupt from FPGA.
 196                  * it should be cared in the future
 197                  * Now, it is assuming IRQ0 was used only from SMSC.
 198                  */
 199                 u16 val = ioread16(base + IRQ0MR);
 200                 val &= ~(1 << 4); /* enable SMSC911x */
 201                 iowrite16(val, base + IRQ0MR);
 202                 iounmap(base);
 203
 204                 regulator_register_fixed(0, dummy_supplies,
 205                                          ARRAY_SIZE(dummy_supplies));
 206
 207                 platform_device_register_resndata(
 208                         &platform_bus, "smsc911x", -1,
 209                         smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
 210                         &smsc911x_data, sizeof(smsc911x_data));
 211         }
 212
 213         /* for SDHI */
 214         base = ioremap_nocache(PFC, 0x200);
 215         if (base) {
 216                 /*
 217                  * FIXME
 218                  *
 219                  * SDHI CD/WP pin needs pull-up
 220                  */
 221                 iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
 222                 iounmap(base);
 223
 224                 r8a7778_sdhi_init(0, &sdhi0_info);
 225         }
 226 }
 227
 228 static const char *bockw_boards_compat_dt[] __initdata = {
 229         "renesas,bockw",
 230         NULL,
 231 };
 232
 233 DT_MACHINE_START(BOCKW_DT, "bockw")
 234         .init_early     = r8a7778_init_delay,
 235         .init_irq       = r8a7778_init_irq_dt,
 236         .init_machine   = bockw_init,
 237         .init_time      = shmobile_timer_init,
 238         .dt_compat      = bockw_boards_compat_dt,
 239 MACHINE_END