2 * r7a72100 clock framework support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2012 Phil Edworthy
6 * Copyright (C) 2011 Magnus Damm
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #include <linux/init.h>
18 #include <linux/kernel.h>
20 #include <linux/sh_clk.h>
21 #include <linux/clkdev.h>
22 #include <mach/common.h>
23 #include <mach/r7s72100.h>
25 /* Frequency Control Registers */
26 #define FRQCR 0xfcfe0010
27 #define FRQCR2 0xfcfe0014
28 /* Standby Control Registers */
29 #define STBCR3 0xfcfe0420
30 #define STBCR4 0xfcfe0424
31 #define STBCR7 0xfcfe0430
32 #define STBCR9 0xfcfe0438
33 #define STBCR10 0xfcfe043c
37 static struct clk_mapping cpg_mapping = {
42 /* Fixed 32 KHz root clock for RTC */
43 static struct clk r_clk = {
48 * Default rate for the root input clock, reset this with clk_set_rate()
49 * from the platform code.
51 static struct clk extal_clk = {
53 .mapping = &cpg_mapping,
56 static unsigned long pll_recalc(struct clk *clk)
58 return clk->parent->rate * PLL_RATE;
61 static struct sh_clk_ops pll_clk_ops = {
65 static struct clk pll_clk = {
68 .flags = CLK_ENABLE_ON_INIT,
71 static unsigned long bus_recalc(struct clk *clk)
73 return clk->parent->rate / 3;
76 static struct sh_clk_ops bus_clk_ops = {
80 static struct clk bus_clk = {
83 .flags = CLK_ENABLE_ON_INIT,
86 static unsigned long peripheral0_recalc(struct clk *clk)
88 return clk->parent->rate / 12;
91 static struct sh_clk_ops peripheral0_clk_ops = {
92 .recalc = peripheral0_recalc,
95 static struct clk peripheral0_clk = {
96 .ops = &peripheral0_clk_ops,
98 .flags = CLK_ENABLE_ON_INIT,
101 static unsigned long peripheral1_recalc(struct clk *clk)
103 return clk->parent->rate / 6;
106 static struct sh_clk_ops peripheral1_clk_ops = {
107 .recalc = peripheral1_recalc,
110 static struct clk peripheral1_clk = {
111 .ops = &peripheral1_clk_ops,
113 .flags = CLK_ENABLE_ON_INIT,
116 struct clk *main_clks[] = {
125 static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
126 static int multipliers[] = { 1, 2, 1, 1 };
128 static struct clk_div_mult_table div4_div_mult_table = {
130 .nr_divisors = ARRAY_SIZE(div2),
131 .multipliers = multipliers,
132 .nr_multipliers = ARRAY_SIZE(multipliers),
135 static struct clk_div4_table div4_table = {
136 .div_mult_table = &div4_div_mult_table,
142 #define DIV4(_reg, _bit, _mask, _flags) \
143 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
145 /* The mask field specifies the div2 entries that are valid */
146 struct clk div4_clks[DIV4_NR] = {
147 [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
148 | CLK_ENABLE_ON_INIT),
152 MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
153 MSTP97, MSTP96, MSTP95, MSTP94,
155 MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
159 static struct clk mstp_clks[MSTP_NR] = {
160 [MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
161 [MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
162 [MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
163 [MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
164 [MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
165 [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
166 [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
167 [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
168 [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
169 [MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
170 [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
171 [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
172 [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
173 [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
174 [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
175 [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
176 [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
177 [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
178 [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
181 static struct clk_lookup lookups[] = {
183 CLKDEV_CON_ID("rclk", &r_clk),
184 CLKDEV_CON_ID("extal", &extal_clk),
185 CLKDEV_CON_ID("pll_clk", &pll_clk),
186 CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
189 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
192 CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
193 CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
194 CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
195 CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
196 CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
197 CLKDEV_DEV_ID("e800c800.spi", &mstp_clks[MSTP107]),
198 CLKDEV_DEV_ID("e800d000.spi", &mstp_clks[MSTP106]),
199 CLKDEV_DEV_ID("e800d800.spi", &mstp_clks[MSTP105]),
200 CLKDEV_DEV_ID("e800e000.spi", &mstp_clks[MSTP104]),
201 CLKDEV_DEV_ID("e800e800.spi", &mstp_clks[MSTP103]),
202 CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),
203 CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),
204 CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),
205 CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]),
206 CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
207 CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
210 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
211 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
212 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
213 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
214 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
215 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
216 CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
217 CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
220 void __init r7s72100_clock_init(void)
224 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
225 ret = clk_register(main_clks[k]);
227 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
230 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
233 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
238 panic("failed to setup rza1 clocks\n");