2 * SH7372 clock framework support
4 * Copyright (C) 2010 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/init.h>
20 #include <linux/kernel.h>
22 #include <linux/sh_clk.h>
23 #include <mach/common.h>
24 #include <asm/clkdev.h>
26 /* SH7372 registers */
27 #define FRQCRA 0xe6150000
28 #define FRQCRB 0xe6150004
29 #define FRQCRC 0xe61500e0
30 #define FRQCRD 0xe61500e4
31 #define VCLKCR1 0xe6150008
32 #define VCLKCR2 0xe615000c
33 #define VCLKCR3 0xe615001c
34 #define FMSICKCR 0xe6150010
35 #define FMSOCKCR 0xe6150014
36 #define FSIACKCR 0xe6150018
37 #define FSIBCKCR 0xe6150090
38 #define SUBCKCR 0xe6150080
39 #define SPUCKCR 0xe6150084
40 #define VOUCKCR 0xe6150088
41 #define HDMICKCR 0xe6150094
42 #define DSITCKCR 0xe6150060
43 #define DSI0PCKCR 0xe6150064
44 #define DSI1PCKCR 0xe6150098
45 #define PLLC01CR 0xe6150028
46 #define PLLC2CR 0xe615002c
47 #define SMSTPCR0 0xe6150130
48 #define SMSTPCR1 0xe6150134
49 #define SMSTPCR2 0xe6150138
50 #define SMSTPCR3 0xe615013c
51 #define SMSTPCR4 0xe6150140
53 #define FSIDIVA 0xFE1F8000
54 #define FSIDIVB 0xFE1F8008
56 /* Platforms must set frequency on their DV_CLKI pin */
57 struct clk sh7372_dv_clki_clk = {
60 /* Fixed 32 KHz root clock from EXTALR pin */
61 static struct clk r_clk = {
66 * 26MHz default rate for the EXTAL1 root input clock.
67 * If needed, reset this with clk_set_rate() from the platform code.
69 struct clk sh7372_extal1_clk = {
74 * 48MHz default rate for the EXTAL2 root input clock.
75 * If needed, reset this with clk_set_rate() from the platform code.
77 struct clk sh7372_extal2_clk = {
81 /* A fixed divide-by-2 block */
82 static unsigned long div2_recalc(struct clk *clk)
84 return clk->parent->rate / 2;
87 static struct clk_ops div2_clk_ops = {
88 .recalc = div2_recalc,
91 /* Divide dv_clki by two */
92 struct clk sh7372_dv_clki_div2_clk = {
94 .parent = &sh7372_dv_clki_clk,
97 /* Divide extal1 by two */
98 static struct clk extal1_div2_clk = {
100 .parent = &sh7372_extal1_clk,
103 /* Divide extal2 by two */
104 static struct clk extal2_div2_clk = {
105 .ops = &div2_clk_ops,
106 .parent = &sh7372_extal2_clk,
109 /* Divide extal2 by four */
110 static struct clk extal2_div4_clk = {
111 .ops = &div2_clk_ops,
112 .parent = &extal2_div2_clk,
115 /* PLLC0 and PLLC1 */
116 static unsigned long pllc01_recalc(struct clk *clk)
118 unsigned long mult = 1;
120 if (__raw_readl(PLLC01CR) & (1 << 14))
121 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
123 return clk->parent->rate * mult;
126 static struct clk_ops pllc01_clk_ops = {
127 .recalc = pllc01_recalc,
130 static struct clk pllc0_clk = {
131 .ops = &pllc01_clk_ops,
132 .flags = CLK_ENABLE_ON_INIT,
133 .parent = &extal1_div2_clk,
134 .enable_reg = (void __iomem *)FRQCRC,
137 static struct clk pllc1_clk = {
138 .ops = &pllc01_clk_ops,
139 .flags = CLK_ENABLE_ON_INIT,
140 .parent = &extal1_div2_clk,
141 .enable_reg = (void __iomem *)FRQCRA,
144 /* Divide PLLC1 by two */
145 static struct clk pllc1_div2_clk = {
146 .ops = &div2_clk_ops,
147 .parent = &pllc1_clk,
152 /* Indices are important - they are the actual src selecting values */
153 static struct clk *pllc2_parent[] = {
154 [0] = &extal1_div2_clk,
155 [1] = &extal2_div2_clk,
156 [2] = &sh7372_dv_clki_div2_clk,
159 /* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
160 static struct cpufreq_frequency_table pllc2_freq_table[29];
162 static void pllc2_table_rebuild(struct clk *clk)
166 /* Initialise PLLC2 frequency table */
167 for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
168 pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
169 pllc2_freq_table[i].index = i;
172 /* This is a special entry - switching PLL off makes it a repeater */
173 pllc2_freq_table[i].frequency = clk->parent->rate;
174 pllc2_freq_table[i].index = i;
176 pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
177 pllc2_freq_table[i].index = i;
180 static unsigned long pllc2_recalc(struct clk *clk)
182 unsigned long mult = 1;
184 pllc2_table_rebuild(clk);
187 * If the PLL is off, mult == 1, clk->rate will be updated in
190 if (__raw_readl(PLLC2CR) & (1 << 31))
191 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
193 return clk->parent->rate * mult;
196 static long pllc2_round_rate(struct clk *clk, unsigned long rate)
198 return clk_rate_table_round(clk, clk->freq_table, rate);
201 static int pllc2_enable(struct clk *clk)
205 __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
207 for (i = 0; i < 100; i++)
208 if (__raw_readl(PLLC2CR) & 0x80000000) {
209 clk->rate = pllc2_recalc(clk);
213 pr_err("%s(): timeout!\n", __func__);
218 static void pllc2_disable(struct clk *clk)
220 __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
223 static int pllc2_set_rate(struct clk *clk, unsigned long rate)
228 idx = clk_rate_table_find(clk, clk->freq_table, rate);
232 if (rate == clk->parent->rate) {
237 value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
239 if (value & 0x80000000)
242 __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR);
244 if (value & 0x80000000)
245 return pllc2_enable(clk);
250 static int pllc2_set_parent(struct clk *clk, struct clk *parent)
255 if (!clk->parent_table || !clk->parent_num)
258 /* Search the parent */
259 for (i = 0; i < clk->parent_num; i++)
260 if (clk->parent_table[i] == parent)
263 if (i == clk->parent_num)
266 ret = clk_reparent(clk, parent);
270 value = __raw_readl(PLLC2CR) & ~(3 << 6);
272 __raw_writel(value | (i << 6), PLLC2CR);
274 /* Rebiuld the frequency table */
275 pllc2_table_rebuild(clk);
280 static struct clk_ops pllc2_clk_ops = {
281 .recalc = pllc2_recalc,
282 .round_rate = pllc2_round_rate,
283 .set_rate = pllc2_set_rate,
284 .enable = pllc2_enable,
285 .disable = pllc2_disable,
286 .set_parent = pllc2_set_parent,
289 struct clk sh7372_pllc2_clk = {
290 .ops = &pllc2_clk_ops,
291 .parent = &extal1_div2_clk,
292 .freq_table = pllc2_freq_table,
293 .nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1,
294 .parent_table = pllc2_parent,
295 .parent_num = ARRAY_SIZE(pllc2_parent),
298 /* External input clock (pin name: FSIACK/FSIBCK ) */
299 struct clk sh7372_fsiack_clk = {
302 struct clk sh7372_fsibck_clk = {
305 static struct clk *main_clks[] = {
310 &sh7372_dv_clki_div2_clk,
322 static void div4_kick(struct clk *clk)
326 /* set KICK bit in FRQCRB to update hardware setting */
327 value = __raw_readl(FRQCRB);
329 __raw_writel(value, FRQCRB);
332 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
333 24, 32, 36, 48, 0, 72, 96, 0 };
335 static struct clk_div_mult_table div4_div_mult_table = {
336 .divisors = divisors,
337 .nr_divisors = ARRAY_SIZE(divisors),
340 static struct clk_div4_table div4_table = {
341 .div_mult_table = &div4_div_mult_table,
345 enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
346 DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP,
347 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
348 DIV4_DDRP, DIV4_NR };
350 #define DIV4(_reg, _bit, _mask, _flags) \
351 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
353 static struct clk div4_clks[DIV4_NR] = {
354 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
355 [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
356 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
357 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
358 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
359 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
360 [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
361 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
362 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
363 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
364 [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
365 [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
366 [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
367 [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
368 [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
371 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
373 DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
376 static struct clk div6_clks[DIV6_NR] = {
377 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
378 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
379 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
380 [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
381 [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
382 [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
383 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
384 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
385 [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
386 [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
387 [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
390 enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
392 /* Indices are important - they are the actual src selecting values */
393 static struct clk *hdmi_parent[] = {
394 [0] = &pllc1_div2_clk,
395 [1] = &sh7372_pllc2_clk,
396 [2] = &sh7372_dv_clki_clk,
397 [3] = NULL, /* pllc2_div4 not implemented yet */
400 static struct clk *fsiackcr_parent[] = {
401 [0] = &pllc1_div2_clk,
402 [1] = &sh7372_pllc2_clk,
403 [2] = &sh7372_fsiack_clk, /* external input for FSI A */
404 [3] = NULL, /* setting prohibited */
407 static struct clk *fsibckcr_parent[] = {
408 [0] = &pllc1_div2_clk,
409 [1] = &sh7372_pllc2_clk,
410 [2] = &sh7372_fsibck_clk, /* external input for FSI B */
411 [3] = NULL, /* setting prohibited */
414 static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
415 [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
416 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
417 [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
418 fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
419 [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
420 fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
424 static unsigned long fsidiv_recalc(struct clk *clk)
428 value = __raw_readl(clk->mapping->base);
430 if ((value & 0x3) != 0x3)
437 return clk->parent->rate / value;
440 static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
442 return clk_rate_div_range_round(clk, 2, 0xffff, rate);
445 static void fsidiv_disable(struct clk *clk)
447 __raw_writel(0, clk->mapping->base);
450 static int fsidiv_enable(struct clk *clk)
454 value = __raw_readl(clk->mapping->base) >> 16;
460 __raw_writel((value << 16) | 0x3, clk->mapping->base);
465 static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
469 if (clk->parent->rate == rate) {
474 idx = (clk->parent->rate / rate) & 0xffff;
478 __raw_writel(idx << 16, clk->mapping->base);
479 return fsidiv_enable(clk);
482 static struct clk_ops fsidiv_clk_ops = {
483 .recalc = fsidiv_recalc,
484 .round_rate = fsidiv_round_rate,
485 .set_rate = fsidiv_set_rate,
486 .enable = fsidiv_enable,
487 .disable = fsidiv_disable,
490 static struct clk_mapping sh7372_fsidiva_clk_mapping = {
495 struct clk sh7372_fsidiva_clk = {
496 .ops = &fsidiv_clk_ops,
497 .parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
498 .mapping = &sh7372_fsidiva_clk_mapping,
501 static struct clk_mapping sh7372_fsidivb_clk_mapping = {
506 struct clk sh7372_fsidivb_clk = {
507 .ops = &fsidiv_clk_ops,
508 .parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
509 .mapping = &sh7372_fsidivb_clk_mapping,
512 static struct clk *late_main_clks[] = {
519 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
520 MSTP118, MSTP117, MSTP116,
521 MSTP106, MSTP101, MSTP100,
523 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
524 MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
525 MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
528 #define MSTP(_parent, _reg, _bit, _flags) \
529 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
531 static struct clk mstp_clks[MSTP_NR] = {
532 [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
533 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
534 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
535 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
536 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
537 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
538 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
539 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
540 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
541 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
542 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
543 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
544 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
545 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
546 [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
547 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
548 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
549 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
550 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
551 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
552 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
553 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
554 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
555 [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
556 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
557 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
558 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
559 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
560 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
561 [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
562 [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
563 [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
564 [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
565 [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
566 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
569 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
570 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
571 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
573 static struct clk_lookup lookups[] = {
575 CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
576 CLKDEV_CON_ID("r_clk", &r_clk),
577 CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
578 CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
579 CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
580 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
581 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
582 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
583 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
584 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
585 CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
588 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
589 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
590 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
591 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
592 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
593 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
594 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
595 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
596 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
597 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
598 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
599 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
600 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
601 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
602 CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
605 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
606 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
607 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
608 CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
609 CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
610 CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FSIA]),
611 CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FSIB]),
612 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
613 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
614 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
615 CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
616 CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
617 CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
618 CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),
621 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
622 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
623 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
624 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
625 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
626 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
627 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
628 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
629 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
630 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
631 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
632 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
633 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
634 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
635 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
636 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
637 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
638 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
639 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
640 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
641 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
642 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
643 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
644 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
645 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
646 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
647 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
648 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */
649 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP323]), /* USB0 */
650 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
651 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
652 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
653 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
654 CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
655 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
656 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
657 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
658 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
659 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
661 CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
662 CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
663 CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
666 void __init sh7372_clock_init(void)
670 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
671 ret = clk_register(main_clks[k]);
674 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
677 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
680 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
683 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
685 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
686 ret = clk_register(late_main_clks[k]);
688 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
693 panic("failed to setup sh7372 clocks\n");