2 * sh7372 Power management support
4 * Copyright (C) 2011 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/suspend.h>
13 #include <linux/cpuidle.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/err.h>
17 #include <linux/slab.h>
18 #include <linux/pm_clock.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/irq.h>
22 #include <linux/bitrev.h>
23 #include <linux/console.h>
25 #include <asm/tlbflush.h>
26 #include <asm/suspend.h>
27 #include <mach/common.h>
28 #include <mach/sh7372.h>
29 #include <mach/pm-rmobile.h>
32 #define DBGREG1 IOMEM(0xe6100020)
33 #define DBGREG9 IOMEM(0xe6100040)
36 #define SYSTBCR IOMEM(0xe6150024)
37 #define MSTPSR0 IOMEM(0xe6150030)
38 #define MSTPSR1 IOMEM(0xe6150038)
39 #define MSTPSR2 IOMEM(0xe6150040)
40 #define MSTPSR3 IOMEM(0xe6150048)
41 #define MSTPSR4 IOMEM(0xe615004c)
42 #define PLLC01STPCR IOMEM(0xe61500c8)
45 #define SBAR IOMEM(0xe6180020)
46 #define WUPRMSK IOMEM(0xe6180028)
47 #define WUPSMSK IOMEM(0xe618002c)
48 #define WUPSMSK2 IOMEM(0xe6180048)
49 #define WUPSFAC IOMEM(0xe6180098)
50 #define IRQCR IOMEM(0xe618022c)
51 #define IRQCR2 IOMEM(0xe6180238)
52 #define IRQCR3 IOMEM(0xe6180244)
53 #define IRQCR4 IOMEM(0xe6180248)
54 #define PDNSEL IOMEM(0xe6180254)
57 #define ICR1A IOMEM(0xe6900000)
58 #define ICR2A IOMEM(0xe6900004)
59 #define ICR3A IOMEM(0xe6900008)
60 #define ICR4A IOMEM(0xe690000c)
61 #define INTMSK00A IOMEM(0xe6900040)
62 #define INTMSK10A IOMEM(0xe6900044)
63 #define INTMSK20A IOMEM(0xe6900048)
64 #define INTMSK30A IOMEM(0xe690004c)
67 /* FIXME: pointing where? */
68 #define SMFRAM 0xe6a70000
71 #define APARMBAREA IOMEM(0xe6f10020)
75 struct rmobile_pm_domain sh7372_pd_a4lc = {
80 struct rmobile_pm_domain sh7372_pd_a4mp = {
85 struct rmobile_pm_domain sh7372_pd_d4 = {
90 static int sh7372_a4r_pd_suspend(void)
92 sh7372_intcs_suspend();
93 __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
97 struct rmobile_pm_domain sh7372_pd_a4r = {
100 .suspend = sh7372_a4r_pd_suspend,
101 .resume = sh7372_intcs_resume,
104 struct rmobile_pm_domain sh7372_pd_a3rv = {
105 .genpd.name = "A3RV",
109 struct rmobile_pm_domain sh7372_pd_a3ri = {
110 .genpd.name = "A3RI",
114 static int sh7372_pd_a4s_suspend(void)
117 * The A4S domain contains the CPU core and therefore it should
118 * only be turned off if the CPU is in use.
123 struct rmobile_pm_domain sh7372_pd_a4s = {
126 .gov = &pm_domain_always_on_gov,
128 .suspend = sh7372_pd_a4s_suspend,
131 static int sh7372_a3sp_pd_suspend(void)
134 * Serial consoles make use of SCIF hardware located in A3SP,
135 * keep such power domain on if "no_console_suspend" is set.
137 return console_suspend_enabled ? 0 : -EBUSY;
140 struct rmobile_pm_domain sh7372_pd_a3sp = {
141 .genpd.name = "A3SP",
143 .gov = &pm_domain_always_on_gov,
145 .suspend = sh7372_a3sp_pd_suspend,
148 struct rmobile_pm_domain sh7372_pd_a3sg = {
149 .genpd.name = "A3SG",
153 #endif /* CONFIG_PM */
155 #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
156 static void sh7372_set_reset_vector(unsigned long address)
158 /* set reset vector, translate 4k */
159 __raw_writel(address, SBAR);
160 __raw_writel(0, APARMBAREA);
163 static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
166 __raw_writel(0, PLLC01STPCR);
168 __raw_writel(1 << 28, PLLC01STPCR);
170 __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
171 cpu_suspend(sleep_mode, sh7372_do_idle_sysc);
172 __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
174 /* disable reset vector translation */
175 __raw_writel(0, SBAR);
178 static int sh7372_sysc_valid(unsigned long *mskp, unsigned long *msk2p)
180 unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
181 unsigned long msk, msk2;
183 /* check active clocks to determine potential wakeup sources */
185 mstpsr0 = __raw_readl(MSTPSR0);
186 if ((mstpsr0 & 0x00000003) != 0x00000003) {
187 pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
191 mstpsr1 = __raw_readl(MSTPSR1);
192 if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
193 pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
197 mstpsr2 = __raw_readl(MSTPSR2);
198 if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
199 pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
203 mstpsr3 = __raw_readl(MSTPSR3);
204 if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
205 pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
209 mstpsr4 = __raw_readl(MSTPSR4);
210 if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
211 pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
218 /* make bitmaps of limited number of wakeup sources */
220 if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
223 if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
226 if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
229 if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
232 if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
235 if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
238 if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
247 static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
249 u16 tmp, irqcr1, irqcr2;
255 /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
256 for (k = 0; k <= 7; k++) {
257 tmp = (icr >> ((7 - k) * 4)) & 0xf;
258 irqcr1 |= (tmp & 0x03) << (k * 2);
259 irqcr2 |= (tmp >> 2) << (k * 2);
266 static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
268 u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
271 /* read IRQ0A -> IRQ15A mask */
272 tmp = bitrev8(__raw_readb(INTMSK00A));
273 tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
275 /* setup WUPSMSK from clocks and external IRQ mask */
276 msk = (~msk & 0xc030000f) | (tmp << 4);
277 __raw_writel(msk, WUPSMSK);
279 /* propage level/edge trigger for external IRQ 0->15 */
280 sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
281 sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
282 __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
283 __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
285 /* read IRQ16A -> IRQ31A mask */
286 tmp = bitrev8(__raw_readb(INTMSK20A));
287 tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
289 /* setup WUPSMSK2 from clocks and external IRQ mask */
290 msk2 = (~msk2 & 0x00030000) | tmp;
291 __raw_writel(msk2, WUPSMSK2);
293 /* propage level/edge trigger for external IRQ 16->31 */
294 sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
295 sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
296 __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
297 __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
300 static void sh7372_enter_a3sm_common(int pllc0_on)
302 /* use INTCA together with SYSC for wakeup */
303 sh7372_setup_sysc(1 << 0, 0);
304 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
305 sh7372_enter_sysc(pllc0_on, 1 << 12);
307 #endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
309 #ifdef CONFIG_CPU_IDLE
310 static int sh7372_do_idle_core_standby(unsigned long unused)
312 cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
316 static void sh7372_enter_core_standby(void)
318 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
320 /* enter sleep mode with SYSTBCR to 0x10 */
321 __raw_writel(0x10, SYSTBCR);
322 cpu_suspend(0, sh7372_do_idle_core_standby);
323 __raw_writel(0, SYSTBCR);
325 /* disable reset vector translation */
326 __raw_writel(0, SBAR);
329 static void sh7372_enter_a3sm_pll_on(void)
331 sh7372_enter_a3sm_common(1);
334 static void sh7372_enter_a3sm_pll_off(void)
336 sh7372_enter_a3sm_common(0);
339 static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
341 struct cpuidle_state *state = &drv->states[drv->state_count];
343 snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
344 strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
345 state->exit_latency = 10;
346 state->target_residency = 20 + 10;
347 state->flags = CPUIDLE_FLAG_TIME_VALID;
348 shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
351 state = &drv->states[drv->state_count];
352 snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
353 strncpy(state->desc, "A3SM PLL ON", CPUIDLE_DESC_LEN);
354 state->exit_latency = 20;
355 state->target_residency = 30 + 20;
356 state->flags = CPUIDLE_FLAG_TIME_VALID;
357 shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_on;
360 state = &drv->states[drv->state_count];
361 snprintf(state->name, CPUIDLE_NAME_LEN, "C4");
362 strncpy(state->desc, "A3SM PLL OFF", CPUIDLE_DESC_LEN);
363 state->exit_latency = 120;
364 state->target_residency = 30 + 120;
365 state->flags = CPUIDLE_FLAG_TIME_VALID;
366 shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_off;
370 static void sh7372_cpuidle_init(void)
372 shmobile_cpuidle_setup = sh7372_cpuidle_setup;
375 static void sh7372_cpuidle_init(void) {}
378 #ifdef CONFIG_SUSPEND
379 static void sh7372_enter_a4s_common(int pllc0_on)
381 sh7372_intca_suspend();
382 memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
383 sh7372_set_reset_vector(SMFRAM);
384 sh7372_enter_sysc(pllc0_on, 1 << 10);
385 sh7372_intca_resume();
388 static int sh7372_enter_suspend(suspend_state_t suspend_state)
390 unsigned long msk, msk2;
392 /* check active clocks to determine potential wakeup sources */
393 if (sh7372_sysc_valid(&msk, &msk2)) {
394 if (!console_suspend_enabled &&
395 sh7372_pd_a4s.genpd.status == GPD_STATE_POWER_OFF) {
396 /* convert INTC mask/sense to SYSC mask/sense */
397 sh7372_setup_sysc(msk, msk2);
399 /* enter A4S sleep with PLLC0 off */
400 pr_debug("entering A4S\n");
401 sh7372_enter_a4s_common(0);
406 /* default to enter A3SM sleep with PLLC0 off */
407 pr_debug("entering A3SM\n");
408 sh7372_enter_a3sm_common(0);
413 * sh7372_pm_notifier_fn - SH7372 PM notifier routine.
415 * @pm_event: Event being handled.
418 static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
419 unsigned long pm_event, void *unused)
422 case PM_SUSPEND_PREPARE:
424 * This is necessary, because the A4R domain has to be "on"
425 * when suspend_device_irqs() and resume_device_irqs() are
426 * executed during system suspend and resume, respectively, so
427 * that those functions don't crash while accessing the INTCS.
429 pm_genpd_poweron(&sh7372_pd_a4r.genpd);
431 case PM_POST_SUSPEND:
432 pm_genpd_poweroff_unused();
439 static void sh7372_suspend_init(void)
441 shmobile_suspend_ops.enter = sh7372_enter_suspend;
442 pm_notifier(sh7372_pm_notifier_fn, 0);
445 static void sh7372_suspend_init(void) {}
448 void __init sh7372_pm_init(void)
450 /* enable DBG hardware block to kick SYSC */
451 __raw_writel(0x0000a500, DBGREG9);
452 __raw_writel(0x0000a501, DBGREG9);
453 __raw_writel(0x00000000, DBGREG1);
455 /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
456 __raw_writel(0, PDNSEL);
458 sh7372_suspend_init();
459 sh7372_cpuidle_init();