2 * R8A7740 processor support
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/serial_sci.h>
28 #include <linux/sh_dma.h>
29 #include <linux/sh_timer.h>
30 #include <linux/dma-mapping.h>
31 #include <mach/dma-register.h>
32 #include <mach/r8a7740.h>
33 #include <mach/pm-rmobile.h>
34 #include <mach/common.h>
35 #include <mach/irqs.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/time.h>
41 static struct map_desc r8a7740_io_desc[] __initdata = {
44 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
47 .virtual = 0xe6000000,
48 .pfn = __phys_to_pfn(0xe6000000),
50 .type = MT_DEVICE_NONSHARED
52 #ifdef CONFIG_CACHE_L2X0
55 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
58 .virtual = 0xf0002000,
59 .pfn = __phys_to_pfn(0xf0100000),
61 .type = MT_DEVICE_NONSHARED
66 void __init r8a7740_map_io(void)
68 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
71 * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
72 * enough to allocate the frame buffer memory.
74 init_consistent_dma_size(12 << 20);
78 static struct plat_sci_port scif0_platform_data = {
79 .mapbase = 0xe6c40000,
80 .flags = UPF_BOOT_AUTOCONF,
81 .scscr = SCSCR_RE | SCSCR_TE,
82 .scbrr_algo_id = SCBRR_ALGO_4,
84 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
87 static struct platform_device scif0_device = {
91 .platform_data = &scif0_platform_data,
96 static struct plat_sci_port scif1_platform_data = {
97 .mapbase = 0xe6c50000,
98 .flags = UPF_BOOT_AUTOCONF,
99 .scscr = SCSCR_RE | SCSCR_TE,
100 .scbrr_algo_id = SCBRR_ALGO_4,
102 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
105 static struct platform_device scif1_device = {
109 .platform_data = &scif1_platform_data,
114 static struct plat_sci_port scif2_platform_data = {
115 .mapbase = 0xe6c60000,
116 .flags = UPF_BOOT_AUTOCONF,
117 .scscr = SCSCR_RE | SCSCR_TE,
118 .scbrr_algo_id = SCBRR_ALGO_4,
120 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
123 static struct platform_device scif2_device = {
127 .platform_data = &scif2_platform_data,
132 static struct plat_sci_port scif3_platform_data = {
133 .mapbase = 0xe6c70000,
134 .flags = UPF_BOOT_AUTOCONF,
135 .scscr = SCSCR_RE | SCSCR_TE,
136 .scbrr_algo_id = SCBRR_ALGO_4,
138 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
141 static struct platform_device scif3_device = {
145 .platform_data = &scif3_platform_data,
150 static struct plat_sci_port scif4_platform_data = {
151 .mapbase = 0xe6c80000,
152 .flags = UPF_BOOT_AUTOCONF,
153 .scscr = SCSCR_RE | SCSCR_TE,
154 .scbrr_algo_id = SCBRR_ALGO_4,
156 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
159 static struct platform_device scif4_device = {
163 .platform_data = &scif4_platform_data,
168 static struct plat_sci_port scif5_platform_data = {
169 .mapbase = 0xe6cb0000,
170 .flags = UPF_BOOT_AUTOCONF,
171 .scscr = SCSCR_RE | SCSCR_TE,
172 .scbrr_algo_id = SCBRR_ALGO_4,
174 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
177 static struct platform_device scif5_device = {
181 .platform_data = &scif5_platform_data,
186 static struct plat_sci_port scif6_platform_data = {
187 .mapbase = 0xe6cc0000,
188 .flags = UPF_BOOT_AUTOCONF,
189 .scscr = SCSCR_RE | SCSCR_TE,
190 .scbrr_algo_id = SCBRR_ALGO_4,
192 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
195 static struct platform_device scif6_device = {
199 .platform_data = &scif6_platform_data,
204 static struct plat_sci_port scif7_platform_data = {
205 .mapbase = 0xe6cd0000,
206 .flags = UPF_BOOT_AUTOCONF,
207 .scscr = SCSCR_RE | SCSCR_TE,
208 .scbrr_algo_id = SCBRR_ALGO_4,
210 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
213 static struct platform_device scif7_device = {
217 .platform_data = &scif7_platform_data,
222 static struct plat_sci_port scifb_platform_data = {
223 .mapbase = 0xe6c30000,
224 .flags = UPF_BOOT_AUTOCONF,
225 .scscr = SCSCR_RE | SCSCR_TE,
226 .scbrr_algo_id = SCBRR_ALGO_4,
228 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
231 static struct platform_device scifb_device = {
235 .platform_data = &scifb_platform_data,
240 static struct sh_timer_config cmt10_platform_data = {
242 .channel_offset = 0x10,
244 .clockevent_rating = 125,
245 .clocksource_rating = 125,
248 static struct resource cmt10_resources[] = {
253 .flags = IORESOURCE_MEM,
256 .start = evt2irq(0x0b00),
257 .flags = IORESOURCE_IRQ,
261 static struct platform_device cmt10_device = {
265 .platform_data = &cmt10_platform_data,
267 .resource = cmt10_resources,
268 .num_resources = ARRAY_SIZE(cmt10_resources),
271 static struct platform_device *r8a7740_early_devices[] __initdata = {
285 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
287 .slave_id = SHDMA_SLAVE_SDHI0_TX,
289 .chcr = CHCR_TX(XMIT_SZ_16BIT),
292 .slave_id = SHDMA_SLAVE_SDHI0_RX,
294 .chcr = CHCR_RX(XMIT_SZ_16BIT),
297 .slave_id = SHDMA_SLAVE_SDHI1_TX,
299 .chcr = CHCR_TX(XMIT_SZ_16BIT),
302 .slave_id = SHDMA_SLAVE_SDHI1_RX,
304 .chcr = CHCR_RX(XMIT_SZ_16BIT),
307 .slave_id = SHDMA_SLAVE_SDHI2_TX,
309 .chcr = CHCR_TX(XMIT_SZ_16BIT),
312 .slave_id = SHDMA_SLAVE_SDHI2_RX,
314 .chcr = CHCR_RX(XMIT_SZ_16BIT),
317 .slave_id = SHDMA_SLAVE_FSIA_TX,
319 .chcr = CHCR_TX(XMIT_SZ_32BIT),
322 .slave_id = SHDMA_SLAVE_FSIA_RX,
324 .chcr = CHCR_RX(XMIT_SZ_32BIT),
327 .slave_id = SHDMA_SLAVE_FSIB_TX,
329 .chcr = CHCR_TX(XMIT_SZ_32BIT),
334 #define DMA_CHANNEL(a, b, c) \
339 .chclr_offset = (0x220 - 0x20) + a \
342 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
343 DMA_CHANNEL(0x00, 0, 0),
344 DMA_CHANNEL(0x10, 0, 8),
345 DMA_CHANNEL(0x20, 4, 0),
346 DMA_CHANNEL(0x30, 4, 8),
347 DMA_CHANNEL(0x50, 8, 0),
348 DMA_CHANNEL(0x60, 8, 8),
351 static struct sh_dmae_pdata dma_platform_data = {
352 .slave = r8a7740_dmae_slaves,
353 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
354 .channel = r8a7740_dmae_channels,
355 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
356 .ts_low_shift = TS_LOW_SHIFT,
357 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
358 .ts_high_shift = TS_HI_SHIFT,
359 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
360 .ts_shift = dma_ts_shift,
361 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
362 .dmaor_init = DMAOR_DME,
366 /* Resource order important! */
367 static struct resource r8a7740_dmae0_resources[] = {
369 /* Channel registers and DMAOR */
372 .flags = IORESOURCE_MEM,
378 .flags = IORESOURCE_MEM,
382 .start = evt2irq(0x20c0),
383 .end = evt2irq(0x20c0),
384 .flags = IORESOURCE_IRQ,
387 /* IRQ for channels 0-5 */
388 .start = evt2irq(0x2000),
389 .end = evt2irq(0x20a0),
390 .flags = IORESOURCE_IRQ,
394 /* Resource order important! */
395 static struct resource r8a7740_dmae1_resources[] = {
397 /* Channel registers and DMAOR */
400 .flags = IORESOURCE_MEM,
406 .flags = IORESOURCE_MEM,
410 .start = evt2irq(0x21c0),
411 .end = evt2irq(0x21c0),
412 .flags = IORESOURCE_IRQ,
415 /* IRQ for channels 0-5 */
416 .start = evt2irq(0x2100),
417 .end = evt2irq(0x21a0),
418 .flags = IORESOURCE_IRQ,
422 /* Resource order important! */
423 static struct resource r8a7740_dmae2_resources[] = {
425 /* Channel registers and DMAOR */
428 .flags = IORESOURCE_MEM,
434 .flags = IORESOURCE_MEM,
438 .start = evt2irq(0x22c0),
439 .end = evt2irq(0x22c0),
440 .flags = IORESOURCE_IRQ,
443 /* IRQ for channels 0-5 */
444 .start = evt2irq(0x2200),
445 .end = evt2irq(0x22a0),
446 .flags = IORESOURCE_IRQ,
450 static struct platform_device dma0_device = {
451 .name = "sh-dma-engine",
453 .resource = r8a7740_dmae0_resources,
454 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
456 .platform_data = &dma_platform_data,
460 static struct platform_device dma1_device = {
461 .name = "sh-dma-engine",
463 .resource = r8a7740_dmae1_resources,
464 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
466 .platform_data = &dma_platform_data,
470 static struct platform_device dma2_device = {
471 .name = "sh-dma-engine",
473 .resource = r8a7740_dmae2_resources,
474 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
476 .platform_data = &dma_platform_data,
481 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
489 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
491 .slave_id = SHDMA_SLAVE_USBHS_TX,
492 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
494 .slave_id = SHDMA_SLAVE_USBHS_RX,
495 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
499 static struct sh_dmae_pdata usb_dma_platform_data = {
500 .slave = r8a7740_usb_dma_slaves,
501 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
502 .channel = r8a7740_usb_dma_channels,
503 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
504 .ts_low_shift = USBTS_LOW_SHIFT,
505 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
506 .ts_high_shift = USBTS_HI_SHIFT,
507 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
508 .ts_shift = dma_usbts_shift,
509 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
510 .dmaor_init = DMAOR_DME,
512 .chcr_ie_bit = 1 << 5,
519 static struct resource r8a7740_usb_dma_resources[] = {
521 /* Channel registers and DMAOR */
523 .end = 0xe68a0064 - 1,
524 .flags = IORESOURCE_MEM,
529 .end = 0xe68a0014 - 1,
530 .flags = IORESOURCE_MEM,
533 /* IRQ for channels */
534 .start = evt2irq(0x0a00),
535 .end = evt2irq(0x0a00),
536 .flags = IORESOURCE_IRQ,
540 static struct platform_device usb_dma_device = {
541 .name = "sh-dma-engine",
543 .resource = r8a7740_usb_dma_resources,
544 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
546 .platform_data = &usb_dma_platform_data,
551 static struct resource i2c0_resources[] = {
555 .end = 0xfff20425 - 1,
556 .flags = IORESOURCE_MEM,
559 .start = intcs_evt2irq(0xe00),
560 .end = intcs_evt2irq(0xe60),
561 .flags = IORESOURCE_IRQ,
565 static struct resource i2c1_resources[] = {
569 .end = 0xe6c20425 - 1,
570 .flags = IORESOURCE_MEM,
573 .start = evt2irq(0x780), /* IIC1_ALI1 */
574 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
575 .flags = IORESOURCE_IRQ,
579 static struct platform_device i2c0_device = {
580 .name = "i2c-sh_mobile",
582 .resource = i2c0_resources,
583 .num_resources = ARRAY_SIZE(i2c0_resources),
586 static struct platform_device i2c1_device = {
587 .name = "i2c-sh_mobile",
589 .resource = i2c1_resources,
590 .num_resources = ARRAY_SIZE(i2c1_resources),
593 static struct resource pmu_resources[] = {
595 .start = evt2irq(0x19a0),
596 .end = evt2irq(0x19a0),
597 .flags = IORESOURCE_IRQ,
601 static struct platform_device pmu_device = {
604 .num_resources = ARRAY_SIZE(pmu_resources),
605 .resource = pmu_resources,
608 static struct platform_device *r8a7740_late_devices[] __initdata = {
619 * r8a7740 chip has lasting errata on MERAM buffer.
620 * this is work-around for it.
622 * "Media RAM (MERAM)" on r8a7740 documentation
624 #define MEBUFCNTR 0xFE950098
625 void r8a7740_meram_workaround(void)
629 reg = ioremap_nocache(MEBUFCNTR, 4);
631 iowrite32(0x01600164, reg);
637 #define ICSTART 0x0070
639 #define i2c_read(reg, offset) ioread8(reg + offset)
640 #define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
643 * r8a7740 chip has lasting errata on I2C I/O pad reset.
644 * this is work-around for it.
646 static void r8a7740_i2c_workaround(struct platform_device *pdev)
648 struct resource *res;
651 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
652 if (unlikely(!res)) {
653 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
657 reg = ioremap(res->start, resource_size(res));
658 if (unlikely(!reg)) {
659 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
663 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
664 i2c_read(reg, ICCR); /* dummy read */
666 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
667 i2c_read(reg, ICSTART); /* dummy read */
671 i2c_write(reg, ICCR, 0x01);
672 i2c_write(reg, ICSTART, 0x00);
676 i2c_write(reg, ICCR, 0x10);
678 i2c_write(reg, ICCR, 0x00);
680 i2c_write(reg, ICCR, 0x10);
686 void __init r8a7740_add_standard_devices(void)
688 /* I2C work-around */
689 r8a7740_i2c_workaround(&i2c0_device);
690 r8a7740_i2c_workaround(&i2c1_device);
692 r8a7740_init_pm_domains();
695 platform_add_devices(r8a7740_early_devices,
696 ARRAY_SIZE(r8a7740_early_devices));
697 platform_add_devices(r8a7740_late_devices,
698 ARRAY_SIZE(r8a7740_late_devices));
700 /* add devices to PM domain */
702 rmobile_add_device_to_domain("A3SP", &scif0_device);
703 rmobile_add_device_to_domain("A3SP", &scif1_device);
704 rmobile_add_device_to_domain("A3SP", &scif2_device);
705 rmobile_add_device_to_domain("A3SP", &scif3_device);
706 rmobile_add_device_to_domain("A3SP", &scif4_device);
707 rmobile_add_device_to_domain("A3SP", &scif5_device);
708 rmobile_add_device_to_domain("A3SP", &scif6_device);
709 rmobile_add_device_to_domain("A3SP", &scif7_device);
710 rmobile_add_device_to_domain("A3SP", &scifb_device);
711 rmobile_add_device_to_domain("A3SP", &i2c1_device);
714 static void __init r8a7740_earlytimer_init(void)
716 r8a7740_clock_init(0);
717 shmobile_earlytimer_init();
720 void __init r8a7740_add_early_devices(void)
722 early_platform_add_devices(r8a7740_early_devices,
723 ARRAY_SIZE(r8a7740_early_devices));
725 /* setup early console here as well */
726 shmobile_setup_console();
728 /* override timer setup with soc-specific code */
729 shmobile_timer.init = r8a7740_earlytimer_init;
734 void __init r8a7740_add_early_devices_dt(void)
736 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
738 early_platform_add_devices(r8a7740_early_devices,
739 ARRAY_SIZE(r8a7740_early_devices));
741 /* setup early console here as well */
742 shmobile_setup_console();
745 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
749 void __init r8a7740_add_standard_devices_dt(void)
751 /* clocks are setup late during boot in the case of DT */
752 r8a7740_clock_init(0);
754 platform_add_devices(r8a7740_early_devices,
755 ARRAY_SIZE(r8a7740_early_devices));
757 of_platform_populate(NULL, of_default_bus_match_table,
758 r8a7740_auxdata_lookup, NULL);
761 static const char *r8a7740_boards_compat_dt[] __initdata = {
766 DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)")
767 .map_io = r8a7740_map_io,
768 .init_early = r8a7740_add_early_devices_dt,
769 .init_irq = r8a7740_init_irq,
770 .handle_irq = shmobile_handle_irq_intc,
771 .init_machine = r8a7740_add_standard_devices_dt,
772 .timer = &shmobile_timer,
773 .dt_compat = r8a7740_boards_compat_dt,
776 #endif /* CONFIG_USE_OF */