arch/arm/mach-shmobile/setup-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/serial_sci.h>
  29 #include <linux/sh_dma.h>
  30 #include <linux/sh_timer.h>
  31 #include <linux/platform_data/sh_ipmmu.h>
  32 #include <mach/dma-register.h>
  33 #include <mach/r8a7740.h>
  34 #include <mach/pm-rmobile.h>
  35 #include <mach/common.h>
  36 #include <mach/irqs.h>
  37 #include <asm/mach-types.h>
  38 #include <asm/mach/map.h>
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/time.h>
  41
  42 static struct map_desc r8a7740_io_desc[] __initdata = {
  43          /*
  44           * for CPGA/INTC/PFC
  45           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
  46           */
  47         {
  48                 .virtual        = 0xe6000000,
  49                 .pfn            = __phys_to_pfn(0xe6000000),
  50                 .length         = 160 << 20,
  51                 .type           = MT_DEVICE_NONSHARED
  52         },
  53 #ifdef CONFIG_CACHE_L2X0
  54         /*
  55          * for l2x0_init()
  56          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
  57          */
  58         {
  59                 .virtual        = 0xf0002000,
  60                 .pfn            = __phys_to_pfn(0xf0100000),
  61                 .length         = PAGE_SIZE,
  62                 .type           = MT_DEVICE_NONSHARED
  63         },
  64 #endif
  65 };
  66
  67 void __init r8a7740_map_io(void)
  68 {
  69         iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
  70 }
  71
  72 /* PFC */
  73 static const struct resource pfc_resources[] = {
  74         DEFINE_RES_MEM(0xe6050000, 0x8000),
  75         DEFINE_RES_MEM(0xe605800c, 0x0020),
  76 };
  77
  78 void __init r8a7740_pinmux_init(void)
  79 {
  80         platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
  81                                         ARRAY_SIZE(pfc_resources));
  82 }
  83
  84 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
  85         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
  86 };
  87
  88 static struct resource irqpin0_resources[] = {
  89         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
  90         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
  91         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
  92         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
  93         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
  94         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
  95         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
  96         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
  97         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
  98         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
  99         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
 100         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
 101         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
 102 };
 103
 104 static struct platform_device irqpin0_device = {
 105         .name           = "renesas_intc_irqpin",
 106         .id             = 0,
 107         .resource       = irqpin0_resources,
 108         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 109         .dev            = {
 110                 .platform_data  = &irqpin0_platform_data,
 111         },
 112 };
 113
 114 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 115         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 116 };
 117
 118 static struct resource irqpin1_resources[] = {
 119         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 120         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 121         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 122         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 123         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 124         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
 125         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
 126         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
 127         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
 128         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
 129         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
 130         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
 131         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
 132 };
 133
 134 static struct platform_device irqpin1_device = {
 135         .name           = "renesas_intc_irqpin",
 136         .id             = 1,
 137         .resource       = irqpin1_resources,
 138         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 139         .dev            = {
 140                 .platform_data  = &irqpin1_platform_data,
 141         },
 142 };
 143
 144 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 145         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 146 };
 147
 148 static struct resource irqpin2_resources[] = {
 149         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 150         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
 151         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
 152         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
 153         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
 154         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
 155         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
 156         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
 157         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
 158         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
 159         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
 160         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
 161         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
 162 };
 163
 164 static struct platform_device irqpin2_device = {
 165         .name           = "renesas_intc_irqpin",
 166         .id             = 2,
 167         .resource       = irqpin2_resources,
 168         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 169         .dev            = {
 170                 .platform_data  = &irqpin2_platform_data,
 171         },
 172 };
 173
 174 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 175         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 176 };
 177
 178 static struct resource irqpin3_resources[] = {
 179         DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
 180         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 181         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 182         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 183         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 184         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
 185         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
 186         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
 187         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
 188         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
 189         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
 190         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
 191         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
 192 };
 193
 194 static struct platform_device irqpin3_device = {
 195         .name           = "renesas_intc_irqpin",
 196         .id             = 3,
 197         .resource       = irqpin3_resources,
 198         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 199         .dev            = {
 200                 .platform_data  = &irqpin3_platform_data,
 201         },
 202 };
 203
 204 /* SCIFA0 */
 205 static struct plat_sci_port scif0_platform_data = {
 206         .mapbase        = 0xe6c40000,
 207         .flags          = UPF_BOOT_AUTOCONF,
 208         .scscr          = SCSCR_RE | SCSCR_TE,
 209         .scbrr_algo_id  = SCBRR_ALGO_4,
 210         .type           = PORT_SCIFA,
 211         .irqs           = SCIx_IRQ_MUXED(gic_spi(100)),
 212 };
 213
 214 static struct platform_device scif0_device = {
 215         .name           = "sh-sci",
 216         .id             = 0,
 217         .dev            = {
 218                 .platform_data  = &scif0_platform_data,
 219         },
 220 };
 221
 222 /* SCIFA1 */
 223 static struct plat_sci_port scif1_platform_data = {
 224         .mapbase        = 0xe6c50000,
 225         .flags          = UPF_BOOT_AUTOCONF,
 226         .scscr          = SCSCR_RE | SCSCR_TE,
 227         .scbrr_algo_id  = SCBRR_ALGO_4,
 228         .type           = PORT_SCIFA,
 229         .irqs           = SCIx_IRQ_MUXED(gic_spi(101)),
 230 };
 231
 232 static struct platform_device scif1_device = {
 233         .name           = "sh-sci",
 234         .id             = 1,
 235         .dev            = {
 236                 .platform_data  = &scif1_platform_data,
 237         },
 238 };
 239
 240 /* SCIFA2 */
 241 static struct plat_sci_port scif2_platform_data = {
 242         .mapbase        = 0xe6c60000,
 243         .flags          = UPF_BOOT_AUTOCONF,
 244         .scscr          = SCSCR_RE | SCSCR_TE,
 245         .scbrr_algo_id  = SCBRR_ALGO_4,
 246         .type           = PORT_SCIFA,
 247         .irqs           = SCIx_IRQ_MUXED(gic_spi(102)),
 248 };
 249
 250 static struct platform_device scif2_device = {
 251         .name           = "sh-sci",
 252         .id             = 2,
 253         .dev            = {
 254                 .platform_data  = &scif2_platform_data,
 255         },
 256 };
 257
 258 /* SCIFA3 */
 259 static struct plat_sci_port scif3_platform_data = {
 260         .mapbase        = 0xe6c70000,
 261         .flags          = UPF_BOOT_AUTOCONF,
 262         .scscr          = SCSCR_RE | SCSCR_TE,
 263         .scbrr_algo_id  = SCBRR_ALGO_4,
 264         .type           = PORT_SCIFA,
 265         .irqs           = SCIx_IRQ_MUXED(gic_spi(103)),
 266 };
 267
 268 static struct platform_device scif3_device = {
 269         .name           = "sh-sci",
 270         .id             = 3,
 271         .dev            = {
 272                 .platform_data  = &scif3_platform_data,
 273         },
 274 };
 275
 276 /* SCIFA4 */
 277 static struct plat_sci_port scif4_platform_data = {
 278         .mapbase        = 0xe6c80000,
 279         .flags          = UPF_BOOT_AUTOCONF,
 280         .scscr          = SCSCR_RE | SCSCR_TE,
 281         .scbrr_algo_id  = SCBRR_ALGO_4,
 282         .type           = PORT_SCIFA,
 283         .irqs           = SCIx_IRQ_MUXED(gic_spi(104)),
 284 };
 285
 286 static struct platform_device scif4_device = {
 287         .name           = "sh-sci",
 288         .id             = 4,
 289         .dev            = {
 290                 .platform_data  = &scif4_platform_data,
 291         },
 292 };
 293
 294 /* SCIFA5 */
 295 static struct plat_sci_port scif5_platform_data = {
 296         .mapbase        = 0xe6cb0000,
 297         .flags          = UPF_BOOT_AUTOCONF,
 298         .scscr          = SCSCR_RE | SCSCR_TE,
 299         .scbrr_algo_id  = SCBRR_ALGO_4,
 300         .type           = PORT_SCIFA,
 301         .irqs           = SCIx_IRQ_MUXED(gic_spi(105)),
 302 };
 303
 304 static struct platform_device scif5_device = {
 305         .name           = "sh-sci",
 306         .id             = 5,
 307         .dev            = {
 308                 .platform_data  = &scif5_platform_data,
 309         },
 310 };
 311
 312 /* SCIFA6 */
 313 static struct plat_sci_port scif6_platform_data = {
 314         .mapbase        = 0xe6cc0000,
 315         .flags          = UPF_BOOT_AUTOCONF,
 316         .scscr          = SCSCR_RE | SCSCR_TE,
 317         .scbrr_algo_id  = SCBRR_ALGO_4,
 318         .type           = PORT_SCIFA,
 319         .irqs           = SCIx_IRQ_MUXED(gic_spi(106)),
 320 };
 321
 322 static struct platform_device scif6_device = {
 323         .name           = "sh-sci",
 324         .id             = 6,
 325         .dev            = {
 326                 .platform_data  = &scif6_platform_data,
 327         },
 328 };
 329
 330 /* SCIFA7 */
 331 static struct plat_sci_port scif7_platform_data = {
 332         .mapbase        = 0xe6cd0000,
 333         .flags          = UPF_BOOT_AUTOCONF,
 334         .scscr          = SCSCR_RE | SCSCR_TE,
 335         .scbrr_algo_id  = SCBRR_ALGO_4,
 336         .type           = PORT_SCIFA,
 337         .irqs           = SCIx_IRQ_MUXED(gic_spi(107)),
 338 };
 339
 340 static struct platform_device scif7_device = {
 341         .name           = "sh-sci",
 342         .id             = 7,
 343         .dev            = {
 344                 .platform_data  = &scif7_platform_data,
 345         },
 346 };
 347
 348 /* SCIFB */
 349 static struct plat_sci_port scifb_platform_data = {
 350         .mapbase        = 0xe6c30000,
 351         .flags          = UPF_BOOT_AUTOCONF,
 352         .scscr          = SCSCR_RE | SCSCR_TE,
 353         .scbrr_algo_id  = SCBRR_ALGO_4,
 354         .type           = PORT_SCIFB,
 355         .irqs           = SCIx_IRQ_MUXED(gic_spi(108)),
 356 };
 357
 358 static struct platform_device scifb_device = {
 359         .name           = "sh-sci",
 360         .id             = 8,
 361         .dev            = {
 362                 .platform_data  = &scifb_platform_data,
 363         },
 364 };
 365
 366 /* CMT */
 367 static struct sh_timer_config cmt10_platform_data = {
 368         .name = "CMT10",
 369         .channel_offset = 0x10,
 370         .timer_bit = 0,
 371         .clockevent_rating = 125,
 372         .clocksource_rating = 125,
 373 };
 374
 375 static struct resource cmt10_resources[] = {
 376         [0] = {
 377                 .name   = "CMT10",
 378                 .start  = 0xe6138010,
 379                 .end    = 0xe613801b,
 380                 .flags  = IORESOURCE_MEM,
 381         },
 382         [1] = {
 383                 .start  = gic_spi(58),
 384                 .flags  = IORESOURCE_IRQ,
 385         },
 386 };
 387
 388 static struct platform_device cmt10_device = {
 389         .name           = "sh_cmt",
 390         .id             = 10,
 391         .dev = {
 392                 .platform_data  = &cmt10_platform_data,
 393         },
 394         .resource       = cmt10_resources,
 395         .num_resources  = ARRAY_SIZE(cmt10_resources),
 396 };
 397
 398 /* TMU */
 399 static struct sh_timer_config tmu00_platform_data = {
 400         .name = "TMU00",
 401         .channel_offset = 0x4,
 402         .timer_bit = 0,
 403         .clockevent_rating = 200,
 404 };
 405
 406 static struct resource tmu00_resources[] = {
 407         [0] = {
 408                 .name   = "TMU00",
 409                 .start  = 0xfff80008,
 410                 .end    = 0xfff80014 - 1,
 411                 .flags  = IORESOURCE_MEM,
 412         },
 413         [1] = {
 414                 .start  = gic_spi(198),
 415                 .flags  = IORESOURCE_IRQ,
 416         },
 417 };
 418
 419 static struct platform_device tmu00_device = {
 420         .name           = "sh_tmu",
 421         .id             = 0,
 422         .dev = {
 423                 .platform_data  = &tmu00_platform_data,
 424         },
 425         .resource       = tmu00_resources,
 426         .num_resources  = ARRAY_SIZE(tmu00_resources),
 427 };
 428
 429 static struct sh_timer_config tmu01_platform_data = {
 430         .name = "TMU01",
 431         .channel_offset = 0x10,
 432         .timer_bit = 1,
 433         .clocksource_rating = 200,
 434 };
 435
 436 static struct resource tmu01_resources[] = {
 437         [0] = {
 438                 .name   = "TMU01",
 439                 .start  = 0xfff80014,
 440                 .end    = 0xfff80020 - 1,
 441                 .flags  = IORESOURCE_MEM,
 442         },
 443         [1] = {
 444                 .start  = gic_spi(199),
 445                 .flags  = IORESOURCE_IRQ,
 446         },
 447 };
 448
 449 static struct platform_device tmu01_device = {
 450         .name           = "sh_tmu",
 451         .id             = 1,
 452         .dev = {
 453                 .platform_data  = &tmu01_platform_data,
 454         },
 455         .resource       = tmu01_resources,
 456         .num_resources  = ARRAY_SIZE(tmu01_resources),
 457 };
 458
 459 static struct sh_timer_config tmu02_platform_data = {
 460         .name = "TMU02",
 461         .channel_offset = 0x1C,
 462         .timer_bit = 2,
 463         .clocksource_rating = 200,
 464 };
 465
 466 static struct resource tmu02_resources[] = {
 467         [0] = {
 468                 .name   = "TMU02",
 469                 .start  = 0xfff80020,
 470                 .end    = 0xfff8002C - 1,
 471                 .flags  = IORESOURCE_MEM,
 472         },
 473         [1] = {
 474                 .start  = gic_spi(200),
 475                 .flags  = IORESOURCE_IRQ,
 476         },
 477 };
 478
 479 static struct platform_device tmu02_device = {
 480         .name           = "sh_tmu",
 481         .id             = 2,
 482         .dev = {
 483                 .platform_data  = &tmu02_platform_data,
 484         },
 485         .resource       = tmu02_resources,
 486         .num_resources  = ARRAY_SIZE(tmu02_resources),
 487 };
 488
 489 /* IPMMUI (an IPMMU module for ICB/LMB) */
 490 static struct resource ipmmu_resources[] = {
 491         [0] = {
 492                 .name   = "IPMMUI",
 493                 .start  = 0xfe951000,
 494                 .end    = 0xfe9510ff,
 495                 .flags  = IORESOURCE_MEM,
 496         },
 497 };
 498
 499 static const char * const ipmmu_dev_names[] = {
 500         "sh_mobile_lcdc_fb.0",
 501         "sh_mobile_lcdc_fb.1",
 502         "sh_mobile_ceu.0",
 503 };
 504
 505 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 506         .dev_names = ipmmu_dev_names,
 507         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 508 };
 509
 510 static struct platform_device ipmmu_device = {
 511         .name           = "ipmmu",
 512         .id             = -1,
 513         .dev = {
 514                 .platform_data = &ipmmu_platform_data,
 515         },
 516         .resource       = ipmmu_resources,
 517         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 518 };
 519
 520 static struct platform_device *r8a7740_devices_dt[] __initdata = {
 521         &scif0_device,
 522         &scif1_device,
 523         &scif2_device,
 524         &scif3_device,
 525         &scif4_device,
 526         &scif5_device,
 527         &scif6_device,
 528         &scif7_device,
 529         &scifb_device,
 530         &cmt10_device,
 531 };
 532
 533 static struct platform_device *r8a7740_early_devices[] __initdata = {
 534         &irqpin0_device,
 535         &irqpin1_device,
 536         &irqpin2_device,
 537         &irqpin3_device,
 538         &tmu00_device,
 539         &tmu01_device,
 540         &tmu02_device,
 541         &ipmmu_device,
 542 };
 543
 544 /* DMA */
 545 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
 546         {
 547                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 548                 .addr           = 0xe6850030,
 549                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 550                 .mid_rid        = 0xc1,
 551         }, {
 552                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 553                 .addr           = 0xe6850030,
 554                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 555                 .mid_rid        = 0xc2,
 556         }, {
 557                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 558                 .addr           = 0xe6860030,
 559                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 560                 .mid_rid        = 0xc9,
 561         }, {
 562                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 563                 .addr           = 0xe6860030,
 564                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 565                 .mid_rid        = 0xca,
 566         }, {
 567                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 568                 .addr           = 0xe6870030,
 569                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 570                 .mid_rid        = 0xcd,
 571         }, {
 572                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 573                 .addr           = 0xe6870030,
 574                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 575                 .mid_rid        = 0xce,
 576         }, {
 577                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 578                 .addr           = 0xfe1f0024,
 579                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 580                 .mid_rid        = 0xb1,
 581         }, {
 582                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 583                 .addr           = 0xfe1f0020,
 584                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 585                 .mid_rid        = 0xb2,
 586         }, {
 587                 .slave_id       = SHDMA_SLAVE_FSIB_TX,
 588                 .addr           = 0xfe1f0064,
 589                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 590                 .mid_rid        = 0xb5,
 591         }, {
 592                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 593                 .addr           = 0xe6bd0034,
 594                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 595                 .mid_rid        = 0xd1,
 596         }, {
 597                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 598                 .addr           = 0xe6bd0034,
 599                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 600                 .mid_rid        = 0xd2,
 601         },
 602 };
 603
 604 #define DMA_CHANNEL(a, b, c)                    \
 605 {                                               \
 606         .offset         = a,                    \
 607         .dmars          = b,                    \
 608         .dmars_bit      = c,                    \
 609         .chclr_offset   = (0x220 - 0x20) + a    \
 610 }
 611
 612 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
 613         DMA_CHANNEL(0x00, 0, 0),
 614         DMA_CHANNEL(0x10, 0, 8),
 615         DMA_CHANNEL(0x20, 4, 0),
 616         DMA_CHANNEL(0x30, 4, 8),
 617         DMA_CHANNEL(0x50, 8, 0),
 618         DMA_CHANNEL(0x60, 8, 8),
 619 };
 620
 621 static struct sh_dmae_pdata dma_platform_data = {
 622         .slave          = r8a7740_dmae_slaves,
 623         .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
 624         .channel        = r8a7740_dmae_channels,
 625         .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
 626         .ts_low_shift   = TS_LOW_SHIFT,
 627         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 628         .ts_high_shift  = TS_HI_SHIFT,
 629         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 630         .ts_shift       = dma_ts_shift,
 631         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 632         .dmaor_init     = DMAOR_DME,
 633         .chclr_present  = 1,
 634 };
 635
 636 /* Resource order important! */
 637 static struct resource r8a7740_dmae0_resources[] = {
 638         {
 639                 /* Channel registers and DMAOR */
 640                 .start  = 0xfe008020,
 641                 .end    = 0xfe00828f,
 642                 .flags  = IORESOURCE_MEM,
 643         },
 644         {
 645                 /* DMARSx */
 646                 .start  = 0xfe009000,
 647                 .end    = 0xfe00900b,
 648                 .flags  = IORESOURCE_MEM,
 649         },
 650         {
 651                 .name   = "error_irq",
 652                 .start  = gic_spi(34),
 653                 .end    = gic_spi(34),
 654                 .flags  = IORESOURCE_IRQ,
 655         },
 656         {
 657                 /* IRQ for channels 0-5 */
 658                 .start  = gic_spi(28),
 659                 .end    = gic_spi(33),
 660                 .flags  = IORESOURCE_IRQ,
 661         },
 662 };
 663
 664 /* Resource order important! */
 665 static struct resource r8a7740_dmae1_resources[] = {
 666         {
 667                 /* Channel registers and DMAOR */
 668                 .start  = 0xfe018020,
 669                 .end    = 0xfe01828f,
 670                 .flags  = IORESOURCE_MEM,
 671         },
 672         {
 673                 /* DMARSx */
 674                 .start  = 0xfe019000,
 675                 .end    = 0xfe01900b,
 676                 .flags  = IORESOURCE_MEM,
 677         },
 678         {
 679                 .name   = "error_irq",
 680                 .start  = gic_spi(41),
 681                 .end    = gic_spi(41),
 682                 .flags  = IORESOURCE_IRQ,
 683         },
 684         {
 685                 /* IRQ for channels 0-5 */
 686                 .start  = gic_spi(35),
 687                 .end    = gic_spi(40),
 688                 .flags  = IORESOURCE_IRQ,
 689         },
 690 };
 691
 692 /* Resource order important! */
 693 static struct resource r8a7740_dmae2_resources[] = {
 694         {
 695                 /* Channel registers and DMAOR */
 696                 .start  = 0xfe028020,
 697                 .end    = 0xfe02828f,
 698                 .flags  = IORESOURCE_MEM,
 699         },
 700         {
 701                 /* DMARSx */
 702                 .start  = 0xfe029000,
 703                 .end    = 0xfe02900b,
 704                 .flags  = IORESOURCE_MEM,
 705         },
 706         {
 707                 .name   = "error_irq",
 708                 .start  = gic_spi(48),
 709                 .end    = gic_spi(48),
 710                 .flags  = IORESOURCE_IRQ,
 711         },
 712         {
 713                 /* IRQ for channels 0-5 */
 714                 .start  = gic_spi(42),
 715                 .end    = gic_spi(47),
 716                 .flags  = IORESOURCE_IRQ,
 717         },
 718 };
 719
 720 static struct platform_device dma0_device = {
 721         .name           = "sh-dma-engine",
 722         .id             = 0,
 723         .resource       = r8a7740_dmae0_resources,
 724         .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
 725         .dev            = {
 726                 .platform_data  = &dma_platform_data,
 727         },
 728 };
 729
 730 static struct platform_device dma1_device = {
 731         .name           = "sh-dma-engine",
 732         .id             = 1,
 733         .resource       = r8a7740_dmae1_resources,
 734         .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
 735         .dev            = {
 736                 .platform_data  = &dma_platform_data,
 737         },
 738 };
 739
 740 static struct platform_device dma2_device = {
 741         .name           = "sh-dma-engine",
 742         .id             = 2,
 743         .resource       = r8a7740_dmae2_resources,
 744         .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
 745         .dev            = {
 746                 .platform_data  = &dma_platform_data,
 747         },
 748 };
 749
 750 /* USB-DMAC */
 751 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
 752         {
 753                 .offset = 0,
 754         }, {
 755                 .offset = 0x20,
 756         },
 757 };
 758
 759 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
 760         {
 761                 .slave_id       = SHDMA_SLAVE_USBHS_TX,
 762                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 763         }, {
 764                 .slave_id       = SHDMA_SLAVE_USBHS_RX,
 765                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 766         },
 767 };
 768
 769 static struct sh_dmae_pdata usb_dma_platform_data = {
 770         .slave          = r8a7740_usb_dma_slaves,
 771         .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
 772         .channel        = r8a7740_usb_dma_channels,
 773         .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
 774         .ts_low_shift   = USBTS_LOW_SHIFT,
 775         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 776         .ts_high_shift  = USBTS_HI_SHIFT,
 777         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 778         .ts_shift       = dma_usbts_shift,
 779         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 780         .dmaor_init     = DMAOR_DME,
 781         .chcr_offset    = 0x14,
 782         .chcr_ie_bit    = 1 << 5,
 783         .dmaor_is_32bit = 1,
 784         .needs_tend_set = 1,
 785         .no_dmars       = 1,
 786         .slave_only     = 1,
 787 };
 788
 789 static struct resource r8a7740_usb_dma_resources[] = {
 790         {
 791                 /* Channel registers and DMAOR */
 792                 .start  = 0xe68a0020,
 793                 .end    = 0xe68a0064 - 1,
 794                 .flags  = IORESOURCE_MEM,
 795         },
 796         {
 797                 /* VCR/SWR/DMICR */
 798                 .start  = 0xe68a0000,
 799                 .end    = 0xe68a0014 - 1,
 800                 .flags  = IORESOURCE_MEM,
 801         },
 802         {
 803                 /* IRQ for channels */
 804                 .start  = gic_spi(49),
 805                 .end    = gic_spi(49),
 806                 .flags  = IORESOURCE_IRQ,
 807         },
 808 };
 809
 810 static struct platform_device usb_dma_device = {
 811         .name           = "sh-dma-engine",
 812         .id             = 3,
 813         .resource       = r8a7740_usb_dma_resources,
 814         .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
 815         .dev            = {
 816                 .platform_data  = &usb_dma_platform_data,
 817         },
 818 };
 819
 820 /* I2C */
 821 static struct resource i2c0_resources[] = {
 822         [0] = {
 823                 .name   = "IIC0",
 824                 .start  = 0xfff20000,
 825                 .end    = 0xfff20425 - 1,
 826                 .flags  = IORESOURCE_MEM,
 827         },
 828         [1] = {
 829                 .start  = gic_spi(201),
 830                 .end    = gic_spi(204),
 831                 .flags  = IORESOURCE_IRQ,
 832         },
 833 };
 834
 835 static struct resource i2c1_resources[] = {
 836         [0] = {
 837                 .name   = "IIC1",
 838                 .start  = 0xe6c20000,
 839                 .end    = 0xe6c20425 - 1,
 840                 .flags  = IORESOURCE_MEM,
 841         },
 842         [1] = {
 843                 .start  = gic_spi(70), /* IIC1_ALI1 */
 844                 .end    = gic_spi(73), /* IIC1_DTEI1 */
 845                 .flags  = IORESOURCE_IRQ,
 846         },
 847 };
 848
 849 static struct platform_device i2c0_device = {
 850         .name           = "i2c-sh_mobile",
 851         .id             = 0,
 852         .resource       = i2c0_resources,
 853         .num_resources  = ARRAY_SIZE(i2c0_resources),
 854 };
 855
 856 static struct platform_device i2c1_device = {
 857         .name           = "i2c-sh_mobile",
 858         .id             = 1,
 859         .resource       = i2c1_resources,
 860         .num_resources  = ARRAY_SIZE(i2c1_resources),
 861 };
 862
 863 static struct resource pmu_resources[] = {
 864         [0] = {
 865                 .start  = gic_spi(83),
 866                 .end    = gic_spi(83),
 867                 .flags  = IORESOURCE_IRQ,
 868         },
 869 };
 870
 871 static struct platform_device pmu_device = {
 872         .name   = "arm-pmu",
 873         .id     = -1,
 874         .num_resources = ARRAY_SIZE(pmu_resources),
 875         .resource = pmu_resources,
 876 };
 877
 878 static struct platform_device *r8a7740_late_devices[] __initdata = {
 879         &i2c0_device,
 880         &i2c1_device,
 881         &dma0_device,
 882         &dma1_device,
 883         &dma2_device,
 884         &usb_dma_device,
 885         &pmu_device,
 886 };
 887
 888 /*
 889  * r8a7740 chip has lasting errata on MERAM buffer.
 890  * this is work-around for it.
 891  * see
 892  *      "Media RAM (MERAM)" on r8a7740 documentation
 893  */
 894 #define MEBUFCNTR       0xFE950098
 895 void r8a7740_meram_workaround(void)
 896 {
 897         void __iomem *reg;
 898
 899         reg = ioremap_nocache(MEBUFCNTR, 4);
 900         if (reg) {
 901                 iowrite32(0x01600164, reg);
 902                 iounmap(reg);
 903         }
 904 }
 905
 906 #define ICCR    0x0004
 907 #define ICSTART 0x0070
 908
 909 #define i2c_read(reg, offset)           ioread8(reg + offset)
 910 #define i2c_write(reg, offset, data)    iowrite8(data, reg + offset)
 911
 912 /*
 913  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 914  * this is work-around for it.
 915  */
 916 static void r8a7740_i2c_workaround(struct platform_device *pdev)
 917 {
 918         struct resource *res;
 919         void __iomem *reg;
 920
 921         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 922         if (unlikely(!res)) {
 923                 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
 924                 return;
 925         }
 926
 927         reg = ioremap(res->start, resource_size(res));
 928         if (unlikely(!reg)) {
 929                 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
 930                 return;
 931         }
 932
 933         i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
 934         i2c_read(reg, ICCR); /* dummy read */
 935
 936         i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
 937         i2c_read(reg, ICSTART); /* dummy read */
 938
 939         udelay(10);
 940
 941         i2c_write(reg, ICCR, 0x01);
 942         i2c_write(reg, ICSTART, 0x00);
 943
 944         udelay(10);
 945
 946         i2c_write(reg, ICCR, 0x10);
 947         udelay(10);
 948         i2c_write(reg, ICCR, 0x00);
 949         udelay(10);
 950         i2c_write(reg, ICCR, 0x10);
 951         udelay(10);
 952
 953         iounmap(reg);
 954 }
 955
 956 void __init r8a7740_add_standard_devices(void)
 957 {
 958         /* I2C work-around */
 959         r8a7740_i2c_workaround(&i2c0_device);
 960         r8a7740_i2c_workaround(&i2c1_device);
 961
 962         r8a7740_init_pm_domains();
 963
 964         /* add devices */
 965         platform_add_devices(r8a7740_early_devices,
 966                             ARRAY_SIZE(r8a7740_early_devices));
 967         platform_add_devices(r8a7740_devices_dt,
 968                             ARRAY_SIZE(r8a7740_devices_dt));
 969         platform_add_devices(r8a7740_late_devices,
 970                              ARRAY_SIZE(r8a7740_late_devices));
 971
 972         /* add devices to PM domain  */
 973
 974         rmobile_add_device_to_domain("A3SP",    &scif0_device);
 975         rmobile_add_device_to_domain("A3SP",    &scif1_device);
 976         rmobile_add_device_to_domain("A3SP",    &scif2_device);
 977         rmobile_add_device_to_domain("A3SP",    &scif3_device);
 978         rmobile_add_device_to_domain("A3SP",    &scif4_device);
 979         rmobile_add_device_to_domain("A3SP",    &scif5_device);
 980         rmobile_add_device_to_domain("A3SP",    &scif6_device);
 981         rmobile_add_device_to_domain("A3SP",    &scif7_device);
 982         rmobile_add_device_to_domain("A3SP",    &scifb_device);
 983         rmobile_add_device_to_domain("A3SP",    &i2c1_device);
 984 }
 985
 986 void __init r8a7740_add_early_devices(void)
 987 {
 988         early_platform_add_devices(r8a7740_early_devices,
 989                                    ARRAY_SIZE(r8a7740_early_devices));
 990         early_platform_add_devices(r8a7740_devices_dt,
 991                                    ARRAY_SIZE(r8a7740_devices_dt));
 992
 993         /* setup early console here as well */
 994         shmobile_setup_console();
 995 }
 996
 997 #ifdef CONFIG_USE_OF
 998
 999 void __init r8a7740_add_early_devices_dt(void)
1000 {
1001         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
1002
1003         early_platform_add_devices(r8a7740_early_devices,
1004                                    ARRAY_SIZE(r8a7740_early_devices));
1005
1006         /* setup early console here as well */
1007         shmobile_setup_console();
1008 }
1009
1010 void __init r8a7740_add_standard_devices_dt(void)
1011 {
1012         platform_add_devices(r8a7740_devices_dt,
1013                             ARRAY_SIZE(r8a7740_devices_dt));
1014         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1015 }
1016
1017 void __init r8a7740_init_delay(void)
1018 {
1019         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
1020 };
1021
1022 static void __init r8a7740_generic_init(void)
1023 {
1024         r8a7740_clock_init(0);
1025         r8a7740_add_standard_devices_dt();
1026 }
1027
1028 static const char *r8a7740_boards_compat_dt[] __initdata = {
1029         "renesas,r8a7740",
1030         NULL,
1031 };
1032
1033 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
1034         .map_io         = r8a7740_map_io,
1035         .init_early     = r8a7740_init_delay,
1036         .init_irq       = r8a7740_init_irq_of,
1037         .init_machine   = r8a7740_generic_init,
1038         .init_time      = shmobile_timer_init,
1039         .dt_compat      = r8a7740_boards_compat_dt,
1040 MACHINE_END
1041
1042 #endif /* CONFIG_USE_OF */