2 * r8a7779 processor support
4 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 * Copyright (C) 2013 Cogent Embedded, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqchip.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_data/dma-rcar-hpbdma.h>
29 #include <linux/platform_data/gpio-rcar.h>
30 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
31 #include <linux/platform_device.h>
32 #include <linux/delay.h>
33 #include <linux/input.h>
35 #include <linux/serial_sci.h>
36 #include <linux/sh_timer.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/usb/otg.h>
39 #include <linux/usb/hcd.h>
40 #include <linux/usb/ehci_pdriver.h>
41 #include <linux/usb/ohci_pdriver.h>
42 #include <linux/pm_runtime.h>
43 #include <mach/irqs.h>
44 #include <mach/r8a7779.h>
45 #include <mach/common.h>
46 #include <asm/mach-types.h>
47 #include <asm/mach/arch.h>
48 #include <asm/mach/time.h>
49 #include <asm/mach/map.h>
50 #include <asm/hardware/cache-l2x0.h>
52 static struct map_desc r8a7779_io_desc[] __initdata = {
53 /* 2M entity map for 0xf0000000 (MPCORE) */
55 .virtual = 0xf0000000,
56 .pfn = __phys_to_pfn(0xf0000000),
58 .type = MT_DEVICE_NONSHARED
60 /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
62 .virtual = 0xfe000000,
63 .pfn = __phys_to_pfn(0xfe000000),
65 .type = MT_DEVICE_NONSHARED
69 void __init r8a7779_map_io(void)
71 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
75 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
76 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
77 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
78 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
79 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
81 #define INT2NTSR0 IOMEM(0xfe700060)
82 #define INT2NTSR1 IOMEM(0xfe700064)
84 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
85 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
86 .sense_bitfield_width = 2,
89 static struct resource irqpin0_resources[] __initdata = {
90 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
91 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
92 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
93 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
94 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
95 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
96 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
97 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
98 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
101 void __init r8a7779_init_irq_extpin_dt(int irlm)
103 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
107 pr_warn("r8a7779: unable to setup external irq pin mode\n");
111 tmp = ioread32(icr0);
113 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
115 tmp &= ~(1 << 23); /* IRL mode - not supported */
116 tmp |= (1 << 21); /* LVLMODE = 1 */
117 iowrite32(tmp, icr0);
121 void __init r8a7779_init_irq_extpin(int irlm)
123 r8a7779_init_irq_extpin_dt(irlm);
125 platform_device_register_resndata(
126 &platform_bus, "renesas_intc_irqpin", -1,
127 irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
128 &irqpin0_platform_data, sizeof(irqpin0_platform_data));
132 static struct resource r8a7779_pfc_resources[] = {
133 DEFINE_RES_MEM(0xfffc0000, 0x023c),
136 static struct platform_device r8a7779_pfc_device = {
137 .name = "pfc-r8a7779",
139 .resource = r8a7779_pfc_resources,
140 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
143 #define R8A7779_GPIO(idx, npins) \
144 static struct resource r8a7779_gpio##idx##_resources[] = { \
145 DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \
146 DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \
149 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
150 .gpio_base = 32 * (idx), \
152 .number_of_pins = npins, \
153 .pctl_name = "pfc-r8a7779", \
156 static struct platform_device r8a7779_gpio##idx##_device = { \
157 .name = "gpio_rcar", \
159 .resource = r8a7779_gpio##idx##_resources, \
160 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
162 .platform_data = &r8a7779_gpio##idx##_platform_data, \
174 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
176 &r8a7779_gpio0_device,
177 &r8a7779_gpio1_device,
178 &r8a7779_gpio2_device,
179 &r8a7779_gpio3_device,
180 &r8a7779_gpio4_device,
181 &r8a7779_gpio5_device,
182 &r8a7779_gpio6_device,
185 void __init r8a7779_pinmux_init(void)
187 platform_add_devices(r8a7779_pinctrl_devices,
188 ARRAY_SIZE(r8a7779_pinctrl_devices));
191 static struct plat_sci_port scif0_platform_data = {
192 .mapbase = 0xffe40000,
193 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
194 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
195 .scbrr_algo_id = SCBRR_ALGO_2,
197 .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)),
200 static struct platform_device scif0_device = {
204 .platform_data = &scif0_platform_data,
208 static struct plat_sci_port scif1_platform_data = {
209 .mapbase = 0xffe41000,
210 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
211 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
212 .scbrr_algo_id = SCBRR_ALGO_2,
214 .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
217 static struct platform_device scif1_device = {
221 .platform_data = &scif1_platform_data,
225 static struct plat_sci_port scif2_platform_data = {
226 .mapbase = 0xffe42000,
227 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
228 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
229 .scbrr_algo_id = SCBRR_ALGO_2,
231 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
234 static struct platform_device scif2_device = {
238 .platform_data = &scif2_platform_data,
242 static struct plat_sci_port scif3_platform_data = {
243 .mapbase = 0xffe43000,
244 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
245 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
246 .scbrr_algo_id = SCBRR_ALGO_2,
248 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
251 static struct platform_device scif3_device = {
255 .platform_data = &scif3_platform_data,
259 static struct plat_sci_port scif4_platform_data = {
260 .mapbase = 0xffe44000,
261 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
262 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
263 .scbrr_algo_id = SCBRR_ALGO_2,
265 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
268 static struct platform_device scif4_device = {
272 .platform_data = &scif4_platform_data,
276 static struct plat_sci_port scif5_platform_data = {
277 .mapbase = 0xffe45000,
278 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
279 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
280 .scbrr_algo_id = SCBRR_ALGO_2,
282 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
285 static struct platform_device scif5_device = {
289 .platform_data = &scif5_platform_data,
294 static struct sh_timer_config tmu00_platform_data = {
296 .channel_offset = 0x4,
298 .clockevent_rating = 200,
301 static struct resource tmu00_resources[] = {
306 .flags = IORESOURCE_MEM,
309 .start = gic_iid(0x40),
310 .flags = IORESOURCE_IRQ,
314 static struct platform_device tmu00_device = {
318 .platform_data = &tmu00_platform_data,
320 .resource = tmu00_resources,
321 .num_resources = ARRAY_SIZE(tmu00_resources),
324 static struct sh_timer_config tmu01_platform_data = {
326 .channel_offset = 0x10,
328 .clocksource_rating = 200,
331 static struct resource tmu01_resources[] = {
336 .flags = IORESOURCE_MEM,
339 .start = gic_iid(0x41),
340 .flags = IORESOURCE_IRQ,
344 static struct platform_device tmu01_device = {
348 .platform_data = &tmu01_platform_data,
350 .resource = tmu01_resources,
351 .num_resources = ARRAY_SIZE(tmu01_resources),
355 static struct resource rcar_i2c0_res[] = {
359 .flags = IORESOURCE_MEM,
361 .start = gic_iid(0x6f),
362 .flags = IORESOURCE_IRQ,
366 static struct platform_device i2c0_device = {
369 .resource = rcar_i2c0_res,
370 .num_resources = ARRAY_SIZE(rcar_i2c0_res),
373 static struct resource rcar_i2c1_res[] = {
377 .flags = IORESOURCE_MEM,
379 .start = gic_iid(0x72),
380 .flags = IORESOURCE_IRQ,
384 static struct platform_device i2c1_device = {
387 .resource = rcar_i2c1_res,
388 .num_resources = ARRAY_SIZE(rcar_i2c1_res),
391 static struct resource rcar_i2c2_res[] = {
395 .flags = IORESOURCE_MEM,
397 .start = gic_iid(0x70),
398 .flags = IORESOURCE_IRQ,
402 static struct platform_device i2c2_device = {
405 .resource = rcar_i2c2_res,
406 .num_resources = ARRAY_SIZE(rcar_i2c2_res),
409 static struct resource rcar_i2c3_res[] = {
413 .flags = IORESOURCE_MEM,
415 .start = gic_iid(0x71),
416 .flags = IORESOURCE_IRQ,
420 static struct platform_device i2c3_device = {
423 .resource = rcar_i2c3_res,
424 .num_resources = ARRAY_SIZE(rcar_i2c3_res),
427 static struct resource sata_resources[] = {
432 .flags = IORESOURCE_MEM,
435 .start = gic_iid(0x84),
436 .flags = IORESOURCE_IRQ,
440 static struct platform_device sata_device = {
443 .resource = sata_resources,
444 .num_resources = ARRAY_SIZE(sata_resources),
446 .dma_mask = &sata_device.dev.coherent_dma_mask,
447 .coherent_dma_mask = DMA_BIT_MASK(32),
452 static struct usb_phy *phy;
454 static int usb_power_on(struct platform_device *pdev)
459 pm_runtime_enable(&pdev->dev);
460 pm_runtime_get_sync(&pdev->dev);
467 static void usb_power_off(struct platform_device *pdev)
472 usb_phy_shutdown(phy);
474 pm_runtime_put_sync(&pdev->dev);
475 pm_runtime_disable(&pdev->dev);
478 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
481 * Below are recommended values from the datasheet;
482 * see [USB :: Setting of EHCI Internal Buffer].
484 /* EHCI IP internal buffer setting */
485 iowrite32(0x00ff0040, hcd->regs + 0x0094);
486 /* EHCI IP internal buffer enable */
487 iowrite32(0x00000001, hcd->regs + 0x009C);
492 static struct usb_ehci_pdata ehcix_pdata = {
493 .power_on = usb_power_on,
494 .power_off = usb_power_off,
495 .power_suspend = usb_power_off,
496 .pre_setup = ehci_init_internal_buffer,
499 static struct resource ehci0_resources[] = {
502 .end = 0xffe70400 - 1,
503 .flags = IORESOURCE_MEM,
506 .start = gic_iid(0x4c),
507 .flags = IORESOURCE_IRQ,
511 static struct platform_device ehci0_device = {
512 .name = "ehci-platform",
515 .dma_mask = &ehci0_device.dev.coherent_dma_mask,
516 .coherent_dma_mask = 0xffffffff,
517 .platform_data = &ehcix_pdata,
519 .num_resources = ARRAY_SIZE(ehci0_resources),
520 .resource = ehci0_resources,
523 static struct resource ehci1_resources[] = {
526 .end = 0xfff70400 - 1,
527 .flags = IORESOURCE_MEM,
530 .start = gic_iid(0x4d),
531 .flags = IORESOURCE_IRQ,
535 static struct platform_device ehci1_device = {
536 .name = "ehci-platform",
539 .dma_mask = &ehci1_device.dev.coherent_dma_mask,
540 .coherent_dma_mask = 0xffffffff,
541 .platform_data = &ehcix_pdata,
543 .num_resources = ARRAY_SIZE(ehci1_resources),
544 .resource = ehci1_resources,
547 static struct usb_ohci_pdata ohcix_pdata = {
548 .power_on = usb_power_on,
549 .power_off = usb_power_off,
550 .power_suspend = usb_power_off,
553 static struct resource ohci0_resources[] = {
556 .end = 0xffe70800 - 1,
557 .flags = IORESOURCE_MEM,
560 .start = gic_iid(0x4c),
561 .flags = IORESOURCE_IRQ,
565 static struct platform_device ohci0_device = {
566 .name = "ohci-platform",
569 .dma_mask = &ohci0_device.dev.coherent_dma_mask,
570 .coherent_dma_mask = 0xffffffff,
571 .platform_data = &ohcix_pdata,
573 .num_resources = ARRAY_SIZE(ohci0_resources),
574 .resource = ohci0_resources,
577 static struct resource ohci1_resources[] = {
580 .end = 0xfff70800 - 1,
581 .flags = IORESOURCE_MEM,
584 .start = gic_iid(0x4d),
585 .flags = IORESOURCE_IRQ,
589 static struct platform_device ohci1_device = {
590 .name = "ohci-platform",
593 .dma_mask = &ohci1_device.dev.coherent_dma_mask,
594 .coherent_dma_mask = 0xffffffff,
595 .platform_data = &ohcix_pdata,
597 .num_resources = ARRAY_SIZE(ohci1_resources),
598 .resource = ohci1_resources,
602 static struct resource ether_resources[] __initdata = {
606 .flags = IORESOURCE_MEM,
608 .start = gic_iid(0xb4),
609 .flags = IORESOURCE_IRQ,
613 #define R8A7779_VIN(idx) \
614 static struct resource vin##idx##_resources[] __initdata = { \
615 DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \
616 DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \
619 static struct platform_device_info vin##idx##_info __initdata = { \
620 .parent = &platform_bus, \
621 .name = "r8a7779-vin", \
623 .res = vin##idx##_resources, \
624 .num_res = ARRAY_SIZE(vin##idx##_resources), \
625 .dma_mask = DMA_BIT_MASK(32), \
633 static struct platform_device_info *vin_info_table[] __initdata = {
642 /* Asynchronous mode register bits */
643 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */
644 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */
645 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */
646 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */
647 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */
648 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */
649 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */
650 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */
651 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */
652 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */
653 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */
654 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */
655 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */
656 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */
657 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */
658 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */
659 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */
660 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */
661 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */
662 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */
663 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */
664 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */
665 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */
666 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */
667 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */
668 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */
669 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */
670 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */
671 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */
672 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */
673 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */
674 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */
675 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */
676 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */
677 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */
678 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */
679 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */
680 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */
681 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */
682 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */
683 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */
684 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */
685 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */
686 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */
687 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */
688 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */
689 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */
690 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */
691 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */
692 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */
693 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */
694 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */
695 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */
696 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */
697 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */
698 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */
699 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
700 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */
701 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */
702 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */
703 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */
704 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */
705 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
706 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */
707 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */
708 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */
709 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */
710 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */
711 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */
712 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */
713 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */
714 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */
716 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
718 .id = HPBDMA_SLAVE_SDHI0_TX,
719 .addr = 0xffe4c000 + 0x30,
720 .dcr = HPB_DMAE_DCR_SPDS_16BIT |
722 HPB_DMAE_DCR_DPDS_16BIT,
723 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
724 HPB_DMAE_ASYNCRSTR_ASRST22 |
725 HPB_DMAE_ASYNCRSTR_ASRST23,
726 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
727 HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
728 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
729 HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
731 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
734 .id = HPBDMA_SLAVE_SDHI0_RX,
735 .addr = 0xffe4c000 + 0x30,
736 .dcr = HPB_DMAE_DCR_SMDL |
737 HPB_DMAE_DCR_SPDS_16BIT |
738 HPB_DMAE_DCR_DPDS_16BIT,
739 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
740 HPB_DMAE_ASYNCRSTR_ASRST22 |
741 HPB_DMAE_ASYNCRSTR_ASRST23,
742 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
743 HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
744 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
745 HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
747 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
752 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
753 HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
754 HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
757 static struct hpb_dmae_pdata dma_platform_data __initdata = {
758 .slaves = hpb_dmae_slaves,
759 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
760 .channels = hpb_dmae_channels,
761 .num_channels = ARRAY_SIZE(hpb_dmae_channels),
767 .num_hw_channels = 44,
770 static struct resource hpb_dmae_resources[] __initdata = {
771 /* Channel registers */
772 DEFINE_RES_MEM(0xffc08000, 0x1000),
773 /* Common registers */
774 DEFINE_RES_MEM(0xffc09000, 0x170),
775 /* Asynchronous reset registers */
776 DEFINE_RES_MEM(0xffc00300, 4),
777 /* Asynchronous mode registers */
778 DEFINE_RES_MEM(0xffc00400, 4),
779 /* IRQ for DMA channels */
780 DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
783 static void __init r8a7779_register_hpb_dmae(void)
785 platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
787 ARRAY_SIZE(hpb_dmae_resources),
789 sizeof(dma_platform_data));
792 static struct platform_device *r8a7779_devices_dt[] __initdata = {
803 static struct platform_device *r8a7779_standard_devices[] __initdata = {
811 void __init r8a7779_add_standard_devices(void)
813 #ifdef CONFIG_CACHE_L2X0
814 /* Early BRESP enable, Shared attribute override enable, 64K*16way */
815 l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
819 r8a7779_init_pm_domains();
821 platform_add_devices(r8a7779_devices_dt,
822 ARRAY_SIZE(r8a7779_devices_dt));
823 platform_add_devices(r8a7779_standard_devices,
824 ARRAY_SIZE(r8a7779_standard_devices));
825 r8a7779_register_hpb_dmae();
828 void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
830 platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
832 ARRAY_SIZE(ether_resources),
833 pdata, sizeof(*pdata));
836 void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
838 BUG_ON(id < 0 || id > 3);
840 vin_info_table[id]->data = pdata;
841 vin_info_table[id]->size_data = sizeof(*pdata);
843 platform_device_register_full(vin_info_table[id]);
846 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
847 void __init __weak r8a7779_register_twd(void) { }
849 void __init r8a7779_earlytimer_init(void)
851 r8a7779_clock_init();
852 r8a7779_register_twd();
853 shmobile_earlytimer_init();
856 void __init r8a7779_add_early_devices(void)
858 early_platform_add_devices(r8a7779_devices_dt,
859 ARRAY_SIZE(r8a7779_devices_dt));
861 /* Early serial console setup is not included here due to
862 * memory map collisions. The SCIF serial ports in r8a7779
863 * are difficult to entity map 1:1 due to collision with the
864 * virtual memory range used by the coherent DMA code on ARM.
866 * Anyone wanting to debug early can remove UPF_IOREMAP from
867 * the sh-sci serial console platform data, adjust mapbase
868 * to a static M:N virt:phys mapping that needs to be added to
869 * the mappings passed with iotable_init() above.
871 * Then add a call to shmobile_setup_console() from this function.
873 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
874 * command line in case of the marzen board.
878 static struct platform_device *r8a7779_late_devices[] __initdata = {
885 void __init r8a7779_init_late(void)
888 phy = usb_get_phy(USB_PHY_TYPE_USB2);
890 shmobile_init_late();
891 platform_add_devices(r8a7779_late_devices,
892 ARRAY_SIZE(r8a7779_late_devices));
896 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
898 return 0; /* always allow wakeup */
901 void __init r8a7779_init_irq_dt(void)
903 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
907 /* route all interrupts to ARM */
908 __raw_writel(0xffffffff, INT2NTSR0);
909 __raw_writel(0x3fffffff, INT2NTSR1);
911 /* unmask all known interrupts in INTCS2 */
912 __raw_writel(0xfffffff0, INT2SMSKCR0);
913 __raw_writel(0xfff7ffff, INT2SMSKCR1);
914 __raw_writel(0xfffbffdf, INT2SMSKCR2);
915 __raw_writel(0xbffffffc, INT2SMSKCR3);
916 __raw_writel(0x003fee3f, INT2SMSKCR4);
919 void __init r8a7779_init_delay(void)
921 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
924 void __init r8a7779_add_standard_devices_dt(void)
926 /* clocks are setup late during boot in the case of DT */
927 r8a7779_clock_init();
929 platform_add_devices(r8a7779_devices_dt,
930 ARRAY_SIZE(r8a7779_devices_dt));
931 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
934 static const char *r8a7779_compat_dt[] __initdata = {
939 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
940 .map_io = r8a7779_map_io,
941 .init_early = r8a7779_init_delay,
942 .nr_irqs = NR_IRQS_LEGACY,
943 .init_irq = r8a7779_init_irq_dt,
944 .init_machine = r8a7779_add_standard_devices_dt,
945 .init_late = r8a7779_init_late,
946 .dt_compat = r8a7779_compat_dt,
948 #endif /* CONFIG_USE_OF */