2 * sh7367 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/uio_driver.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_timer.h>
31 #include <mach/hardware.h>
32 #include <asm/mach-types.h>
33 #include <asm/mach/arch.h>
36 static struct plat_sci_port scif0_platform_data = {
37 .mapbase = 0xe6c40000,
38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE,
40 .scbrr_algo_id = SCBRR_ALGO_4,
42 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
43 evt2irq(0xc00), evt2irq(0xc00) },
46 static struct platform_device scif0_device = {
50 .platform_data = &scif0_platform_data,
55 static struct plat_sci_port scif1_platform_data = {
56 .mapbase = 0xe6c50000,
57 .flags = UPF_BOOT_AUTOCONF,
58 .scscr = SCSCR_RE | SCSCR_TE,
59 .scbrr_algo_id = SCBRR_ALGO_4,
61 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
62 evt2irq(0xc20), evt2irq(0xc20) },
65 static struct platform_device scif1_device = {
69 .platform_data = &scif1_platform_data,
74 static struct plat_sci_port scif2_platform_data = {
75 .mapbase = 0xe6c60000,
76 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE,
78 .scbrr_algo_id = SCBRR_ALGO_4,
80 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
81 evt2irq(0xc40), evt2irq(0xc40) },
84 static struct platform_device scif2_device = {
88 .platform_data = &scif2_platform_data,
93 static struct plat_sci_port scif3_platform_data = {
94 .mapbase = 0xe6c70000,
95 .flags = UPF_BOOT_AUTOCONF,
96 .scscr = SCSCR_RE | SCSCR_TE,
97 .scbrr_algo_id = SCBRR_ALGO_4,
99 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
100 evt2irq(0xc60), evt2irq(0xc60) },
103 static struct platform_device scif3_device = {
107 .platform_data = &scif3_platform_data,
112 static struct plat_sci_port scif4_platform_data = {
113 .mapbase = 0xe6c80000,
114 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_RE | SCSCR_TE,
116 .scbrr_algo_id = SCBRR_ALGO_4,
118 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
119 evt2irq(0xd20), evt2irq(0xd20) },
122 static struct platform_device scif4_device = {
126 .platform_data = &scif4_platform_data,
131 static struct plat_sci_port scif5_platform_data = {
132 .mapbase = 0xe6cb0000,
133 .flags = UPF_BOOT_AUTOCONF,
134 .scscr = SCSCR_RE | SCSCR_TE,
135 .scbrr_algo_id = SCBRR_ALGO_4,
137 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
138 evt2irq(0xd40), evt2irq(0xd40) },
141 static struct platform_device scif5_device = {
145 .platform_data = &scif5_platform_data,
150 static struct plat_sci_port scif6_platform_data = {
151 .mapbase = 0xe6c30000,
152 .flags = UPF_BOOT_AUTOCONF,
153 .scscr = SCSCR_RE | SCSCR_TE,
154 .scbrr_algo_id = SCBRR_ALGO_4,
156 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
157 evt2irq(0xd60), evt2irq(0xd60) },
160 static struct platform_device scif6_device = {
164 .platform_data = &scif6_platform_data,
168 static struct sh_timer_config cmt10_platform_data = {
170 .channel_offset = 0x10,
172 .clockevent_rating = 125,
173 .clocksource_rating = 125,
176 static struct resource cmt10_resources[] = {
181 .flags = IORESOURCE_MEM,
184 .start = evt2irq(0xb00), /* CMT1_CMT10 */
185 .flags = IORESOURCE_IRQ,
189 static struct platform_device cmt10_device = {
193 .platform_data = &cmt10_platform_data,
195 .resource = cmt10_resources,
196 .num_resources = ARRAY_SIZE(cmt10_resources),
200 static struct uio_info vpu_platform_data = {
203 .irq = intcs_evt2irq(0x980),
206 static struct resource vpu_resources[] = {
211 .flags = IORESOURCE_MEM,
215 static struct platform_device vpu_device = {
216 .name = "uio_pdrv_genirq",
219 .platform_data = &vpu_platform_data,
221 .resource = vpu_resources,
222 .num_resources = ARRAY_SIZE(vpu_resources),
226 static struct uio_info veu0_platform_data = {
229 .irq = intcs_evt2irq(0x700),
232 static struct resource veu0_resources[] = {
237 .flags = IORESOURCE_MEM,
241 static struct platform_device veu0_device = {
242 .name = "uio_pdrv_genirq",
245 .platform_data = &veu0_platform_data,
247 .resource = veu0_resources,
248 .num_resources = ARRAY_SIZE(veu0_resources),
252 static struct uio_info veu1_platform_data = {
255 .irq = intcs_evt2irq(0x720),
258 static struct resource veu1_resources[] = {
263 .flags = IORESOURCE_MEM,
267 static struct platform_device veu1_device = {
268 .name = "uio_pdrv_genirq",
271 .platform_data = &veu1_platform_data,
273 .resource = veu1_resources,
274 .num_resources = ARRAY_SIZE(veu1_resources),
278 static struct uio_info veu2_platform_data = {
281 .irq = intcs_evt2irq(0x740),
284 static struct resource veu2_resources[] = {
289 .flags = IORESOURCE_MEM,
293 static struct platform_device veu2_device = {
294 .name = "uio_pdrv_genirq",
297 .platform_data = &veu2_platform_data,
299 .resource = veu2_resources,
300 .num_resources = ARRAY_SIZE(veu2_resources),
304 static struct uio_info veu3_platform_data = {
307 .irq = intcs_evt2irq(0x760),
310 static struct resource veu3_resources[] = {
315 .flags = IORESOURCE_MEM,
319 static struct platform_device veu3_device = {
320 .name = "uio_pdrv_genirq",
323 .platform_data = &veu3_platform_data,
325 .resource = veu3_resources,
326 .num_resources = ARRAY_SIZE(veu3_resources),
330 static struct uio_info veu2h_platform_data = {
333 .irq = intcs_evt2irq(0x520),
336 static struct resource veu2h_resources[] = {
341 .flags = IORESOURCE_MEM,
345 static struct platform_device veu2h_device = {
346 .name = "uio_pdrv_genirq",
349 .platform_data = &veu2h_platform_data,
351 .resource = veu2h_resources,
352 .num_resources = ARRAY_SIZE(veu2h_resources),
356 static struct uio_info jpu_platform_data = {
359 .irq = intcs_evt2irq(0x560),
362 static struct resource jpu_resources[] = {
367 .flags = IORESOURCE_MEM,
371 static struct platform_device jpu_device = {
372 .name = "uio_pdrv_genirq",
375 .platform_data = &jpu_platform_data,
377 .resource = jpu_resources,
378 .num_resources = ARRAY_SIZE(jpu_resources),
382 static struct uio_info spu1_platform_data = {
385 .irq = evt2irq(0xfc0),
388 static struct resource spu1_resources[] = {
393 .flags = IORESOURCE_MEM,
397 static struct platform_device spu1_device = {
398 .name = "uio_pdrv_genirq",
401 .platform_data = &spu1_platform_data,
403 .resource = spu1_resources,
404 .num_resources = ARRAY_SIZE(spu1_resources),
407 static struct platform_device *sh7367_early_devices[] __initdata = {
418 static struct platform_device *sh7367_devices[] __initdata = {
429 void __init sh7367_add_standard_devices(void)
431 platform_add_devices(sh7367_early_devices,
432 ARRAY_SIZE(sh7367_early_devices));
434 platform_add_devices(sh7367_devices,
435 ARRAY_SIZE(sh7367_devices));
438 #define SYMSTPCR2 0xe6158048
439 #define SYMSTPCR2_CMT1 (1 << 29)
441 void __init sh7367_add_early_devices(void)
443 /* enable clock to CMT1 */
444 __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
446 early_platform_add_devices(sh7367_early_devices,
447 ARRAY_SIZE(sh7367_early_devices));