2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_domain.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/platform_data/sh_ipmmu.h>
37 #include <mach/dma-register.h>
38 #include <mach/hardware.h>
39 #include <mach/irqs.h>
40 #include <mach/sh7372.h>
41 #include <mach/common.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach-types.h>
44 #include <asm/mach/arch.h>
45 #include <asm/mach/time.h>
47 static struct map_desc sh7372_io_desc[] __initdata = {
48 /* create a 1:1 entity map for 0xe6xxxxxx
49 * used by CPGA, INTC and PFC.
52 .virtual = 0xe6000000,
53 .pfn = __phys_to_pfn(0xe6000000),
55 .type = MT_DEVICE_NONSHARED
59 void __init sh7372_map_io(void)
61 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
65 static struct resource sh7372_pfc_resources[] = {
69 .flags = IORESOURCE_MEM,
74 .flags = IORESOURCE_MEM,
78 static struct platform_device sh7372_pfc_device = {
81 .resource = sh7372_pfc_resources,
82 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
85 void __init sh7372_pinmux_init(void)
87 platform_device_register(&sh7372_pfc_device);
91 static struct plat_sci_port scif0_platform_data = {
92 .mapbase = 0xe6c40000,
93 .flags = UPF_BOOT_AUTOCONF,
94 .scscr = SCSCR_RE | SCSCR_TE,
95 .scbrr_algo_id = SCBRR_ALGO_4,
97 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
98 evt2irq(0x0c00), evt2irq(0x0c00) },
101 static struct platform_device scif0_device = {
105 .platform_data = &scif0_platform_data,
110 static struct plat_sci_port scif1_platform_data = {
111 .mapbase = 0xe6c50000,
112 .flags = UPF_BOOT_AUTOCONF,
113 .scscr = SCSCR_RE | SCSCR_TE,
114 .scbrr_algo_id = SCBRR_ALGO_4,
116 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
117 evt2irq(0x0c20), evt2irq(0x0c20) },
120 static struct platform_device scif1_device = {
124 .platform_data = &scif1_platform_data,
129 static struct plat_sci_port scif2_platform_data = {
130 .mapbase = 0xe6c60000,
131 .flags = UPF_BOOT_AUTOCONF,
132 .scscr = SCSCR_RE | SCSCR_TE,
133 .scbrr_algo_id = SCBRR_ALGO_4,
135 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
136 evt2irq(0x0c40), evt2irq(0x0c40) },
139 static struct platform_device scif2_device = {
143 .platform_data = &scif2_platform_data,
148 static struct plat_sci_port scif3_platform_data = {
149 .mapbase = 0xe6c70000,
150 .flags = UPF_BOOT_AUTOCONF,
151 .scscr = SCSCR_RE | SCSCR_TE,
152 .scbrr_algo_id = SCBRR_ALGO_4,
154 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
155 evt2irq(0x0c60), evt2irq(0x0c60) },
158 static struct platform_device scif3_device = {
162 .platform_data = &scif3_platform_data,
167 static struct plat_sci_port scif4_platform_data = {
168 .mapbase = 0xe6c80000,
169 .flags = UPF_BOOT_AUTOCONF,
170 .scscr = SCSCR_RE | SCSCR_TE,
171 .scbrr_algo_id = SCBRR_ALGO_4,
173 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
174 evt2irq(0x0d20), evt2irq(0x0d20) },
177 static struct platform_device scif4_device = {
181 .platform_data = &scif4_platform_data,
186 static struct plat_sci_port scif5_platform_data = {
187 .mapbase = 0xe6cb0000,
188 .flags = UPF_BOOT_AUTOCONF,
189 .scscr = SCSCR_RE | SCSCR_TE,
190 .scbrr_algo_id = SCBRR_ALGO_4,
192 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
193 evt2irq(0x0d40), evt2irq(0x0d40) },
196 static struct platform_device scif5_device = {
200 .platform_data = &scif5_platform_data,
205 static struct plat_sci_port scif6_platform_data = {
206 .mapbase = 0xe6c30000,
207 .flags = UPF_BOOT_AUTOCONF,
208 .scscr = SCSCR_RE | SCSCR_TE,
209 .scbrr_algo_id = SCBRR_ALGO_4,
211 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
212 evt2irq(0x0d60), evt2irq(0x0d60) },
215 static struct platform_device scif6_device = {
219 .platform_data = &scif6_platform_data,
224 static struct sh_timer_config cmt2_platform_data = {
226 .channel_offset = 0x40,
228 .clockevent_rating = 125,
229 .clocksource_rating = 125,
232 static struct resource cmt2_resources[] = {
237 .flags = IORESOURCE_MEM,
240 .start = evt2irq(0x0b80), /* CMT2 */
241 .flags = IORESOURCE_IRQ,
245 static struct platform_device cmt2_device = {
249 .platform_data = &cmt2_platform_data,
251 .resource = cmt2_resources,
252 .num_resources = ARRAY_SIZE(cmt2_resources),
256 static struct sh_timer_config tmu00_platform_data = {
258 .channel_offset = 0x4,
260 .clockevent_rating = 200,
263 static struct resource tmu00_resources[] = {
268 .flags = IORESOURCE_MEM,
271 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
272 .flags = IORESOURCE_IRQ,
276 static struct platform_device tmu00_device = {
280 .platform_data = &tmu00_platform_data,
282 .resource = tmu00_resources,
283 .num_resources = ARRAY_SIZE(tmu00_resources),
286 static struct sh_timer_config tmu01_platform_data = {
288 .channel_offset = 0x10,
290 .clocksource_rating = 200,
293 static struct resource tmu01_resources[] = {
298 .flags = IORESOURCE_MEM,
301 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
302 .flags = IORESOURCE_IRQ,
306 static struct platform_device tmu01_device = {
310 .platform_data = &tmu01_platform_data,
312 .resource = tmu01_resources,
313 .num_resources = ARRAY_SIZE(tmu01_resources),
317 static struct resource iic0_resources[] = {
321 .end = 0xFFF20425 - 1,
322 .flags = IORESOURCE_MEM,
325 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
326 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
327 .flags = IORESOURCE_IRQ,
331 static struct platform_device iic0_device = {
332 .name = "i2c-sh_mobile",
333 .id = 0, /* "i2c0" clock */
334 .num_resources = ARRAY_SIZE(iic0_resources),
335 .resource = iic0_resources,
338 static struct resource iic1_resources[] = {
342 .end = 0xE6C20425 - 1,
343 .flags = IORESOURCE_MEM,
346 .start = evt2irq(0x780), /* IIC1_ALI1 */
347 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
348 .flags = IORESOURCE_IRQ,
352 static struct platform_device iic1_device = {
353 .name = "i2c-sh_mobile",
354 .id = 1, /* "i2c1" clock */
355 .num_resources = ARRAY_SIZE(iic1_resources),
356 .resource = iic1_resources,
360 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
362 .slave_id = SHDMA_SLAVE_SCIF0_TX,
364 .chcr = CHCR_TX(XMIT_SZ_8BIT),
367 .slave_id = SHDMA_SLAVE_SCIF0_RX,
369 .chcr = CHCR_RX(XMIT_SZ_8BIT),
372 .slave_id = SHDMA_SLAVE_SCIF1_TX,
374 .chcr = CHCR_TX(XMIT_SZ_8BIT),
377 .slave_id = SHDMA_SLAVE_SCIF1_RX,
379 .chcr = CHCR_RX(XMIT_SZ_8BIT),
382 .slave_id = SHDMA_SLAVE_SCIF2_TX,
384 .chcr = CHCR_TX(XMIT_SZ_8BIT),
387 .slave_id = SHDMA_SLAVE_SCIF2_RX,
389 .chcr = CHCR_RX(XMIT_SZ_8BIT),
392 .slave_id = SHDMA_SLAVE_SCIF3_TX,
394 .chcr = CHCR_TX(XMIT_SZ_8BIT),
397 .slave_id = SHDMA_SLAVE_SCIF3_RX,
399 .chcr = CHCR_RX(XMIT_SZ_8BIT),
402 .slave_id = SHDMA_SLAVE_SCIF4_TX,
404 .chcr = CHCR_TX(XMIT_SZ_8BIT),
407 .slave_id = SHDMA_SLAVE_SCIF4_RX,
409 .chcr = CHCR_RX(XMIT_SZ_8BIT),
412 .slave_id = SHDMA_SLAVE_SCIF5_TX,
414 .chcr = CHCR_TX(XMIT_SZ_8BIT),
417 .slave_id = SHDMA_SLAVE_SCIF5_RX,
419 .chcr = CHCR_RX(XMIT_SZ_8BIT),
422 .slave_id = SHDMA_SLAVE_SCIF6_TX,
424 .chcr = CHCR_TX(XMIT_SZ_8BIT),
427 .slave_id = SHDMA_SLAVE_SCIF6_RX,
429 .chcr = CHCR_RX(XMIT_SZ_8BIT),
432 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
434 .chcr = CHCR_TX(XMIT_SZ_32BIT),
437 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
439 .chcr = CHCR_RX(XMIT_SZ_32BIT),
442 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
444 .chcr = CHCR_TX(XMIT_SZ_32BIT),
447 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
449 .chcr = CHCR_RX(XMIT_SZ_32BIT),
452 .slave_id = SHDMA_SLAVE_SDHI0_TX,
454 .chcr = CHCR_TX(XMIT_SZ_16BIT),
457 .slave_id = SHDMA_SLAVE_SDHI0_RX,
459 .chcr = CHCR_RX(XMIT_SZ_16BIT),
462 .slave_id = SHDMA_SLAVE_SDHI1_TX,
464 .chcr = CHCR_TX(XMIT_SZ_16BIT),
467 .slave_id = SHDMA_SLAVE_SDHI1_RX,
469 .chcr = CHCR_RX(XMIT_SZ_16BIT),
472 .slave_id = SHDMA_SLAVE_SDHI2_TX,
474 .chcr = CHCR_TX(XMIT_SZ_16BIT),
477 .slave_id = SHDMA_SLAVE_SDHI2_RX,
479 .chcr = CHCR_RX(XMIT_SZ_16BIT),
482 .slave_id = SHDMA_SLAVE_FSIA_TX,
484 .chcr = CHCR_TX(XMIT_SZ_32BIT),
487 .slave_id = SHDMA_SLAVE_FSIA_RX,
489 .chcr = CHCR_RX(XMIT_SZ_32BIT),
492 .slave_id = SHDMA_SLAVE_MMCIF_TX,
494 .chcr = CHCR_TX(XMIT_SZ_32BIT),
497 .slave_id = SHDMA_SLAVE_MMCIF_RX,
499 .chcr = CHCR_RX(XMIT_SZ_32BIT),
504 #define SH7372_CHCLR (0x220 - 0x20)
506 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
511 .chclr_offset = SH7372_CHCLR + 0,
516 .chclr_offset = SH7372_CHCLR + 0x10,
521 .chclr_offset = SH7372_CHCLR + 0x20,
526 .chclr_offset = SH7372_CHCLR + 0x30,
531 .chclr_offset = SH7372_CHCLR + 0x50,
536 .chclr_offset = SH7372_CHCLR + 0x60,
540 static struct sh_dmae_pdata dma_platform_data = {
541 .slave = sh7372_dmae_slaves,
542 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
543 .channel = sh7372_dmae_channels,
544 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
545 .ts_low_shift = TS_LOW_SHIFT,
546 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
547 .ts_high_shift = TS_HI_SHIFT,
548 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
549 .ts_shift = dma_ts_shift,
550 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
551 .dmaor_init = DMAOR_DME,
555 /* Resource order important! */
556 static struct resource sh7372_dmae0_resources[] = {
558 /* Channel registers and DMAOR */
561 .flags = IORESOURCE_MEM,
567 .flags = IORESOURCE_MEM,
571 .start = evt2irq(0x20c0),
572 .end = evt2irq(0x20c0),
573 .flags = IORESOURCE_IRQ,
576 /* IRQ for channels 0-5 */
577 .start = evt2irq(0x2000),
578 .end = evt2irq(0x20a0),
579 .flags = IORESOURCE_IRQ,
583 /* Resource order important! */
584 static struct resource sh7372_dmae1_resources[] = {
586 /* Channel registers and DMAOR */
589 .flags = IORESOURCE_MEM,
595 .flags = IORESOURCE_MEM,
599 .start = evt2irq(0x21c0),
600 .end = evt2irq(0x21c0),
601 .flags = IORESOURCE_IRQ,
604 /* IRQ for channels 0-5 */
605 .start = evt2irq(0x2100),
606 .end = evt2irq(0x21a0),
607 .flags = IORESOURCE_IRQ,
611 /* Resource order important! */
612 static struct resource sh7372_dmae2_resources[] = {
614 /* Channel registers and DMAOR */
617 .flags = IORESOURCE_MEM,
623 .flags = IORESOURCE_MEM,
627 .start = evt2irq(0x22c0),
628 .end = evt2irq(0x22c0),
629 .flags = IORESOURCE_IRQ,
632 /* IRQ for channels 0-5 */
633 .start = evt2irq(0x2200),
634 .end = evt2irq(0x22a0),
635 .flags = IORESOURCE_IRQ,
639 static struct platform_device dma0_device = {
640 .name = "sh-dma-engine",
642 .resource = sh7372_dmae0_resources,
643 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
645 .platform_data = &dma_platform_data,
649 static struct platform_device dma1_device = {
650 .name = "sh-dma-engine",
652 .resource = sh7372_dmae1_resources,
653 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
655 .platform_data = &dma_platform_data,
659 static struct platform_device dma2_device = {
660 .name = "sh-dma-engine",
662 .resource = sh7372_dmae2_resources,
663 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
665 .platform_data = &dma_platform_data,
672 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
681 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
683 .slave_id = SHDMA_SLAVE_USB0_TX,
684 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
686 .slave_id = SHDMA_SLAVE_USB0_RX,
687 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
691 static struct sh_dmae_pdata usb_dma0_platform_data = {
692 .slave = sh7372_usb_dmae0_slaves,
693 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
694 .channel = sh7372_usb_dmae_channels,
695 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
696 .ts_low_shift = USBTS_LOW_SHIFT,
697 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
698 .ts_high_shift = USBTS_HI_SHIFT,
699 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
700 .ts_shift = dma_usbts_shift,
701 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
702 .dmaor_init = DMAOR_DME,
704 .chcr_ie_bit = 1 << 5,
711 static struct resource sh7372_usb_dmae0_resources[] = {
713 /* Channel registers and DMAOR */
715 .end = 0xe68a0064 - 1,
716 .flags = IORESOURCE_MEM,
721 .end = 0xe68a0014 - 1,
722 .flags = IORESOURCE_MEM,
725 /* IRQ for channels */
726 .start = evt2irq(0x0a00),
727 .end = evt2irq(0x0a00),
728 .flags = IORESOURCE_IRQ,
732 static struct platform_device usb_dma0_device = {
733 .name = "sh-dma-engine",
735 .resource = sh7372_usb_dmae0_resources,
736 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
738 .platform_data = &usb_dma0_platform_data,
743 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
745 .slave_id = SHDMA_SLAVE_USB1_TX,
746 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
748 .slave_id = SHDMA_SLAVE_USB1_RX,
749 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
753 static struct sh_dmae_pdata usb_dma1_platform_data = {
754 .slave = sh7372_usb_dmae1_slaves,
755 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
756 .channel = sh7372_usb_dmae_channels,
757 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
758 .ts_low_shift = USBTS_LOW_SHIFT,
759 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
760 .ts_high_shift = USBTS_HI_SHIFT,
761 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
762 .ts_shift = dma_usbts_shift,
763 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
764 .dmaor_init = DMAOR_DME,
766 .chcr_ie_bit = 1 << 5,
773 static struct resource sh7372_usb_dmae1_resources[] = {
775 /* Channel registers and DMAOR */
777 .end = 0xe68c0064 - 1,
778 .flags = IORESOURCE_MEM,
783 .end = 0xe68c0014 - 1,
784 .flags = IORESOURCE_MEM,
787 /* IRQ for channels */
788 .start = evt2irq(0x1d00),
789 .end = evt2irq(0x1d00),
790 .flags = IORESOURCE_IRQ,
794 static struct platform_device usb_dma1_device = {
795 .name = "sh-dma-engine",
797 .resource = sh7372_usb_dmae1_resources,
798 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
800 .platform_data = &usb_dma1_platform_data,
805 static struct uio_info vpu_platform_data = {
808 .irq = intcs_evt2irq(0x980),
811 static struct resource vpu_resources[] = {
816 .flags = IORESOURCE_MEM,
820 static struct platform_device vpu_device = {
821 .name = "uio_pdrv_genirq",
824 .platform_data = &vpu_platform_data,
826 .resource = vpu_resources,
827 .num_resources = ARRAY_SIZE(vpu_resources),
831 static struct uio_info veu0_platform_data = {
834 .irq = intcs_evt2irq(0x700),
837 static struct resource veu0_resources[] = {
842 .flags = IORESOURCE_MEM,
846 static struct platform_device veu0_device = {
847 .name = "uio_pdrv_genirq",
850 .platform_data = &veu0_platform_data,
852 .resource = veu0_resources,
853 .num_resources = ARRAY_SIZE(veu0_resources),
857 static struct uio_info veu1_platform_data = {
860 .irq = intcs_evt2irq(0x720),
863 static struct resource veu1_resources[] = {
868 .flags = IORESOURCE_MEM,
872 static struct platform_device veu1_device = {
873 .name = "uio_pdrv_genirq",
876 .platform_data = &veu1_platform_data,
878 .resource = veu1_resources,
879 .num_resources = ARRAY_SIZE(veu1_resources),
883 static struct uio_info veu2_platform_data = {
886 .irq = intcs_evt2irq(0x740),
889 static struct resource veu2_resources[] = {
894 .flags = IORESOURCE_MEM,
898 static struct platform_device veu2_device = {
899 .name = "uio_pdrv_genirq",
902 .platform_data = &veu2_platform_data,
904 .resource = veu2_resources,
905 .num_resources = ARRAY_SIZE(veu2_resources),
909 static struct uio_info veu3_platform_data = {
912 .irq = intcs_evt2irq(0x760),
915 static struct resource veu3_resources[] = {
920 .flags = IORESOURCE_MEM,
924 static struct platform_device veu3_device = {
925 .name = "uio_pdrv_genirq",
928 .platform_data = &veu3_platform_data,
930 .resource = veu3_resources,
931 .num_resources = ARRAY_SIZE(veu3_resources),
935 static struct uio_info jpu_platform_data = {
938 .irq = intcs_evt2irq(0x560),
941 static struct resource jpu_resources[] = {
946 .flags = IORESOURCE_MEM,
950 static struct platform_device jpu_device = {
951 .name = "uio_pdrv_genirq",
954 .platform_data = &jpu_platform_data,
956 .resource = jpu_resources,
957 .num_resources = ARRAY_SIZE(jpu_resources),
961 static struct uio_info spu0_platform_data = {
964 .irq = evt2irq(0x1800),
967 static struct resource spu0_resources[] = {
972 .flags = IORESOURCE_MEM,
976 static struct platform_device spu0_device = {
977 .name = "uio_pdrv_genirq",
980 .platform_data = &spu0_platform_data,
982 .resource = spu0_resources,
983 .num_resources = ARRAY_SIZE(spu0_resources),
987 static struct uio_info spu1_platform_data = {
990 .irq = evt2irq(0x1820),
993 static struct resource spu1_resources[] = {
998 .flags = IORESOURCE_MEM,
1002 static struct platform_device spu1_device = {
1003 .name = "uio_pdrv_genirq",
1006 .platform_data = &spu1_platform_data,
1008 .resource = spu1_resources,
1009 .num_resources = ARRAY_SIZE(spu1_resources),
1012 /* IPMMUI (an IPMMU module for ICB/LMB) */
1013 static struct resource ipmmu_resources[] = {
1016 .start = 0xfe951000,
1018 .flags = IORESOURCE_MEM,
1022 static const char * const ipmmu_dev_names[] = {
1023 "sh_mobile_lcdc_fb.0",
1024 "sh_mobile_lcdc_fb.1",
1026 "uio_pdrv_genirq.0",
1027 "uio_pdrv_genirq.1",
1028 "uio_pdrv_genirq.2",
1029 "uio_pdrv_genirq.3",
1030 "uio_pdrv_genirq.4",
1031 "uio_pdrv_genirq.5",
1034 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
1035 .dev_names = ipmmu_dev_names,
1036 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
1039 static struct platform_device ipmmu_device = {
1043 .platform_data = &ipmmu_platform_data,
1045 .resource = ipmmu_resources,
1046 .num_resources = ARRAY_SIZE(ipmmu_resources),
1049 static struct platform_device *sh7372_early_devices[] __initdata = {
1063 static struct platform_device *sh7372_late_devices[] __initdata = {
1081 void __init sh7372_add_standard_devices(void)
1083 struct pm_domain_device domain_devices[] = {
1084 { "A3RV", &vpu_device, },
1085 { "A4MP", &spu0_device, },
1086 { "A4MP", &spu1_device, },
1087 { "A3SP", &scif0_device, },
1088 { "A3SP", &scif1_device, },
1089 { "A3SP", &scif2_device, },
1090 { "A3SP", &scif3_device, },
1091 { "A3SP", &scif4_device, },
1092 { "A3SP", &scif5_device, },
1093 { "A3SP", &scif6_device, },
1094 { "A3SP", &iic1_device, },
1095 { "A3SP", &dma0_device, },
1096 { "A3SP", &dma1_device, },
1097 { "A3SP", &dma2_device, },
1098 { "A3SP", &usb_dma0_device, },
1099 { "A3SP", &usb_dma1_device, },
1100 { "A4R", &iic0_device, },
1101 { "A4R", &veu0_device, },
1102 { "A4R", &veu1_device, },
1103 { "A4R", &veu2_device, },
1104 { "A4R", &veu3_device, },
1105 { "A4R", &jpu_device, },
1106 { "A4R", &tmu00_device, },
1107 { "A4R", &tmu01_device, },
1110 sh7372_init_pm_domains();
1112 platform_add_devices(sh7372_early_devices,
1113 ARRAY_SIZE(sh7372_early_devices));
1115 platform_add_devices(sh7372_late_devices,
1116 ARRAY_SIZE(sh7372_late_devices));
1118 rmobile_add_devices_to_domains(domain_devices,
1119 ARRAY_SIZE(domain_devices));
1122 void __init sh7372_earlytimer_init(void)
1124 sh7372_clock_init();
1125 shmobile_earlytimer_init();
1128 void __init sh7372_add_early_devices(void)
1130 early_platform_add_devices(sh7372_early_devices,
1131 ARRAY_SIZE(sh7372_early_devices));
1133 /* setup early console here as well */
1134 shmobile_setup_console();
1137 #ifdef CONFIG_USE_OF
1139 void __init sh7372_add_early_devices_dt(void)
1141 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1143 early_platform_add_devices(sh7372_early_devices,
1144 ARRAY_SIZE(sh7372_early_devices));
1146 /* setup early console here as well */
1147 shmobile_setup_console();
1150 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1154 void __init sh7372_add_standard_devices_dt(void)
1156 /* clocks are setup late during boot in the case of DT */
1157 sh7372_clock_init();
1159 platform_add_devices(sh7372_early_devices,
1160 ARRAY_SIZE(sh7372_early_devices));
1162 of_platform_populate(NULL, of_default_bus_match_table,
1163 sh7372_auxdata_lookup, NULL);
1166 static const char *sh7372_boards_compat_dt[] __initdata = {
1171 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1172 .map_io = sh7372_map_io,
1173 .init_early = sh7372_add_early_devices_dt,
1174 .nr_irqs = NR_IRQS_LEGACY,
1175 .init_irq = sh7372_init_irq,
1176 .handle_irq = shmobile_handle_irq_intc,
1177 .init_machine = sh7372_add_standard_devices_dt,
1178 .dt_compat = sh7372_boards_compat_dt,
1181 #endif /* CONFIG_USE_OF */