arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/uio_driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_intc.h>
  33 #include <linux/sh_timer.h>
  34 #include <linux/pm_domain.h>
  35 #include <linux/dma-mapping.h>
  36 #include <mach/dma-register.h>
  37 #include <mach/hardware.h>
  38 #include <mach/irqs.h>
  39 #include <mach/sh7372.h>
  40 #include <mach/common.h>
  41 #include <asm/mach/map.h>
  42 #include <asm/mach-types.h>
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/time.h>
  45
  46 static struct map_desc sh7372_io_desc[] __initdata = {
  47         /* create a 1:1 entity map for 0xe6xxxxxx
  48          * used by CPGA, INTC and PFC.
  49          */
  50         {
  51                 .virtual        = 0xe6000000,
  52                 .pfn            = __phys_to_pfn(0xe6000000),
  53                 .length         = 256 << 20,
  54                 .type           = MT_DEVICE_NONSHARED
  55         },
  56 };
  57
  58 void __init sh7372_map_io(void)
  59 {
  60         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  61
  62         /*
  63          * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
  64          * enough to allocate the frame buffer memory.
  65          */
  66         init_consistent_dma_size(12 << 20);
  67 }
  68
  69 /* SCIFA0 */
  70 static struct plat_sci_port scif0_platform_data = {
  71         .mapbase        = 0xe6c40000,
  72         .flags          = UPF_BOOT_AUTOCONF,
  73         .scscr          = SCSCR_RE | SCSCR_TE,
  74         .scbrr_algo_id  = SCBRR_ALGO_4,
  75         .type           = PORT_SCIFA,
  76         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  77                             evt2irq(0x0c00), evt2irq(0x0c00) },
  78 };
  79
  80 static struct platform_device scif0_device = {
  81         .name           = "sh-sci",
  82         .id             = 0,
  83         .dev            = {
  84                 .platform_data  = &scif0_platform_data,
  85         },
  86 };
  87
  88 /* SCIFA1 */
  89 static struct plat_sci_port scif1_platform_data = {
  90         .mapbase        = 0xe6c50000,
  91         .flags          = UPF_BOOT_AUTOCONF,
  92         .scscr          = SCSCR_RE | SCSCR_TE,
  93         .scbrr_algo_id  = SCBRR_ALGO_4,
  94         .type           = PORT_SCIFA,
  95         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  96                             evt2irq(0x0c20), evt2irq(0x0c20) },
  97 };
  98
  99 static struct platform_device scif1_device = {
 100         .name           = "sh-sci",
 101         .id             = 1,
 102         .dev            = {
 103                 .platform_data  = &scif1_platform_data,
 104         },
 105 };
 106
 107 /* SCIFA2 */
 108 static struct plat_sci_port scif2_platform_data = {
 109         .mapbase        = 0xe6c60000,
 110         .flags          = UPF_BOOT_AUTOCONF,
 111         .scscr          = SCSCR_RE | SCSCR_TE,
 112         .scbrr_algo_id  = SCBRR_ALGO_4,
 113         .type           = PORT_SCIFA,
 114         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
 115                             evt2irq(0x0c40), evt2irq(0x0c40) },
 116 };
 117
 118 static struct platform_device scif2_device = {
 119         .name           = "sh-sci",
 120         .id             = 2,
 121         .dev            = {
 122                 .platform_data  = &scif2_platform_data,
 123         },
 124 };
 125
 126 /* SCIFA3 */
 127 static struct plat_sci_port scif3_platform_data = {
 128         .mapbase        = 0xe6c70000,
 129         .flags          = UPF_BOOT_AUTOCONF,
 130         .scscr          = SCSCR_RE | SCSCR_TE,
 131         .scbrr_algo_id  = SCBRR_ALGO_4,
 132         .type           = PORT_SCIFA,
 133         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 134                             evt2irq(0x0c60), evt2irq(0x0c60) },
 135 };
 136
 137 static struct platform_device scif3_device = {
 138         .name           = "sh-sci",
 139         .id             = 3,
 140         .dev            = {
 141                 .platform_data  = &scif3_platform_data,
 142         },
 143 };
 144
 145 /* SCIFA4 */
 146 static struct plat_sci_port scif4_platform_data = {
 147         .mapbase        = 0xe6c80000,
 148         .flags          = UPF_BOOT_AUTOCONF,
 149         .scscr          = SCSCR_RE | SCSCR_TE,
 150         .scbrr_algo_id  = SCBRR_ALGO_4,
 151         .type           = PORT_SCIFA,
 152         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 153                             evt2irq(0x0d20), evt2irq(0x0d20) },
 154 };
 155
 156 static struct platform_device scif4_device = {
 157         .name           = "sh-sci",
 158         .id             = 4,
 159         .dev            = {
 160                 .platform_data  = &scif4_platform_data,
 161         },
 162 };
 163
 164 /* SCIFA5 */
 165 static struct plat_sci_port scif5_platform_data = {
 166         .mapbase        = 0xe6cb0000,
 167         .flags          = UPF_BOOT_AUTOCONF,
 168         .scscr          = SCSCR_RE | SCSCR_TE,
 169         .scbrr_algo_id  = SCBRR_ALGO_4,
 170         .type           = PORT_SCIFA,
 171         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 172                             evt2irq(0x0d40), evt2irq(0x0d40) },
 173 };
 174
 175 static struct platform_device scif5_device = {
 176         .name           = "sh-sci",
 177         .id             = 5,
 178         .dev            = {
 179                 .platform_data  = &scif5_platform_data,
 180         },
 181 };
 182
 183 /* SCIFB */
 184 static struct plat_sci_port scif6_platform_data = {
 185         .mapbase        = 0xe6c30000,
 186         .flags          = UPF_BOOT_AUTOCONF,
 187         .scscr          = SCSCR_RE | SCSCR_TE,
 188         .scbrr_algo_id  = SCBRR_ALGO_4,
 189         .type           = PORT_SCIFB,
 190         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 191                             evt2irq(0x0d60), evt2irq(0x0d60) },
 192 };
 193
 194 static struct platform_device scif6_device = {
 195         .name           = "sh-sci",
 196         .id             = 6,
 197         .dev            = {
 198                 .platform_data  = &scif6_platform_data,
 199         },
 200 };
 201
 202 /* CMT */
 203 static struct sh_timer_config cmt2_platform_data = {
 204         .name = "CMT2",
 205         .channel_offset = 0x40,
 206         .timer_bit = 5,
 207         .clockevent_rating = 125,
 208         .clocksource_rating = 125,
 209 };
 210
 211 static struct resource cmt2_resources[] = {
 212         [0] = {
 213                 .name   = "CMT2",
 214                 .start  = 0xe6130040,
 215                 .end    = 0xe613004b,
 216                 .flags  = IORESOURCE_MEM,
 217         },
 218         [1] = {
 219                 .start  = evt2irq(0x0b80), /* CMT2 */
 220                 .flags  = IORESOURCE_IRQ,
 221         },
 222 };
 223
 224 static struct platform_device cmt2_device = {
 225         .name           = "sh_cmt",
 226         .id             = 2,
 227         .dev = {
 228                 .platform_data  = &cmt2_platform_data,
 229         },
 230         .resource       = cmt2_resources,
 231         .num_resources  = ARRAY_SIZE(cmt2_resources),
 232 };
 233
 234 /* TMU */
 235 static struct sh_timer_config tmu00_platform_data = {
 236         .name = "TMU00",
 237         .channel_offset = 0x4,
 238         .timer_bit = 0,
 239         .clockevent_rating = 200,
 240 };
 241
 242 static struct resource tmu00_resources[] = {
 243         [0] = {
 244                 .name   = "TMU00",
 245                 .start  = 0xfff60008,
 246                 .end    = 0xfff60013,
 247                 .flags  = IORESOURCE_MEM,
 248         },
 249         [1] = {
 250                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 251                 .flags  = IORESOURCE_IRQ,
 252         },
 253 };
 254
 255 static struct platform_device tmu00_device = {
 256         .name           = "sh_tmu",
 257         .id             = 0,
 258         .dev = {
 259                 .platform_data  = &tmu00_platform_data,
 260         },
 261         .resource       = tmu00_resources,
 262         .num_resources  = ARRAY_SIZE(tmu00_resources),
 263 };
 264
 265 static struct sh_timer_config tmu01_platform_data = {
 266         .name = "TMU01",
 267         .channel_offset = 0x10,
 268         .timer_bit = 1,
 269         .clocksource_rating = 200,
 270 };
 271
 272 static struct resource tmu01_resources[] = {
 273         [0] = {
 274                 .name   = "TMU01",
 275                 .start  = 0xfff60014,
 276                 .end    = 0xfff6001f,
 277                 .flags  = IORESOURCE_MEM,
 278         },
 279         [1] = {
 280                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 281                 .flags  = IORESOURCE_IRQ,
 282         },
 283 };
 284
 285 static struct platform_device tmu01_device = {
 286         .name           = "sh_tmu",
 287         .id             = 1,
 288         .dev = {
 289                 .platform_data  = &tmu01_platform_data,
 290         },
 291         .resource       = tmu01_resources,
 292         .num_resources  = ARRAY_SIZE(tmu01_resources),
 293 };
 294
 295 /* I2C */
 296 static struct resource iic0_resources[] = {
 297         [0] = {
 298                 .name   = "IIC0",
 299                 .start  = 0xFFF20000,
 300                 .end    = 0xFFF20425 - 1,
 301                 .flags  = IORESOURCE_MEM,
 302         },
 303         [1] = {
 304                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 305                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 306                 .flags  = IORESOURCE_IRQ,
 307         },
 308 };
 309
 310 static struct platform_device iic0_device = {
 311         .name           = "i2c-sh_mobile",
 312         .id             = 0, /* "i2c0" clock */
 313         .num_resources  = ARRAY_SIZE(iic0_resources),
 314         .resource       = iic0_resources,
 315 };
 316
 317 static struct resource iic1_resources[] = {
 318         [0] = {
 319                 .name   = "IIC1",
 320                 .start  = 0xE6C20000,
 321                 .end    = 0xE6C20425 - 1,
 322                 .flags  = IORESOURCE_MEM,
 323         },
 324         [1] = {
 325                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 326                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 327                 .flags  = IORESOURCE_IRQ,
 328         },
 329 };
 330
 331 static struct platform_device iic1_device = {
 332         .name           = "i2c-sh_mobile",
 333         .id             = 1, /* "i2c1" clock */
 334         .num_resources  = ARRAY_SIZE(iic1_resources),
 335         .resource       = iic1_resources,
 336 };
 337
 338 /* DMA */
 339 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 340         {
 341                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 342                 .addr           = 0xe6c40020,
 343                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 344                 .mid_rid        = 0x21,
 345         }, {
 346                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 347                 .addr           = 0xe6c40024,
 348                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 349                 .mid_rid        = 0x22,
 350         }, {
 351                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 352                 .addr           = 0xe6c50020,
 353                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 354                 .mid_rid        = 0x25,
 355         }, {
 356                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 357                 .addr           = 0xe6c50024,
 358                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 359                 .mid_rid        = 0x26,
 360         }, {
 361                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 362                 .addr           = 0xe6c60020,
 363                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 364                 .mid_rid        = 0x29,
 365         }, {
 366                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 367                 .addr           = 0xe6c60024,
 368                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 369                 .mid_rid        = 0x2a,
 370         }, {
 371                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 372                 .addr           = 0xe6c70020,
 373                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 374                 .mid_rid        = 0x2d,
 375         }, {
 376                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 377                 .addr           = 0xe6c70024,
 378                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 379                 .mid_rid        = 0x2e,
 380         }, {
 381                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 382                 .addr           = 0xe6c80020,
 383                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 384                 .mid_rid        = 0x39,
 385         }, {
 386                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 387                 .addr           = 0xe6c80024,
 388                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 389                 .mid_rid        = 0x3a,
 390         }, {
 391                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 392                 .addr           = 0xe6cb0020,
 393                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 394                 .mid_rid        = 0x35,
 395         }, {
 396                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 397                 .addr           = 0xe6cb0024,
 398                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 399                 .mid_rid        = 0x36,
 400         }, {
 401                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 402                 .addr           = 0xe6c30040,
 403                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 404                 .mid_rid        = 0x3d,
 405         }, {
 406                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 407                 .addr           = 0xe6c30060,
 408                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 409                 .mid_rid        = 0x3e,
 410         }, {
 411                 .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
 412                 .addr           = 0xe6a30050,
 413                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 414                 .mid_rid        = 0x83,
 415         }, {
 416                 .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
 417                 .addr           = 0xe6a30050,
 418                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 419                 .mid_rid        = 0x83,
 420         }, {
 421                 .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
 422                 .addr           = 0xe6a30060,
 423                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 424                 .mid_rid        = 0x87,
 425         }, {
 426                 .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
 427                 .addr           = 0xe6a30060,
 428                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 429                 .mid_rid        = 0x87,
 430         }, {
 431                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 432                 .addr           = 0xe6850030,
 433                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 434                 .mid_rid        = 0xc1,
 435         }, {
 436                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 437                 .addr           = 0xe6850030,
 438                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 439                 .mid_rid        = 0xc2,
 440         }, {
 441                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 442                 .addr           = 0xe6860030,
 443                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 444                 .mid_rid        = 0xc9,
 445         }, {
 446                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 447                 .addr           = 0xe6860030,
 448                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 449                 .mid_rid        = 0xca,
 450         }, {
 451                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 452                 .addr           = 0xe6870030,
 453                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 454                 .mid_rid        = 0xcd,
 455         }, {
 456                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 457                 .addr           = 0xe6870030,
 458                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 459                 .mid_rid        = 0xce,
 460         }, {
 461                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 462                 .addr           = 0xfe1f0024,
 463                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 464                 .mid_rid        = 0xb1,
 465         }, {
 466                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 467                 .addr           = 0xfe1f0020,
 468                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 469                 .mid_rid        = 0xb2,
 470         }, {
 471                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 472                 .addr           = 0xe6bd0034,
 473                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 474                 .mid_rid        = 0xd1,
 475         }, {
 476                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 477                 .addr           = 0xe6bd0034,
 478                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 479                 .mid_rid        = 0xd2,
 480         },
 481 };
 482
 483 #define SH7372_CHCLR (0x220 - 0x20)
 484
 485 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 486         {
 487                 .offset = 0,
 488                 .dmars = 0,
 489                 .dmars_bit = 0,
 490                 .chclr_offset = SH7372_CHCLR + 0,
 491         }, {
 492                 .offset = 0x10,
 493                 .dmars = 0,
 494                 .dmars_bit = 8,
 495                 .chclr_offset = SH7372_CHCLR + 0x10,
 496         }, {
 497                 .offset = 0x20,
 498                 .dmars = 4,
 499                 .dmars_bit = 0,
 500                 .chclr_offset = SH7372_CHCLR + 0x20,
 501         }, {
 502                 .offset = 0x30,
 503                 .dmars = 4,
 504                 .dmars_bit = 8,
 505                 .chclr_offset = SH7372_CHCLR + 0x30,
 506         }, {
 507                 .offset = 0x50,
 508                 .dmars = 8,
 509                 .dmars_bit = 0,
 510                 .chclr_offset = SH7372_CHCLR + 0x50,
 511         }, {
 512                 .offset = 0x60,
 513                 .dmars = 8,
 514                 .dmars_bit = 8,
 515                 .chclr_offset = SH7372_CHCLR + 0x60,
 516         }
 517 };
 518
 519 static struct sh_dmae_pdata dma_platform_data = {
 520         .slave          = sh7372_dmae_slaves,
 521         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 522         .channel        = sh7372_dmae_channels,
 523         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 524         .ts_low_shift   = TS_LOW_SHIFT,
 525         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 526         .ts_high_shift  = TS_HI_SHIFT,
 527         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 528         .ts_shift       = dma_ts_shift,
 529         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 530         .dmaor_init     = DMAOR_DME,
 531         .chclr_present  = 1,
 532 };
 533
 534 /* Resource order important! */
 535 static struct resource sh7372_dmae0_resources[] = {
 536         {
 537                 /* Channel registers and DMAOR */
 538                 .start  = 0xfe008020,
 539                 .end    = 0xfe00828f,
 540                 .flags  = IORESOURCE_MEM,
 541         },
 542         {
 543                 /* DMARSx */
 544                 .start  = 0xfe009000,
 545                 .end    = 0xfe00900b,
 546                 .flags  = IORESOURCE_MEM,
 547         },
 548         {
 549                 .name   = "error_irq",
 550                 .start  = evt2irq(0x20c0),
 551                 .end    = evt2irq(0x20c0),
 552                 .flags  = IORESOURCE_IRQ,
 553         },
 554         {
 555                 /* IRQ for channels 0-5 */
 556                 .start  = evt2irq(0x2000),
 557                 .end    = evt2irq(0x20a0),
 558                 .flags  = IORESOURCE_IRQ,
 559         },
 560 };
 561
 562 /* Resource order important! */
 563 static struct resource sh7372_dmae1_resources[] = {
 564         {
 565                 /* Channel registers and DMAOR */
 566                 .start  = 0xfe018020,
 567                 .end    = 0xfe01828f,
 568                 .flags  = IORESOURCE_MEM,
 569         },
 570         {
 571                 /* DMARSx */
 572                 .start  = 0xfe019000,
 573                 .end    = 0xfe01900b,
 574                 .flags  = IORESOURCE_MEM,
 575         },
 576         {
 577                 .name   = "error_irq",
 578                 .start  = evt2irq(0x21c0),
 579                 .end    = evt2irq(0x21c0),
 580                 .flags  = IORESOURCE_IRQ,
 581         },
 582         {
 583                 /* IRQ for channels 0-5 */
 584                 .start  = evt2irq(0x2100),
 585                 .end    = evt2irq(0x21a0),
 586                 .flags  = IORESOURCE_IRQ,
 587         },
 588 };
 589
 590 /* Resource order important! */
 591 static struct resource sh7372_dmae2_resources[] = {
 592         {
 593                 /* Channel registers and DMAOR */
 594                 .start  = 0xfe028020,
 595                 .end    = 0xfe02828f,
 596                 .flags  = IORESOURCE_MEM,
 597         },
 598         {
 599                 /* DMARSx */
 600                 .start  = 0xfe029000,
 601                 .end    = 0xfe02900b,
 602                 .flags  = IORESOURCE_MEM,
 603         },
 604         {
 605                 .name   = "error_irq",
 606                 .start  = evt2irq(0x22c0),
 607                 .end    = evt2irq(0x22c0),
 608                 .flags  = IORESOURCE_IRQ,
 609         },
 610         {
 611                 /* IRQ for channels 0-5 */
 612                 .start  = evt2irq(0x2200),
 613                 .end    = evt2irq(0x22a0),
 614                 .flags  = IORESOURCE_IRQ,
 615         },
 616 };
 617
 618 static struct platform_device dma0_device = {
 619         .name           = "sh-dma-engine",
 620         .id             = 0,
 621         .resource       = sh7372_dmae0_resources,
 622         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 623         .dev            = {
 624                 .platform_data  = &dma_platform_data,
 625         },
 626 };
 627
 628 static struct platform_device dma1_device = {
 629         .name           = "sh-dma-engine",
 630         .id             = 1,
 631         .resource       = sh7372_dmae1_resources,
 632         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 633         .dev            = {
 634                 .platform_data  = &dma_platform_data,
 635         },
 636 };
 637
 638 static struct platform_device dma2_device = {
 639         .name           = "sh-dma-engine",
 640         .id             = 2,
 641         .resource       = sh7372_dmae2_resources,
 642         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 643         .dev            = {
 644                 .platform_data  = &dma_platform_data,
 645         },
 646 };
 647
 648 /*
 649  * USB-DMAC
 650  */
 651 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 652         {
 653                 .offset = 0,
 654         }, {
 655                 .offset = 0x20,
 656         },
 657 };
 658
 659 /* USB DMAC0 */
 660 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 661         {
 662                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 663                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 664         }, {
 665                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 666                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 667         },
 668 };
 669
 670 static struct sh_dmae_pdata usb_dma0_platform_data = {
 671         .slave          = sh7372_usb_dmae0_slaves,
 672         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 673         .channel        = sh7372_usb_dmae_channels,
 674         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 675         .ts_low_shift   = USBTS_LOW_SHIFT,
 676         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 677         .ts_high_shift  = USBTS_HI_SHIFT,
 678         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 679         .ts_shift       = dma_usbts_shift,
 680         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 681         .dmaor_init     = DMAOR_DME,
 682         .chcr_offset    = 0x14,
 683         .chcr_ie_bit    = 1 << 5,
 684         .dmaor_is_32bit = 1,
 685         .needs_tend_set = 1,
 686         .no_dmars       = 1,
 687         .slave_only     = 1,
 688 };
 689
 690 static struct resource sh7372_usb_dmae0_resources[] = {
 691         {
 692                 /* Channel registers and DMAOR */
 693                 .start  = 0xe68a0020,
 694                 .end    = 0xe68a0064 - 1,
 695                 .flags  = IORESOURCE_MEM,
 696         },
 697         {
 698                 /* VCR/SWR/DMICR */
 699                 .start  = 0xe68a0000,
 700                 .end    = 0xe68a0014 - 1,
 701                 .flags  = IORESOURCE_MEM,
 702         },
 703         {
 704                 /* IRQ for channels */
 705                 .start  = evt2irq(0x0a00),
 706                 .end    = evt2irq(0x0a00),
 707                 .flags  = IORESOURCE_IRQ,
 708         },
 709 };
 710
 711 static struct platform_device usb_dma0_device = {
 712         .name           = "sh-dma-engine",
 713         .id             = 3,
 714         .resource       = sh7372_usb_dmae0_resources,
 715         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 716         .dev            = {
 717                 .platform_data  = &usb_dma0_platform_data,
 718         },
 719 };
 720
 721 /* USB DMAC1 */
 722 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 723         {
 724                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 725                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 726         }, {
 727                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 728                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 729         },
 730 };
 731
 732 static struct sh_dmae_pdata usb_dma1_platform_data = {
 733         .slave          = sh7372_usb_dmae1_slaves,
 734         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 735         .channel        = sh7372_usb_dmae_channels,
 736         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 737         .ts_low_shift   = USBTS_LOW_SHIFT,
 738         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 739         .ts_high_shift  = USBTS_HI_SHIFT,
 740         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 741         .ts_shift       = dma_usbts_shift,
 742         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 743         .dmaor_init     = DMAOR_DME,
 744         .chcr_offset    = 0x14,
 745         .chcr_ie_bit    = 1 << 5,
 746         .dmaor_is_32bit = 1,
 747         .needs_tend_set = 1,
 748         .no_dmars       = 1,
 749         .slave_only     = 1,
 750 };
 751
 752 static struct resource sh7372_usb_dmae1_resources[] = {
 753         {
 754                 /* Channel registers and DMAOR */
 755                 .start  = 0xe68c0020,
 756                 .end    = 0xe68c0064 - 1,
 757                 .flags  = IORESOURCE_MEM,
 758         },
 759         {
 760                 /* VCR/SWR/DMICR */
 761                 .start  = 0xe68c0000,
 762                 .end    = 0xe68c0014 - 1,
 763                 .flags  = IORESOURCE_MEM,
 764         },
 765         {
 766                 /* IRQ for channels */
 767                 .start  = evt2irq(0x1d00),
 768                 .end    = evt2irq(0x1d00),
 769                 .flags  = IORESOURCE_IRQ,
 770         },
 771 };
 772
 773 static struct platform_device usb_dma1_device = {
 774         .name           = "sh-dma-engine",
 775         .id             = 4,
 776         .resource       = sh7372_usb_dmae1_resources,
 777         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 778         .dev            = {
 779                 .platform_data  = &usb_dma1_platform_data,
 780         },
 781 };
 782
 783 /* VPU */
 784 static struct uio_info vpu_platform_data = {
 785         .name = "VPU5HG",
 786         .version = "0",
 787         .irq = intcs_evt2irq(0x980),
 788 };
 789
 790 static struct resource vpu_resources[] = {
 791         [0] = {
 792                 .name   = "VPU",
 793                 .start  = 0xfe900000,
 794                 .end    = 0xfe900157,
 795                 .flags  = IORESOURCE_MEM,
 796         },
 797 };
 798
 799 static struct platform_device vpu_device = {
 800         .name           = "uio_pdrv_genirq",
 801         .id             = 0,
 802         .dev = {
 803                 .platform_data  = &vpu_platform_data,
 804         },
 805         .resource       = vpu_resources,
 806         .num_resources  = ARRAY_SIZE(vpu_resources),
 807 };
 808
 809 /* VEU0 */
 810 static struct uio_info veu0_platform_data = {
 811         .name = "VEU0",
 812         .version = "0",
 813         .irq = intcs_evt2irq(0x700),
 814 };
 815
 816 static struct resource veu0_resources[] = {
 817         [0] = {
 818                 .name   = "VEU0",
 819                 .start  = 0xfe920000,
 820                 .end    = 0xfe9200cb,
 821                 .flags  = IORESOURCE_MEM,
 822         },
 823 };
 824
 825 static struct platform_device veu0_device = {
 826         .name           = "uio_pdrv_genirq",
 827         .id             = 1,
 828         .dev = {
 829                 .platform_data  = &veu0_platform_data,
 830         },
 831         .resource       = veu0_resources,
 832         .num_resources  = ARRAY_SIZE(veu0_resources),
 833 };
 834
 835 /* VEU1 */
 836 static struct uio_info veu1_platform_data = {
 837         .name = "VEU1",
 838         .version = "0",
 839         .irq = intcs_evt2irq(0x720),
 840 };
 841
 842 static struct resource veu1_resources[] = {
 843         [0] = {
 844                 .name   = "VEU1",
 845                 .start  = 0xfe924000,
 846                 .end    = 0xfe9240cb,
 847                 .flags  = IORESOURCE_MEM,
 848         },
 849 };
 850
 851 static struct platform_device veu1_device = {
 852         .name           = "uio_pdrv_genirq",
 853         .id             = 2,
 854         .dev = {
 855                 .platform_data  = &veu1_platform_data,
 856         },
 857         .resource       = veu1_resources,
 858         .num_resources  = ARRAY_SIZE(veu1_resources),
 859 };
 860
 861 /* VEU2 */
 862 static struct uio_info veu2_platform_data = {
 863         .name = "VEU2",
 864         .version = "0",
 865         .irq = intcs_evt2irq(0x740),
 866 };
 867
 868 static struct resource veu2_resources[] = {
 869         [0] = {
 870                 .name   = "VEU2",
 871                 .start  = 0xfe928000,
 872                 .end    = 0xfe928307,
 873                 .flags  = IORESOURCE_MEM,
 874         },
 875 };
 876
 877 static struct platform_device veu2_device = {
 878         .name           = "uio_pdrv_genirq",
 879         .id             = 3,
 880         .dev = {
 881                 .platform_data  = &veu2_platform_data,
 882         },
 883         .resource       = veu2_resources,
 884         .num_resources  = ARRAY_SIZE(veu2_resources),
 885 };
 886
 887 /* VEU3 */
 888 static struct uio_info veu3_platform_data = {
 889         .name = "VEU3",
 890         .version = "0",
 891         .irq = intcs_evt2irq(0x760),
 892 };
 893
 894 static struct resource veu3_resources[] = {
 895         [0] = {
 896                 .name   = "VEU3",
 897                 .start  = 0xfe92c000,
 898                 .end    = 0xfe92c307,
 899                 .flags  = IORESOURCE_MEM,
 900         },
 901 };
 902
 903 static struct platform_device veu3_device = {
 904         .name           = "uio_pdrv_genirq",
 905         .id             = 4,
 906         .dev = {
 907                 .platform_data  = &veu3_platform_data,
 908         },
 909         .resource       = veu3_resources,
 910         .num_resources  = ARRAY_SIZE(veu3_resources),
 911 };
 912
 913 /* JPU */
 914 static struct uio_info jpu_platform_data = {
 915         .name = "JPU",
 916         .version = "0",
 917         .irq = intcs_evt2irq(0x560),
 918 };
 919
 920 static struct resource jpu_resources[] = {
 921         [0] = {
 922                 .name   = "JPU",
 923                 .start  = 0xfe980000,
 924                 .end    = 0xfe9902d3,
 925                 .flags  = IORESOURCE_MEM,
 926         },
 927 };
 928
 929 static struct platform_device jpu_device = {
 930         .name           = "uio_pdrv_genirq",
 931         .id             = 5,
 932         .dev = {
 933                 .platform_data  = &jpu_platform_data,
 934         },
 935         .resource       = jpu_resources,
 936         .num_resources  = ARRAY_SIZE(jpu_resources),
 937 };
 938
 939 /* SPU2DSP0 */
 940 static struct uio_info spu0_platform_data = {
 941         .name = "SPU2DSP0",
 942         .version = "0",
 943         .irq = evt2irq(0x1800),
 944 };
 945
 946 static struct resource spu0_resources[] = {
 947         [0] = {
 948                 .name   = "SPU2DSP0",
 949                 .start  = 0xfe200000,
 950                 .end    = 0xfe2fffff,
 951                 .flags  = IORESOURCE_MEM,
 952         },
 953 };
 954
 955 static struct platform_device spu0_device = {
 956         .name           = "uio_pdrv_genirq",
 957         .id             = 6,
 958         .dev = {
 959                 .platform_data  = &spu0_platform_data,
 960         },
 961         .resource       = spu0_resources,
 962         .num_resources  = ARRAY_SIZE(spu0_resources),
 963 };
 964
 965 /* SPU2DSP1 */
 966 static struct uio_info spu1_platform_data = {
 967         .name = "SPU2DSP1",
 968         .version = "0",
 969         .irq = evt2irq(0x1820),
 970 };
 971
 972 static struct resource spu1_resources[] = {
 973         [0] = {
 974                 .name   = "SPU2DSP1",
 975                 .start  = 0xfe300000,
 976                 .end    = 0xfe3fffff,
 977                 .flags  = IORESOURCE_MEM,
 978         },
 979 };
 980
 981 static struct platform_device spu1_device = {
 982         .name           = "uio_pdrv_genirq",
 983         .id             = 7,
 984         .dev = {
 985                 .platform_data  = &spu1_platform_data,
 986         },
 987         .resource       = spu1_resources,
 988         .num_resources  = ARRAY_SIZE(spu1_resources),
 989 };
 990
 991 static struct platform_device *sh7372_early_devices[] __initdata = {
 992         &scif0_device,
 993         &scif1_device,
 994         &scif2_device,
 995         &scif3_device,
 996         &scif4_device,
 997         &scif5_device,
 998         &scif6_device,
 999         &cmt2_device,
1000         &tmu00_device,
1001         &tmu01_device,
1002 };
1003
1004 static struct platform_device *sh7372_late_devices[] __initdata = {
1005         &iic0_device,
1006         &iic1_device,
1007         &dma0_device,
1008         &dma1_device,
1009         &dma2_device,
1010         &usb_dma0_device,
1011         &usb_dma1_device,
1012         &vpu_device,
1013         &veu0_device,
1014         &veu1_device,
1015         &veu2_device,
1016         &veu3_device,
1017         &jpu_device,
1018         &spu0_device,
1019         &spu1_device,
1020 };
1021
1022 void __init sh7372_add_standard_devices(void)
1023 {
1024         struct pm_domain_device domain_devices[] = {
1025                 { "A3RV", &vpu_device, },
1026                 { "A4MP", &spu0_device, },
1027                 { "A4MP", &spu1_device, },
1028                 { "A3SP", &scif0_device, },
1029                 { "A3SP", &scif1_device, },
1030                 { "A3SP", &scif2_device, },
1031                 { "A3SP", &scif3_device, },
1032                 { "A3SP", &scif4_device, },
1033                 { "A3SP", &scif5_device, },
1034                 { "A3SP", &scif6_device, },
1035                 { "A3SP", &iic1_device, },
1036                 { "A3SP", &dma0_device, },
1037                 { "A3SP", &dma1_device, },
1038                 { "A3SP", &dma2_device, },
1039                 { "A3SP", &usb_dma0_device, },
1040                 { "A3SP", &usb_dma1_device, },
1041                 { "A4R", &iic0_device, },
1042                 { "A4R", &veu0_device, },
1043                 { "A4R", &veu1_device, },
1044                 { "A4R", &veu2_device, },
1045                 { "A4R", &veu3_device, },
1046                 { "A4R", &jpu_device, },
1047                 { "A4R", &tmu00_device, },
1048                 { "A4R", &tmu01_device, },
1049         };
1050
1051         sh7372_init_pm_domains();
1052
1053         platform_add_devices(sh7372_early_devices,
1054                             ARRAY_SIZE(sh7372_early_devices));
1055
1056         platform_add_devices(sh7372_late_devices,
1057                             ARRAY_SIZE(sh7372_late_devices));
1058
1059         rmobile_add_devices_to_domains(domain_devices,
1060                                        ARRAY_SIZE(domain_devices));
1061 }
1062
1063 static void __init sh7372_earlytimer_init(void)
1064 {
1065         sh7372_clock_init();
1066         shmobile_earlytimer_init();
1067 }
1068
1069 void __init sh7372_add_early_devices(void)
1070 {
1071         early_platform_add_devices(sh7372_early_devices,
1072                                    ARRAY_SIZE(sh7372_early_devices));
1073
1074         /* setup early console here as well */
1075         shmobile_setup_console();
1076
1077         /* override timer setup with soc-specific code */
1078         shmobile_timer.init = sh7372_earlytimer_init;
1079 }
1080
1081 #ifdef CONFIG_USE_OF
1082
1083 void __init sh7372_add_early_devices_dt(void)
1084 {
1085         shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1086
1087         early_platform_add_devices(sh7372_early_devices,
1088                                    ARRAY_SIZE(sh7372_early_devices));
1089
1090         /* setup early console here as well */
1091         shmobile_setup_console();
1092 }
1093
1094 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1095         { }
1096 };
1097
1098 void __init sh7372_add_standard_devices_dt(void)
1099 {
1100         /* clocks are setup late during boot in the case of DT */
1101         sh7372_clock_init();
1102
1103         platform_add_devices(sh7372_early_devices,
1104                             ARRAY_SIZE(sh7372_early_devices));
1105
1106         of_platform_populate(NULL, of_default_bus_match_table,
1107                              sh7372_auxdata_lookup, NULL);
1108 }
1109
1110 static const char *sh7372_boards_compat_dt[] __initdata = {
1111         "renesas,sh7372",
1112         NULL,
1113 };
1114
1115 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1116         .map_io         = sh7372_map_io,
1117         .init_early     = sh7372_add_early_devices_dt,
1118         .nr_irqs        = NR_IRQS_LEGACY,
1119         .init_irq       = sh7372_init_irq,
1120         .handle_irq     = shmobile_handle_irq_intc,
1121         .init_machine   = sh7372_add_standard_devices_dt,
1122         .timer          = &shmobile_timer,
1123         .dt_compat      = sh7372_boards_compat_dt,
1124 MACHINE_END
1125
1126 #endif /* CONFIG_USE_OF */