2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_domain.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/platform_data/sh_ipmmu.h>
37 #include <mach/dma-register.h>
38 #include <mach/irqs.h>
39 #include <mach/sh7372.h>
40 #include <mach/common.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/time.h>
46 static struct map_desc sh7372_io_desc[] __initdata = {
47 /* create a 1:1 entity map for 0xe6xxxxxx
48 * used by CPGA, INTC and PFC.
51 .virtual = 0xe6000000,
52 .pfn = __phys_to_pfn(0xe6000000),
54 .type = MT_DEVICE_NONSHARED
58 void __init sh7372_map_io(void)
60 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
64 static struct resource sh7372_pfc_resources[] = {
68 .flags = IORESOURCE_MEM,
73 .flags = IORESOURCE_MEM,
77 static struct platform_device sh7372_pfc_device = {
80 .resource = sh7372_pfc_resources,
81 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
84 void __init sh7372_pinmux_init(void)
86 platform_device_register(&sh7372_pfc_device);
90 #define SH7372_SCIF(scif_type, index, baseaddr, irq) \
91 static struct plat_sci_port scif##index##_platform_data = { \
93 .flags = UPF_BOOT_AUTOCONF, \
94 .scscr = SCSCR_RE | SCSCR_TE, \
97 static struct resource scif##index##_resources[] = { \
98 DEFINE_RES_MEM(baseaddr, 0x100), \
99 DEFINE_RES_IRQ(irq), \
102 static struct platform_device scif##index##_device = { \
105 .resource = scif##index##_resources, \
106 .num_resources = ARRAY_SIZE(scif##index##_resources), \
108 .platform_data = &scif##index##_platform_data, \
112 SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
113 SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
114 SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
115 SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
116 SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
117 SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
118 SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
121 static struct sh_timer_config cmt2_platform_data = {
123 .channel_offset = 0x40,
125 .clockevent_rating = 125,
126 .clocksource_rating = 125,
129 static struct resource cmt2_resources[] = {
134 .flags = IORESOURCE_MEM,
137 .start = evt2irq(0x0b80), /* CMT2 */
138 .flags = IORESOURCE_IRQ,
142 static struct platform_device cmt2_device = {
146 .platform_data = &cmt2_platform_data,
148 .resource = cmt2_resources,
149 .num_resources = ARRAY_SIZE(cmt2_resources),
153 static struct sh_timer_config tmu00_platform_data = {
155 .channel_offset = 0x4,
157 .clockevent_rating = 200,
160 static struct resource tmu00_resources[] = {
165 .flags = IORESOURCE_MEM,
168 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
169 .flags = IORESOURCE_IRQ,
173 static struct platform_device tmu00_device = {
177 .platform_data = &tmu00_platform_data,
179 .resource = tmu00_resources,
180 .num_resources = ARRAY_SIZE(tmu00_resources),
183 static struct sh_timer_config tmu01_platform_data = {
185 .channel_offset = 0x10,
187 .clocksource_rating = 200,
190 static struct resource tmu01_resources[] = {
195 .flags = IORESOURCE_MEM,
198 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
199 .flags = IORESOURCE_IRQ,
203 static struct platform_device tmu01_device = {
207 .platform_data = &tmu01_platform_data,
209 .resource = tmu01_resources,
210 .num_resources = ARRAY_SIZE(tmu01_resources),
214 static struct resource iic0_resources[] = {
218 .end = 0xFFF20425 - 1,
219 .flags = IORESOURCE_MEM,
222 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
223 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
224 .flags = IORESOURCE_IRQ,
228 static struct platform_device iic0_device = {
229 .name = "i2c-sh_mobile",
230 .id = 0, /* "i2c0" clock */
231 .num_resources = ARRAY_SIZE(iic0_resources),
232 .resource = iic0_resources,
235 static struct resource iic1_resources[] = {
239 .end = 0xE6C20425 - 1,
240 .flags = IORESOURCE_MEM,
243 .start = evt2irq(0x780), /* IIC1_ALI1 */
244 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
245 .flags = IORESOURCE_IRQ,
249 static struct platform_device iic1_device = {
250 .name = "i2c-sh_mobile",
251 .id = 1, /* "i2c1" clock */
252 .num_resources = ARRAY_SIZE(iic1_resources),
253 .resource = iic1_resources,
257 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
259 .slave_id = SHDMA_SLAVE_SCIF0_TX,
261 .chcr = CHCR_TX(XMIT_SZ_8BIT),
264 .slave_id = SHDMA_SLAVE_SCIF0_RX,
266 .chcr = CHCR_RX(XMIT_SZ_8BIT),
269 .slave_id = SHDMA_SLAVE_SCIF1_TX,
271 .chcr = CHCR_TX(XMIT_SZ_8BIT),
274 .slave_id = SHDMA_SLAVE_SCIF1_RX,
276 .chcr = CHCR_RX(XMIT_SZ_8BIT),
279 .slave_id = SHDMA_SLAVE_SCIF2_TX,
281 .chcr = CHCR_TX(XMIT_SZ_8BIT),
284 .slave_id = SHDMA_SLAVE_SCIF2_RX,
286 .chcr = CHCR_RX(XMIT_SZ_8BIT),
289 .slave_id = SHDMA_SLAVE_SCIF3_TX,
291 .chcr = CHCR_TX(XMIT_SZ_8BIT),
294 .slave_id = SHDMA_SLAVE_SCIF3_RX,
296 .chcr = CHCR_RX(XMIT_SZ_8BIT),
299 .slave_id = SHDMA_SLAVE_SCIF4_TX,
301 .chcr = CHCR_TX(XMIT_SZ_8BIT),
304 .slave_id = SHDMA_SLAVE_SCIF4_RX,
306 .chcr = CHCR_RX(XMIT_SZ_8BIT),
309 .slave_id = SHDMA_SLAVE_SCIF5_TX,
311 .chcr = CHCR_TX(XMIT_SZ_8BIT),
314 .slave_id = SHDMA_SLAVE_SCIF5_RX,
316 .chcr = CHCR_RX(XMIT_SZ_8BIT),
319 .slave_id = SHDMA_SLAVE_SCIF6_TX,
321 .chcr = CHCR_TX(XMIT_SZ_8BIT),
324 .slave_id = SHDMA_SLAVE_SCIF6_RX,
326 .chcr = CHCR_RX(XMIT_SZ_8BIT),
329 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
331 .chcr = CHCR_TX(XMIT_SZ_32BIT),
334 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
336 .chcr = CHCR_RX(XMIT_SZ_32BIT),
339 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
341 .chcr = CHCR_TX(XMIT_SZ_32BIT),
344 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
346 .chcr = CHCR_RX(XMIT_SZ_32BIT),
349 .slave_id = SHDMA_SLAVE_SDHI0_TX,
351 .chcr = CHCR_TX(XMIT_SZ_16BIT),
354 .slave_id = SHDMA_SLAVE_SDHI0_RX,
356 .chcr = CHCR_RX(XMIT_SZ_16BIT),
359 .slave_id = SHDMA_SLAVE_SDHI1_TX,
361 .chcr = CHCR_TX(XMIT_SZ_16BIT),
364 .slave_id = SHDMA_SLAVE_SDHI1_RX,
366 .chcr = CHCR_RX(XMIT_SZ_16BIT),
369 .slave_id = SHDMA_SLAVE_SDHI2_TX,
371 .chcr = CHCR_TX(XMIT_SZ_16BIT),
374 .slave_id = SHDMA_SLAVE_SDHI2_RX,
376 .chcr = CHCR_RX(XMIT_SZ_16BIT),
379 .slave_id = SHDMA_SLAVE_FSIA_TX,
381 .chcr = CHCR_TX(XMIT_SZ_32BIT),
384 .slave_id = SHDMA_SLAVE_FSIA_RX,
386 .chcr = CHCR_RX(XMIT_SZ_32BIT),
389 .slave_id = SHDMA_SLAVE_MMCIF_TX,
391 .chcr = CHCR_TX(XMIT_SZ_32BIT),
394 .slave_id = SHDMA_SLAVE_MMCIF_RX,
396 .chcr = CHCR_RX(XMIT_SZ_32BIT),
401 #define SH7372_CHCLR (0x220 - 0x20)
403 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
408 .chclr_offset = SH7372_CHCLR + 0,
413 .chclr_offset = SH7372_CHCLR + 0x10,
418 .chclr_offset = SH7372_CHCLR + 0x20,
423 .chclr_offset = SH7372_CHCLR + 0x30,
428 .chclr_offset = SH7372_CHCLR + 0x50,
433 .chclr_offset = SH7372_CHCLR + 0x60,
437 static struct sh_dmae_pdata dma_platform_data = {
438 .slave = sh7372_dmae_slaves,
439 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
440 .channel = sh7372_dmae_channels,
441 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
442 .ts_low_shift = TS_LOW_SHIFT,
443 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
444 .ts_high_shift = TS_HI_SHIFT,
445 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
446 .ts_shift = dma_ts_shift,
447 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
448 .dmaor_init = DMAOR_DME,
452 /* Resource order important! */
453 static struct resource sh7372_dmae0_resources[] = {
455 /* Channel registers and DMAOR */
458 .flags = IORESOURCE_MEM,
464 .flags = IORESOURCE_MEM,
468 .start = evt2irq(0x20c0),
469 .end = evt2irq(0x20c0),
470 .flags = IORESOURCE_IRQ,
473 /* IRQ for channels 0-5 */
474 .start = evt2irq(0x2000),
475 .end = evt2irq(0x20a0),
476 .flags = IORESOURCE_IRQ,
480 /* Resource order important! */
481 static struct resource sh7372_dmae1_resources[] = {
483 /* Channel registers and DMAOR */
486 .flags = IORESOURCE_MEM,
492 .flags = IORESOURCE_MEM,
496 .start = evt2irq(0x21c0),
497 .end = evt2irq(0x21c0),
498 .flags = IORESOURCE_IRQ,
501 /* IRQ for channels 0-5 */
502 .start = evt2irq(0x2100),
503 .end = evt2irq(0x21a0),
504 .flags = IORESOURCE_IRQ,
508 /* Resource order important! */
509 static struct resource sh7372_dmae2_resources[] = {
511 /* Channel registers and DMAOR */
514 .flags = IORESOURCE_MEM,
520 .flags = IORESOURCE_MEM,
524 .start = evt2irq(0x22c0),
525 .end = evt2irq(0x22c0),
526 .flags = IORESOURCE_IRQ,
529 /* IRQ for channels 0-5 */
530 .start = evt2irq(0x2200),
531 .end = evt2irq(0x22a0),
532 .flags = IORESOURCE_IRQ,
536 static struct platform_device dma0_device = {
537 .name = "sh-dma-engine",
539 .resource = sh7372_dmae0_resources,
540 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
542 .platform_data = &dma_platform_data,
546 static struct platform_device dma1_device = {
547 .name = "sh-dma-engine",
549 .resource = sh7372_dmae1_resources,
550 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
552 .platform_data = &dma_platform_data,
556 static struct platform_device dma2_device = {
557 .name = "sh-dma-engine",
559 .resource = sh7372_dmae2_resources,
560 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
562 .platform_data = &dma_platform_data,
569 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
578 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
580 .slave_id = SHDMA_SLAVE_USB0_TX,
581 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
583 .slave_id = SHDMA_SLAVE_USB0_RX,
584 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
588 static struct sh_dmae_pdata usb_dma0_platform_data = {
589 .slave = sh7372_usb_dmae0_slaves,
590 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
591 .channel = sh7372_usb_dmae_channels,
592 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
593 .ts_low_shift = USBTS_LOW_SHIFT,
594 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
595 .ts_high_shift = USBTS_HI_SHIFT,
596 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
597 .ts_shift = dma_usbts_shift,
598 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
599 .dmaor_init = DMAOR_DME,
601 .chcr_ie_bit = 1 << 5,
608 static struct resource sh7372_usb_dmae0_resources[] = {
610 /* Channel registers and DMAOR */
612 .end = 0xe68a0064 - 1,
613 .flags = IORESOURCE_MEM,
618 .end = 0xe68a0014 - 1,
619 .flags = IORESOURCE_MEM,
622 /* IRQ for channels */
623 .start = evt2irq(0x0a00),
624 .end = evt2irq(0x0a00),
625 .flags = IORESOURCE_IRQ,
629 static struct platform_device usb_dma0_device = {
630 .name = "sh-dma-engine",
632 .resource = sh7372_usb_dmae0_resources,
633 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
635 .platform_data = &usb_dma0_platform_data,
640 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
642 .slave_id = SHDMA_SLAVE_USB1_TX,
643 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
645 .slave_id = SHDMA_SLAVE_USB1_RX,
646 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
650 static struct sh_dmae_pdata usb_dma1_platform_data = {
651 .slave = sh7372_usb_dmae1_slaves,
652 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
653 .channel = sh7372_usb_dmae_channels,
654 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
655 .ts_low_shift = USBTS_LOW_SHIFT,
656 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
657 .ts_high_shift = USBTS_HI_SHIFT,
658 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
659 .ts_shift = dma_usbts_shift,
660 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
661 .dmaor_init = DMAOR_DME,
663 .chcr_ie_bit = 1 << 5,
670 static struct resource sh7372_usb_dmae1_resources[] = {
672 /* Channel registers and DMAOR */
674 .end = 0xe68c0064 - 1,
675 .flags = IORESOURCE_MEM,
680 .end = 0xe68c0014 - 1,
681 .flags = IORESOURCE_MEM,
684 /* IRQ for channels */
685 .start = evt2irq(0x1d00),
686 .end = evt2irq(0x1d00),
687 .flags = IORESOURCE_IRQ,
691 static struct platform_device usb_dma1_device = {
692 .name = "sh-dma-engine",
694 .resource = sh7372_usb_dmae1_resources,
695 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
697 .platform_data = &usb_dma1_platform_data,
702 static struct uio_info vpu_platform_data = {
705 .irq = intcs_evt2irq(0x980),
708 static struct resource vpu_resources[] = {
713 .flags = IORESOURCE_MEM,
717 static struct platform_device vpu_device = {
718 .name = "uio_pdrv_genirq",
721 .platform_data = &vpu_platform_data,
723 .resource = vpu_resources,
724 .num_resources = ARRAY_SIZE(vpu_resources),
728 static struct uio_info veu0_platform_data = {
731 .irq = intcs_evt2irq(0x700),
734 static struct resource veu0_resources[] = {
739 .flags = IORESOURCE_MEM,
743 static struct platform_device veu0_device = {
744 .name = "uio_pdrv_genirq",
747 .platform_data = &veu0_platform_data,
749 .resource = veu0_resources,
750 .num_resources = ARRAY_SIZE(veu0_resources),
754 static struct uio_info veu1_platform_data = {
757 .irq = intcs_evt2irq(0x720),
760 static struct resource veu1_resources[] = {
765 .flags = IORESOURCE_MEM,
769 static struct platform_device veu1_device = {
770 .name = "uio_pdrv_genirq",
773 .platform_data = &veu1_platform_data,
775 .resource = veu1_resources,
776 .num_resources = ARRAY_SIZE(veu1_resources),
780 static struct uio_info veu2_platform_data = {
783 .irq = intcs_evt2irq(0x740),
786 static struct resource veu2_resources[] = {
791 .flags = IORESOURCE_MEM,
795 static struct platform_device veu2_device = {
796 .name = "uio_pdrv_genirq",
799 .platform_data = &veu2_platform_data,
801 .resource = veu2_resources,
802 .num_resources = ARRAY_SIZE(veu2_resources),
806 static struct uio_info veu3_platform_data = {
809 .irq = intcs_evt2irq(0x760),
812 static struct resource veu3_resources[] = {
817 .flags = IORESOURCE_MEM,
821 static struct platform_device veu3_device = {
822 .name = "uio_pdrv_genirq",
825 .platform_data = &veu3_platform_data,
827 .resource = veu3_resources,
828 .num_resources = ARRAY_SIZE(veu3_resources),
832 static struct uio_info jpu_platform_data = {
835 .irq = intcs_evt2irq(0x560),
838 static struct resource jpu_resources[] = {
843 .flags = IORESOURCE_MEM,
847 static struct platform_device jpu_device = {
848 .name = "uio_pdrv_genirq",
851 .platform_data = &jpu_platform_data,
853 .resource = jpu_resources,
854 .num_resources = ARRAY_SIZE(jpu_resources),
858 static struct uio_info spu0_platform_data = {
861 .irq = evt2irq(0x1800),
864 static struct resource spu0_resources[] = {
869 .flags = IORESOURCE_MEM,
873 static struct platform_device spu0_device = {
874 .name = "uio_pdrv_genirq",
877 .platform_data = &spu0_platform_data,
879 .resource = spu0_resources,
880 .num_resources = ARRAY_SIZE(spu0_resources),
884 static struct uio_info spu1_platform_data = {
887 .irq = evt2irq(0x1820),
890 static struct resource spu1_resources[] = {
895 .flags = IORESOURCE_MEM,
899 static struct platform_device spu1_device = {
900 .name = "uio_pdrv_genirq",
903 .platform_data = &spu1_platform_data,
905 .resource = spu1_resources,
906 .num_resources = ARRAY_SIZE(spu1_resources),
909 /* IPMMUI (an IPMMU module for ICB/LMB) */
910 static struct resource ipmmu_resources[] = {
915 .flags = IORESOURCE_MEM,
919 static const char * const ipmmu_dev_names[] = {
920 "sh_mobile_lcdc_fb.0",
921 "sh_mobile_lcdc_fb.1",
931 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
932 .dev_names = ipmmu_dev_names,
933 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
936 static struct platform_device ipmmu_device = {
940 .platform_data = &ipmmu_platform_data,
942 .resource = ipmmu_resources,
943 .num_resources = ARRAY_SIZE(ipmmu_resources),
946 static struct platform_device *sh7372_early_devices[] __initdata = {
960 static struct platform_device *sh7372_late_devices[] __initdata = {
978 void __init sh7372_add_standard_devices(void)
980 struct pm_domain_device domain_devices[] = {
981 { "A3RV", &vpu_device, },
982 { "A4MP", &spu0_device, },
983 { "A4MP", &spu1_device, },
984 { "A3SP", &scif0_device, },
985 { "A3SP", &scif1_device, },
986 { "A3SP", &scif2_device, },
987 { "A3SP", &scif3_device, },
988 { "A3SP", &scif4_device, },
989 { "A3SP", &scif5_device, },
990 { "A3SP", &scif6_device, },
991 { "A3SP", &iic1_device, },
992 { "A3SP", &dma0_device, },
993 { "A3SP", &dma1_device, },
994 { "A3SP", &dma2_device, },
995 { "A3SP", &usb_dma0_device, },
996 { "A3SP", &usb_dma1_device, },
997 { "A4R", &iic0_device, },
998 { "A4R", &veu0_device, },
999 { "A4R", &veu1_device, },
1000 { "A4R", &veu2_device, },
1001 { "A4R", &veu3_device, },
1002 { "A4R", &jpu_device, },
1003 { "A4R", &tmu00_device, },
1004 { "A4R", &tmu01_device, },
1007 sh7372_init_pm_domains();
1009 platform_add_devices(sh7372_early_devices,
1010 ARRAY_SIZE(sh7372_early_devices));
1012 platform_add_devices(sh7372_late_devices,
1013 ARRAY_SIZE(sh7372_late_devices));
1015 rmobile_add_devices_to_domains(domain_devices,
1016 ARRAY_SIZE(domain_devices));
1019 void __init sh7372_earlytimer_init(void)
1021 sh7372_clock_init();
1022 shmobile_earlytimer_init();
1025 void __init sh7372_add_early_devices(void)
1027 early_platform_add_devices(sh7372_early_devices,
1028 ARRAY_SIZE(sh7372_early_devices));
1030 /* setup early console here as well */
1031 shmobile_setup_console();
1034 #ifdef CONFIG_USE_OF
1036 void __init sh7372_add_early_devices_dt(void)
1038 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1040 early_platform_add_devices(sh7372_early_devices,
1041 ARRAY_SIZE(sh7372_early_devices));
1043 /* setup early console here as well */
1044 shmobile_setup_console();
1047 void __init sh7372_add_standard_devices_dt(void)
1049 /* clocks are setup late during boot in the case of DT */
1050 sh7372_clock_init();
1052 platform_add_devices(sh7372_early_devices,
1053 ARRAY_SIZE(sh7372_early_devices));
1055 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1058 static const char *sh7372_boards_compat_dt[] __initdata = {
1063 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1064 .map_io = sh7372_map_io,
1065 .init_early = sh7372_add_early_devices_dt,
1066 .nr_irqs = NR_IRQS_LEGACY,
1067 .init_irq = sh7372_init_irq,
1068 .handle_irq = shmobile_handle_irq_intc,
1069 .init_machine = sh7372_add_standard_devices_dt,
1070 .dt_compat = sh7372_boards_compat_dt,
1073 #endif /* CONFIG_USE_OF */