2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/platform_data/sh_ipmmu.h>
35 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
36 #include <mach/dma-register.h>
37 #include <mach/irqs.h>
38 #include <mach/sh73a0.h>
39 #include <mach/common.h>
40 #include <asm/mach-types.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/time.h>
45 static struct map_desc sh73a0_io_desc[] __initdata = {
46 /* create a 1:1 entity map for 0xe6xxxxxx
47 * used by CPGA, INTC and PFC.
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
53 .type = MT_DEVICE_NONSHARED
57 void __init sh73a0_map_io(void)
59 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
63 static struct resource pfc_resources[] __initdata = {
64 DEFINE_RES_MEM(0xe6050000, 0x8000),
65 DEFINE_RES_MEM(0xe605801c, 0x000c),
68 void __init sh73a0_pinmux_init(void)
70 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
71 ARRAY_SIZE(pfc_resources));
74 static struct plat_sci_port scif0_platform_data = {
75 .mapbase = 0xe6c40000,
76 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE,
78 .scbrr_algo_id = SCBRR_ALGO_4,
80 .irqs = { gic_spi(72), gic_spi(72),
81 gic_spi(72), gic_spi(72) },
84 static struct platform_device scif0_device = {
88 .platform_data = &scif0_platform_data,
92 static struct plat_sci_port scif1_platform_data = {
93 .mapbase = 0xe6c50000,
94 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_RE | SCSCR_TE,
96 .scbrr_algo_id = SCBRR_ALGO_4,
98 .irqs = { gic_spi(73), gic_spi(73),
99 gic_spi(73), gic_spi(73) },
102 static struct platform_device scif1_device = {
106 .platform_data = &scif1_platform_data,
110 static struct plat_sci_port scif2_platform_data = {
111 .mapbase = 0xe6c60000,
112 .flags = UPF_BOOT_AUTOCONF,
113 .scscr = SCSCR_RE | SCSCR_TE,
114 .scbrr_algo_id = SCBRR_ALGO_4,
116 .irqs = { gic_spi(74), gic_spi(74),
117 gic_spi(74), gic_spi(74) },
120 static struct platform_device scif2_device = {
124 .platform_data = &scif2_platform_data,
128 static struct plat_sci_port scif3_platform_data = {
129 .mapbase = 0xe6c70000,
130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_RE | SCSCR_TE,
132 .scbrr_algo_id = SCBRR_ALGO_4,
134 .irqs = { gic_spi(75), gic_spi(75),
135 gic_spi(75), gic_spi(75) },
138 static struct platform_device scif3_device = {
142 .platform_data = &scif3_platform_data,
146 static struct plat_sci_port scif4_platform_data = {
147 .mapbase = 0xe6c80000,
148 .flags = UPF_BOOT_AUTOCONF,
149 .scscr = SCSCR_RE | SCSCR_TE,
150 .scbrr_algo_id = SCBRR_ALGO_4,
152 .irqs = { gic_spi(78), gic_spi(78),
153 gic_spi(78), gic_spi(78) },
156 static struct platform_device scif4_device = {
160 .platform_data = &scif4_platform_data,
164 static struct plat_sci_port scif5_platform_data = {
165 .mapbase = 0xe6cb0000,
166 .flags = UPF_BOOT_AUTOCONF,
167 .scscr = SCSCR_RE | SCSCR_TE,
168 .scbrr_algo_id = SCBRR_ALGO_4,
170 .irqs = { gic_spi(79), gic_spi(79),
171 gic_spi(79), gic_spi(79) },
174 static struct platform_device scif5_device = {
178 .platform_data = &scif5_platform_data,
182 static struct plat_sci_port scif6_platform_data = {
183 .mapbase = 0xe6cc0000,
184 .flags = UPF_BOOT_AUTOCONF,
185 .scscr = SCSCR_RE | SCSCR_TE,
186 .scbrr_algo_id = SCBRR_ALGO_4,
188 .irqs = { gic_spi(156), gic_spi(156),
189 gic_spi(156), gic_spi(156) },
192 static struct platform_device scif6_device = {
196 .platform_data = &scif6_platform_data,
200 static struct plat_sci_port scif7_platform_data = {
201 .mapbase = 0xe6cd0000,
202 .flags = UPF_BOOT_AUTOCONF,
203 .scscr = SCSCR_RE | SCSCR_TE,
204 .scbrr_algo_id = SCBRR_ALGO_4,
206 .irqs = { gic_spi(143), gic_spi(143),
207 gic_spi(143), gic_spi(143) },
210 static struct platform_device scif7_device = {
214 .platform_data = &scif7_platform_data,
218 static struct plat_sci_port scif8_platform_data = {
219 .mapbase = 0xe6c30000,
220 .flags = UPF_BOOT_AUTOCONF,
221 .scscr = SCSCR_RE | SCSCR_TE,
222 .scbrr_algo_id = SCBRR_ALGO_4,
224 .irqs = { gic_spi(80), gic_spi(80),
225 gic_spi(80), gic_spi(80) },
228 static struct platform_device scif8_device = {
232 .platform_data = &scif8_platform_data,
236 static struct sh_timer_config cmt10_platform_data = {
238 .channel_offset = 0x10,
240 .clockevent_rating = 80,
241 .clocksource_rating = 125,
244 static struct resource cmt10_resources[] = {
249 .flags = IORESOURCE_MEM,
252 .start = gic_spi(65),
253 .flags = IORESOURCE_IRQ,
257 static struct platform_device cmt10_device = {
261 .platform_data = &cmt10_platform_data,
263 .resource = cmt10_resources,
264 .num_resources = ARRAY_SIZE(cmt10_resources),
268 static struct sh_timer_config tmu00_platform_data = {
270 .channel_offset = 0x4,
272 .clockevent_rating = 200,
275 static struct resource tmu00_resources[] = {
276 [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
278 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
279 .flags = IORESOURCE_IRQ,
283 static struct platform_device tmu00_device = {
287 .platform_data = &tmu00_platform_data,
289 .resource = tmu00_resources,
290 .num_resources = ARRAY_SIZE(tmu00_resources),
293 static struct sh_timer_config tmu01_platform_data = {
295 .channel_offset = 0x10,
297 .clocksource_rating = 200,
300 static struct resource tmu01_resources[] = {
301 [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
303 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
304 .flags = IORESOURCE_IRQ,
308 static struct platform_device tmu01_device = {
312 .platform_data = &tmu01_platform_data,
314 .resource = tmu01_resources,
315 .num_resources = ARRAY_SIZE(tmu01_resources),
318 static struct resource i2c0_resources[] = {
319 [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
321 .start = gic_spi(167),
323 .flags = IORESOURCE_IRQ,
327 static struct resource i2c1_resources[] = {
328 [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
330 .start = gic_spi(51),
332 .flags = IORESOURCE_IRQ,
336 static struct resource i2c2_resources[] = {
337 [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
339 .start = gic_spi(171),
341 .flags = IORESOURCE_IRQ,
345 static struct resource i2c3_resources[] = {
346 [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
348 .start = gic_spi(183),
350 .flags = IORESOURCE_IRQ,
354 static struct resource i2c4_resources[] = {
355 [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
357 .start = gic_spi(187),
359 .flags = IORESOURCE_IRQ,
363 static struct platform_device i2c0_device = {
364 .name = "i2c-sh_mobile",
366 .resource = i2c0_resources,
367 .num_resources = ARRAY_SIZE(i2c0_resources),
370 static struct platform_device i2c1_device = {
371 .name = "i2c-sh_mobile",
373 .resource = i2c1_resources,
374 .num_resources = ARRAY_SIZE(i2c1_resources),
377 static struct platform_device i2c2_device = {
378 .name = "i2c-sh_mobile",
380 .resource = i2c2_resources,
381 .num_resources = ARRAY_SIZE(i2c2_resources),
384 static struct platform_device i2c3_device = {
385 .name = "i2c-sh_mobile",
387 .resource = i2c3_resources,
388 .num_resources = ARRAY_SIZE(i2c3_resources),
391 static struct platform_device i2c4_device = {
392 .name = "i2c-sh_mobile",
394 .resource = i2c4_resources,
395 .num_resources = ARRAY_SIZE(i2c4_resources),
398 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
400 .slave_id = SHDMA_SLAVE_SCIF0_TX,
402 .chcr = CHCR_TX(XMIT_SZ_8BIT),
405 .slave_id = SHDMA_SLAVE_SCIF0_RX,
407 .chcr = CHCR_RX(XMIT_SZ_8BIT),
410 .slave_id = SHDMA_SLAVE_SCIF1_TX,
412 .chcr = CHCR_TX(XMIT_SZ_8BIT),
415 .slave_id = SHDMA_SLAVE_SCIF1_RX,
417 .chcr = CHCR_RX(XMIT_SZ_8BIT),
420 .slave_id = SHDMA_SLAVE_SCIF2_TX,
422 .chcr = CHCR_TX(XMIT_SZ_8BIT),
425 .slave_id = SHDMA_SLAVE_SCIF2_RX,
427 .chcr = CHCR_RX(XMIT_SZ_8BIT),
430 .slave_id = SHDMA_SLAVE_SCIF3_TX,
432 .chcr = CHCR_TX(XMIT_SZ_8BIT),
435 .slave_id = SHDMA_SLAVE_SCIF3_RX,
437 .chcr = CHCR_RX(XMIT_SZ_8BIT),
440 .slave_id = SHDMA_SLAVE_SCIF4_TX,
442 .chcr = CHCR_TX(XMIT_SZ_8BIT),
445 .slave_id = SHDMA_SLAVE_SCIF4_RX,
447 .chcr = CHCR_RX(XMIT_SZ_8BIT),
450 .slave_id = SHDMA_SLAVE_SCIF5_TX,
452 .chcr = CHCR_TX(XMIT_SZ_8BIT),
455 .slave_id = SHDMA_SLAVE_SCIF5_RX,
457 .chcr = CHCR_RX(XMIT_SZ_8BIT),
460 .slave_id = SHDMA_SLAVE_SCIF6_TX,
462 .chcr = CHCR_TX(XMIT_SZ_8BIT),
465 .slave_id = SHDMA_SLAVE_SCIF6_RX,
467 .chcr = CHCR_RX(XMIT_SZ_8BIT),
470 .slave_id = SHDMA_SLAVE_SCIF7_TX,
472 .chcr = CHCR_TX(XMIT_SZ_8BIT),
475 .slave_id = SHDMA_SLAVE_SCIF7_RX,
477 .chcr = CHCR_RX(XMIT_SZ_8BIT),
480 .slave_id = SHDMA_SLAVE_SCIF8_TX,
482 .chcr = CHCR_TX(XMIT_SZ_8BIT),
485 .slave_id = SHDMA_SLAVE_SCIF8_RX,
487 .chcr = CHCR_RX(XMIT_SZ_8BIT),
490 .slave_id = SHDMA_SLAVE_SDHI0_TX,
492 .chcr = CHCR_TX(XMIT_SZ_16BIT),
495 .slave_id = SHDMA_SLAVE_SDHI0_RX,
497 .chcr = CHCR_RX(XMIT_SZ_16BIT),
500 .slave_id = SHDMA_SLAVE_SDHI1_TX,
502 .chcr = CHCR_TX(XMIT_SZ_16BIT),
505 .slave_id = SHDMA_SLAVE_SDHI1_RX,
507 .chcr = CHCR_RX(XMIT_SZ_16BIT),
510 .slave_id = SHDMA_SLAVE_SDHI2_TX,
512 .chcr = CHCR_TX(XMIT_SZ_16BIT),
515 .slave_id = SHDMA_SLAVE_SDHI2_RX,
517 .chcr = CHCR_RX(XMIT_SZ_16BIT),
520 .slave_id = SHDMA_SLAVE_MMCIF_TX,
522 .chcr = CHCR_TX(XMIT_SZ_32BIT),
525 .slave_id = SHDMA_SLAVE_MMCIF_RX,
527 .chcr = CHCR_RX(XMIT_SZ_32BIT),
532 #define DMAE_CHANNEL(_offset) \
534 .offset = _offset - 0x20, \
535 .dmars = _offset - 0x20 + 0x40, \
538 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
539 DMAE_CHANNEL(0x8000),
540 DMAE_CHANNEL(0x8080),
541 DMAE_CHANNEL(0x8100),
542 DMAE_CHANNEL(0x8180),
543 DMAE_CHANNEL(0x8200),
544 DMAE_CHANNEL(0x8280),
545 DMAE_CHANNEL(0x8300),
546 DMAE_CHANNEL(0x8380),
547 DMAE_CHANNEL(0x8400),
548 DMAE_CHANNEL(0x8480),
549 DMAE_CHANNEL(0x8500),
550 DMAE_CHANNEL(0x8580),
551 DMAE_CHANNEL(0x8600),
552 DMAE_CHANNEL(0x8680),
553 DMAE_CHANNEL(0x8700),
554 DMAE_CHANNEL(0x8780),
555 DMAE_CHANNEL(0x8800),
556 DMAE_CHANNEL(0x8880),
557 DMAE_CHANNEL(0x8900),
558 DMAE_CHANNEL(0x8980),
561 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
562 .slave = sh73a0_dmae_slaves,
563 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
564 .channel = sh73a0_dmae_channels,
565 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
566 .ts_low_shift = TS_LOW_SHIFT,
567 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
568 .ts_high_shift = TS_HI_SHIFT,
569 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
570 .ts_shift = dma_ts_shift,
571 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
572 .dmaor_init = DMAOR_DME,
575 static struct resource sh73a0_dmae_resources[] = {
576 DEFINE_RES_MEM(0xfe000020, 0x89e0),
579 .start = gic_spi(129),
581 .flags = IORESOURCE_IRQ,
584 /* IRQ for channels 0-19 */
585 .start = gic_spi(109),
587 .flags = IORESOURCE_IRQ,
591 static struct platform_device dma0_device = {
592 .name = "sh-dma-engine",
594 .resource = sh73a0_dmae_resources,
595 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
597 .platform_data = &sh73a0_dmae_platform_data,
602 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
604 .slave_id = SHDMA_SLAVE_FSI2A_RX,
606 .chcr = CHCR_RX(XMIT_SZ_32BIT),
607 .mid_rid = 0xd6, /* CHECK ME */
609 .slave_id = SHDMA_SLAVE_FSI2A_TX,
611 .chcr = CHCR_TX(XMIT_SZ_32BIT),
612 .mid_rid = 0xd5, /* CHECK ME */
614 .slave_id = SHDMA_SLAVE_FSI2C_RX,
616 .chcr = CHCR_RX(XMIT_SZ_32BIT),
617 .mid_rid = 0xda, /* CHECK ME */
619 .slave_id = SHDMA_SLAVE_FSI2C_TX,
621 .chcr = CHCR_TX(XMIT_SZ_32BIT),
622 .mid_rid = 0xd9, /* CHECK ME */
624 .slave_id = SHDMA_SLAVE_FSI2B_RX,
626 .chcr = CHCR_RX(XMIT_SZ_32BIT),
627 .mid_rid = 0x8e, /* CHECK ME */
629 .slave_id = SHDMA_SLAVE_FSI2B_TX,
631 .chcr = CHCR_RX(XMIT_SZ_32BIT),
632 .mid_rid = 0x8d, /* CHECK ME */
634 .slave_id = SHDMA_SLAVE_FSI2D_RX,
636 .chcr = CHCR_RX(XMIT_SZ_32BIT),
637 .mid_rid = 0x9a, /* CHECK ME */
641 #define MPDMA_CHANNEL(a, b, c) \
646 .chclr_offset = (0x220 - 0x20) + a \
649 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
650 MPDMA_CHANNEL(0x00, 0, 0),
651 MPDMA_CHANNEL(0x10, 0, 8),
652 MPDMA_CHANNEL(0x20, 4, 0),
653 MPDMA_CHANNEL(0x30, 4, 8),
654 MPDMA_CHANNEL(0x50, 8, 0),
655 MPDMA_CHANNEL(0x70, 8, 8),
658 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
659 .slave = sh73a0_mpdma_slaves,
660 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
661 .channel = sh73a0_mpdma_channels,
662 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
663 .ts_low_shift = TS_LOW_SHIFT,
664 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
665 .ts_high_shift = TS_HI_SHIFT,
666 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
667 .ts_shift = dma_ts_shift,
668 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
669 .dmaor_init = DMAOR_DME,
673 /* Resource order important! */
674 static struct resource sh73a0_mpdma_resources[] = {
675 /* Channel registers and DMAOR */
676 DEFINE_RES_MEM(0xec618020, 0x270),
678 DEFINE_RES_MEM(0xec619000, 0xc),
681 .start = gic_spi(181),
683 .flags = IORESOURCE_IRQ,
686 /* IRQ for channels 0-5 */
687 .start = gic_spi(175),
689 .flags = IORESOURCE_IRQ,
693 static struct platform_device mpdma0_device = {
694 .name = "sh-dma-engine",
696 .resource = sh73a0_mpdma_resources,
697 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
699 .platform_data = &sh73a0_mpdma_platform_data,
703 static struct resource pmu_resources[] = {
705 .start = gic_spi(55),
707 .flags = IORESOURCE_IRQ,
710 .start = gic_spi(56),
712 .flags = IORESOURCE_IRQ,
716 static struct platform_device pmu_device = {
719 .num_resources = ARRAY_SIZE(pmu_resources),
720 .resource = pmu_resources,
723 /* an IPMMU module for ICB */
724 static struct resource ipmmu_resources[] = {
725 DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
728 static const char * const ipmmu_dev_names[] = {
729 "sh_mobile_lcdc_fb.0",
732 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
733 .dev_names = ipmmu_dev_names,
734 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
737 static struct platform_device ipmmu_device = {
741 .platform_data = &ipmmu_platform_data,
743 .resource = ipmmu_resources,
744 .num_resources = ARRAY_SIZE(ipmmu_resources),
747 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
748 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
751 static struct resource irqpin0_resources[] = {
752 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
753 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
754 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
755 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
756 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
757 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
758 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
759 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
760 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
761 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
762 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
763 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
764 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
767 static struct platform_device irqpin0_device = {
768 .name = "renesas_intc_irqpin",
770 .resource = irqpin0_resources,
771 .num_resources = ARRAY_SIZE(irqpin0_resources),
773 .platform_data = &irqpin0_platform_data,
777 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
778 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
779 .control_parent = true, /* Disable spurious IRQ10 */
782 static struct resource irqpin1_resources[] = {
783 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
784 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
785 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
786 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
787 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
788 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
789 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
790 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
791 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
792 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
793 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
794 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
795 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
798 static struct platform_device irqpin1_device = {
799 .name = "renesas_intc_irqpin",
801 .resource = irqpin1_resources,
802 .num_resources = ARRAY_SIZE(irqpin1_resources),
804 .platform_data = &irqpin1_platform_data,
808 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
809 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
812 static struct resource irqpin2_resources[] = {
813 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
814 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
815 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
816 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
817 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
818 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
819 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
820 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
821 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
822 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
823 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
824 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
825 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
828 static struct platform_device irqpin2_device = {
829 .name = "renesas_intc_irqpin",
831 .resource = irqpin2_resources,
832 .num_resources = ARRAY_SIZE(irqpin2_resources),
834 .platform_data = &irqpin2_platform_data,
838 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
839 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
842 static struct resource irqpin3_resources[] = {
843 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
844 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
845 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
846 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
847 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
848 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
849 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
850 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
851 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
852 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
853 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
854 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
855 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
858 static struct platform_device irqpin3_device = {
859 .name = "renesas_intc_irqpin",
861 .resource = irqpin3_resources,
862 .num_resources = ARRAY_SIZE(irqpin3_resources),
864 .platform_data = &irqpin3_platform_data,
868 static struct platform_device *sh73a0_devices_dt[] __initdata = {
881 static struct platform_device *sh73a0_early_devices[] __initdata = {
887 static struct platform_device *sh73a0_late_devices[] __initdata = {
902 #define SRCR2 IOMEM(0xe61580b0)
904 void __init sh73a0_add_standard_devices(void)
906 /* Clear software reset bit on SY-DMAC module */
907 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
909 platform_add_devices(sh73a0_devices_dt,
910 ARRAY_SIZE(sh73a0_devices_dt));
911 platform_add_devices(sh73a0_early_devices,
912 ARRAY_SIZE(sh73a0_early_devices));
913 platform_add_devices(sh73a0_late_devices,
914 ARRAY_SIZE(sh73a0_late_devices));
917 void __init sh73a0_init_delay(void)
919 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
922 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
923 void __init __weak sh73a0_register_twd(void) { }
925 void __init sh73a0_earlytimer_init(void)
929 shmobile_earlytimer_init();
930 sh73a0_register_twd();
933 void __init sh73a0_add_early_devices(void)
935 early_platform_add_devices(sh73a0_devices_dt,
936 ARRAY_SIZE(sh73a0_devices_dt));
937 early_platform_add_devices(sh73a0_early_devices,
938 ARRAY_SIZE(sh73a0_early_devices));
940 /* setup early console here as well */
941 shmobile_setup_console();
946 void __init sh73a0_add_standard_devices_dt(void)
948 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
950 /* clocks are setup late during boot in the case of DT */
953 platform_add_devices(sh73a0_devices_dt,
954 ARRAY_SIZE(sh73a0_devices_dt));
955 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
957 /* Instantiate cpufreq-cpu0 */
958 platform_device_register_full(&devinfo);
961 static const char *sh73a0_boards_compat_dt[] __initdata = {
966 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
967 .smp = smp_ops(sh73a0_smp_ops),
968 .map_io = sh73a0_map_io,
969 .init_early = sh73a0_init_delay,
970 .nr_irqs = NR_IRQS_LEGACY,
971 .init_machine = sh73a0_add_standard_devices_dt,
972 .dt_compat = sh73a0_boards_compat_dt,
974 #endif /* CONFIG_USE_OF */