2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqchip.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_platform.h>
28 #include <linux/delay.h>
29 #include <linux/input.h>
31 #include <linux/serial_sci.h>
32 #include <linux/sh_dma.h>
33 #include <linux/sh_intc.h>
34 #include <linux/sh_timer.h>
35 #include <linux/platform_data/sh_ipmmu.h>
36 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
37 #include <mach/dma-register.h>
38 #include <mach/hardware.h>
39 #include <mach/irqs.h>
40 #include <mach/sh73a0.h>
41 #include <mach/common.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/arch.h>
45 #include <asm/mach/time.h>
47 static struct map_desc sh73a0_io_desc[] __initdata = {
48 /* create a 1:1 entity map for 0xe6xxxxxx
49 * used by CPGA, INTC and PFC.
52 .virtual = 0xe6000000,
53 .pfn = __phys_to_pfn(0xe6000000),
55 .type = MT_DEVICE_NONSHARED
59 void __init sh73a0_map_io(void)
61 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
64 static struct resource sh73a0_pfc_resources[] = {
68 .flags = IORESOURCE_MEM,
73 .flags = IORESOURCE_MEM,
77 static struct platform_device sh73a0_pfc_device = {
80 .resource = sh73a0_pfc_resources,
81 .num_resources = ARRAY_SIZE(sh73a0_pfc_resources),
84 void __init sh73a0_pinmux_init(void)
86 platform_device_register(&sh73a0_pfc_device);
89 static struct plat_sci_port scif0_platform_data = {
90 .mapbase = 0xe6c40000,
91 .flags = UPF_BOOT_AUTOCONF,
92 .scscr = SCSCR_RE | SCSCR_TE,
93 .scbrr_algo_id = SCBRR_ALGO_4,
95 .irqs = { gic_spi(72), gic_spi(72),
96 gic_spi(72), gic_spi(72) },
99 static struct platform_device scif0_device = {
103 .platform_data = &scif0_platform_data,
107 static struct plat_sci_port scif1_platform_data = {
108 .mapbase = 0xe6c50000,
109 .flags = UPF_BOOT_AUTOCONF,
110 .scscr = SCSCR_RE | SCSCR_TE,
111 .scbrr_algo_id = SCBRR_ALGO_4,
113 .irqs = { gic_spi(73), gic_spi(73),
114 gic_spi(73), gic_spi(73) },
117 static struct platform_device scif1_device = {
121 .platform_data = &scif1_platform_data,
125 static struct plat_sci_port scif2_platform_data = {
126 .mapbase = 0xe6c60000,
127 .flags = UPF_BOOT_AUTOCONF,
128 .scscr = SCSCR_RE | SCSCR_TE,
129 .scbrr_algo_id = SCBRR_ALGO_4,
131 .irqs = { gic_spi(74), gic_spi(74),
132 gic_spi(74), gic_spi(74) },
135 static struct platform_device scif2_device = {
139 .platform_data = &scif2_platform_data,
143 static struct plat_sci_port scif3_platform_data = {
144 .mapbase = 0xe6c70000,
145 .flags = UPF_BOOT_AUTOCONF,
146 .scscr = SCSCR_RE | SCSCR_TE,
147 .scbrr_algo_id = SCBRR_ALGO_4,
149 .irqs = { gic_spi(75), gic_spi(75),
150 gic_spi(75), gic_spi(75) },
153 static struct platform_device scif3_device = {
157 .platform_data = &scif3_platform_data,
161 static struct plat_sci_port scif4_platform_data = {
162 .mapbase = 0xe6c80000,
163 .flags = UPF_BOOT_AUTOCONF,
164 .scscr = SCSCR_RE | SCSCR_TE,
165 .scbrr_algo_id = SCBRR_ALGO_4,
167 .irqs = { gic_spi(78), gic_spi(78),
168 gic_spi(78), gic_spi(78) },
171 static struct platform_device scif4_device = {
175 .platform_data = &scif4_platform_data,
179 static struct plat_sci_port scif5_platform_data = {
180 .mapbase = 0xe6cb0000,
181 .flags = UPF_BOOT_AUTOCONF,
182 .scscr = SCSCR_RE | SCSCR_TE,
183 .scbrr_algo_id = SCBRR_ALGO_4,
185 .irqs = { gic_spi(79), gic_spi(79),
186 gic_spi(79), gic_spi(79) },
189 static struct platform_device scif5_device = {
193 .platform_data = &scif5_platform_data,
197 static struct plat_sci_port scif6_platform_data = {
198 .mapbase = 0xe6cc0000,
199 .flags = UPF_BOOT_AUTOCONF,
200 .scscr = SCSCR_RE | SCSCR_TE,
201 .scbrr_algo_id = SCBRR_ALGO_4,
203 .irqs = { gic_spi(156), gic_spi(156),
204 gic_spi(156), gic_spi(156) },
207 static struct platform_device scif6_device = {
211 .platform_data = &scif6_platform_data,
215 static struct plat_sci_port scif7_platform_data = {
216 .mapbase = 0xe6cd0000,
217 .flags = UPF_BOOT_AUTOCONF,
218 .scscr = SCSCR_RE | SCSCR_TE,
219 .scbrr_algo_id = SCBRR_ALGO_4,
221 .irqs = { gic_spi(143), gic_spi(143),
222 gic_spi(143), gic_spi(143) },
225 static struct platform_device scif7_device = {
229 .platform_data = &scif7_platform_data,
233 static struct plat_sci_port scif8_platform_data = {
234 .mapbase = 0xe6c30000,
235 .flags = UPF_BOOT_AUTOCONF,
236 .scscr = SCSCR_RE | SCSCR_TE,
237 .scbrr_algo_id = SCBRR_ALGO_4,
239 .irqs = { gic_spi(80), gic_spi(80),
240 gic_spi(80), gic_spi(80) },
243 static struct platform_device scif8_device = {
247 .platform_data = &scif8_platform_data,
251 static struct sh_timer_config cmt10_platform_data = {
253 .channel_offset = 0x10,
255 .clockevent_rating = 80,
256 .clocksource_rating = 125,
259 static struct resource cmt10_resources[] = {
264 .flags = IORESOURCE_MEM,
267 .start = gic_spi(65),
268 .flags = IORESOURCE_IRQ,
272 static struct platform_device cmt10_device = {
276 .platform_data = &cmt10_platform_data,
278 .resource = cmt10_resources,
279 .num_resources = ARRAY_SIZE(cmt10_resources),
283 static struct sh_timer_config tmu00_platform_data = {
285 .channel_offset = 0x4,
287 .clockevent_rating = 200,
290 static struct resource tmu00_resources[] = {
291 [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
293 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
294 .flags = IORESOURCE_IRQ,
298 static struct platform_device tmu00_device = {
302 .platform_data = &tmu00_platform_data,
304 .resource = tmu00_resources,
305 .num_resources = ARRAY_SIZE(tmu00_resources),
308 static struct sh_timer_config tmu01_platform_data = {
310 .channel_offset = 0x10,
312 .clocksource_rating = 200,
315 static struct resource tmu01_resources[] = {
316 [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
318 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
319 .flags = IORESOURCE_IRQ,
323 static struct platform_device tmu01_device = {
327 .platform_data = &tmu01_platform_data,
329 .resource = tmu01_resources,
330 .num_resources = ARRAY_SIZE(tmu01_resources),
333 static struct resource i2c0_resources[] = {
334 [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
336 .start = gic_spi(167),
338 .flags = IORESOURCE_IRQ,
342 static struct resource i2c1_resources[] = {
343 [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
345 .start = gic_spi(51),
347 .flags = IORESOURCE_IRQ,
351 static struct resource i2c2_resources[] = {
352 [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
354 .start = gic_spi(171),
356 .flags = IORESOURCE_IRQ,
360 static struct resource i2c3_resources[] = {
361 [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
363 .start = gic_spi(183),
365 .flags = IORESOURCE_IRQ,
369 static struct resource i2c4_resources[] = {
370 [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
372 .start = gic_spi(187),
374 .flags = IORESOURCE_IRQ,
378 static struct platform_device i2c0_device = {
379 .name = "i2c-sh_mobile",
381 .resource = i2c0_resources,
382 .num_resources = ARRAY_SIZE(i2c0_resources),
385 static struct platform_device i2c1_device = {
386 .name = "i2c-sh_mobile",
388 .resource = i2c1_resources,
389 .num_resources = ARRAY_SIZE(i2c1_resources),
392 static struct platform_device i2c2_device = {
393 .name = "i2c-sh_mobile",
395 .resource = i2c2_resources,
396 .num_resources = ARRAY_SIZE(i2c2_resources),
399 static struct platform_device i2c3_device = {
400 .name = "i2c-sh_mobile",
402 .resource = i2c3_resources,
403 .num_resources = ARRAY_SIZE(i2c3_resources),
406 static struct platform_device i2c4_device = {
407 .name = "i2c-sh_mobile",
409 .resource = i2c4_resources,
410 .num_resources = ARRAY_SIZE(i2c4_resources),
413 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
415 .slave_id = SHDMA_SLAVE_SCIF0_TX,
417 .chcr = CHCR_TX(XMIT_SZ_8BIT),
420 .slave_id = SHDMA_SLAVE_SCIF0_RX,
422 .chcr = CHCR_RX(XMIT_SZ_8BIT),
425 .slave_id = SHDMA_SLAVE_SCIF1_TX,
427 .chcr = CHCR_TX(XMIT_SZ_8BIT),
430 .slave_id = SHDMA_SLAVE_SCIF1_RX,
432 .chcr = CHCR_RX(XMIT_SZ_8BIT),
435 .slave_id = SHDMA_SLAVE_SCIF2_TX,
437 .chcr = CHCR_TX(XMIT_SZ_8BIT),
440 .slave_id = SHDMA_SLAVE_SCIF2_RX,
442 .chcr = CHCR_RX(XMIT_SZ_8BIT),
445 .slave_id = SHDMA_SLAVE_SCIF3_TX,
447 .chcr = CHCR_TX(XMIT_SZ_8BIT),
450 .slave_id = SHDMA_SLAVE_SCIF3_RX,
452 .chcr = CHCR_RX(XMIT_SZ_8BIT),
455 .slave_id = SHDMA_SLAVE_SCIF4_TX,
457 .chcr = CHCR_TX(XMIT_SZ_8BIT),
460 .slave_id = SHDMA_SLAVE_SCIF4_RX,
462 .chcr = CHCR_RX(XMIT_SZ_8BIT),
465 .slave_id = SHDMA_SLAVE_SCIF5_TX,
467 .chcr = CHCR_TX(XMIT_SZ_8BIT),
470 .slave_id = SHDMA_SLAVE_SCIF5_RX,
472 .chcr = CHCR_RX(XMIT_SZ_8BIT),
475 .slave_id = SHDMA_SLAVE_SCIF6_TX,
477 .chcr = CHCR_TX(XMIT_SZ_8BIT),
480 .slave_id = SHDMA_SLAVE_SCIF6_RX,
482 .chcr = CHCR_RX(XMIT_SZ_8BIT),
485 .slave_id = SHDMA_SLAVE_SCIF7_TX,
487 .chcr = CHCR_TX(XMIT_SZ_8BIT),
490 .slave_id = SHDMA_SLAVE_SCIF7_RX,
492 .chcr = CHCR_RX(XMIT_SZ_8BIT),
495 .slave_id = SHDMA_SLAVE_SCIF8_TX,
497 .chcr = CHCR_TX(XMIT_SZ_8BIT),
500 .slave_id = SHDMA_SLAVE_SCIF8_RX,
502 .chcr = CHCR_RX(XMIT_SZ_8BIT),
505 .slave_id = SHDMA_SLAVE_SDHI0_TX,
507 .chcr = CHCR_TX(XMIT_SZ_16BIT),
510 .slave_id = SHDMA_SLAVE_SDHI0_RX,
512 .chcr = CHCR_RX(XMIT_SZ_16BIT),
515 .slave_id = SHDMA_SLAVE_SDHI1_TX,
517 .chcr = CHCR_TX(XMIT_SZ_16BIT),
520 .slave_id = SHDMA_SLAVE_SDHI1_RX,
522 .chcr = CHCR_RX(XMIT_SZ_16BIT),
525 .slave_id = SHDMA_SLAVE_SDHI2_TX,
527 .chcr = CHCR_TX(XMIT_SZ_16BIT),
530 .slave_id = SHDMA_SLAVE_SDHI2_RX,
532 .chcr = CHCR_RX(XMIT_SZ_16BIT),
535 .slave_id = SHDMA_SLAVE_MMCIF_TX,
537 .chcr = CHCR_TX(XMIT_SZ_32BIT),
540 .slave_id = SHDMA_SLAVE_MMCIF_RX,
542 .chcr = CHCR_RX(XMIT_SZ_32BIT),
547 #define DMAE_CHANNEL(_offset) \
549 .offset = _offset - 0x20, \
550 .dmars = _offset - 0x20 + 0x40, \
553 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
554 DMAE_CHANNEL(0x8000),
555 DMAE_CHANNEL(0x8080),
556 DMAE_CHANNEL(0x8100),
557 DMAE_CHANNEL(0x8180),
558 DMAE_CHANNEL(0x8200),
559 DMAE_CHANNEL(0x8280),
560 DMAE_CHANNEL(0x8300),
561 DMAE_CHANNEL(0x8380),
562 DMAE_CHANNEL(0x8400),
563 DMAE_CHANNEL(0x8480),
564 DMAE_CHANNEL(0x8500),
565 DMAE_CHANNEL(0x8580),
566 DMAE_CHANNEL(0x8600),
567 DMAE_CHANNEL(0x8680),
568 DMAE_CHANNEL(0x8700),
569 DMAE_CHANNEL(0x8780),
570 DMAE_CHANNEL(0x8800),
571 DMAE_CHANNEL(0x8880),
572 DMAE_CHANNEL(0x8900),
573 DMAE_CHANNEL(0x8980),
576 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
577 .slave = sh73a0_dmae_slaves,
578 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
579 .channel = sh73a0_dmae_channels,
580 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
581 .ts_low_shift = TS_LOW_SHIFT,
582 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
583 .ts_high_shift = TS_HI_SHIFT,
584 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
585 .ts_shift = dma_ts_shift,
586 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
587 .dmaor_init = DMAOR_DME,
590 static struct resource sh73a0_dmae_resources[] = {
591 DEFINE_RES_MEM(0xfe000020, 0x89e0),
594 .start = gic_spi(129),
596 .flags = IORESOURCE_IRQ,
599 /* IRQ for channels 0-19 */
600 .start = gic_spi(109),
602 .flags = IORESOURCE_IRQ,
606 static struct platform_device dma0_device = {
607 .name = "sh-dma-engine",
609 .resource = sh73a0_dmae_resources,
610 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
612 .platform_data = &sh73a0_dmae_platform_data,
617 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
619 .slave_id = SHDMA_SLAVE_FSI2A_RX,
621 .chcr = CHCR_RX(XMIT_SZ_32BIT),
622 .mid_rid = 0xd6, /* CHECK ME */
624 .slave_id = SHDMA_SLAVE_FSI2A_TX,
626 .chcr = CHCR_TX(XMIT_SZ_32BIT),
627 .mid_rid = 0xd5, /* CHECK ME */
629 .slave_id = SHDMA_SLAVE_FSI2C_RX,
631 .chcr = CHCR_RX(XMIT_SZ_32BIT),
632 .mid_rid = 0xda, /* CHECK ME */
634 .slave_id = SHDMA_SLAVE_FSI2C_TX,
636 .chcr = CHCR_TX(XMIT_SZ_32BIT),
637 .mid_rid = 0xd9, /* CHECK ME */
639 .slave_id = SHDMA_SLAVE_FSI2B_RX,
641 .chcr = CHCR_RX(XMIT_SZ_32BIT),
642 .mid_rid = 0x8e, /* CHECK ME */
644 .slave_id = SHDMA_SLAVE_FSI2B_TX,
646 .chcr = CHCR_RX(XMIT_SZ_32BIT),
647 .mid_rid = 0x8d, /* CHECK ME */
649 .slave_id = SHDMA_SLAVE_FSI2D_RX,
651 .chcr = CHCR_RX(XMIT_SZ_32BIT),
652 .mid_rid = 0x9a, /* CHECK ME */
656 #define MPDMA_CHANNEL(a, b, c) \
661 .chclr_offset = (0x220 - 0x20) + a \
664 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
665 MPDMA_CHANNEL(0x00, 0, 0),
666 MPDMA_CHANNEL(0x10, 0, 8),
667 MPDMA_CHANNEL(0x20, 4, 0),
668 MPDMA_CHANNEL(0x30, 4, 8),
669 MPDMA_CHANNEL(0x50, 8, 0),
670 MPDMA_CHANNEL(0x70, 8, 8),
673 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
674 .slave = sh73a0_mpdma_slaves,
675 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
676 .channel = sh73a0_mpdma_channels,
677 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
678 .ts_low_shift = TS_LOW_SHIFT,
679 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
680 .ts_high_shift = TS_HI_SHIFT,
681 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
682 .ts_shift = dma_ts_shift,
683 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
684 .dmaor_init = DMAOR_DME,
688 /* Resource order important! */
689 static struct resource sh73a0_mpdma_resources[] = {
690 /* Channel registers and DMAOR */
691 DEFINE_RES_MEM(0xec618020, 0x270),
693 DEFINE_RES_MEM(0xec619000, 0xc),
696 .start = gic_spi(181),
698 .flags = IORESOURCE_IRQ,
701 /* IRQ for channels 0-5 */
702 .start = gic_spi(175),
704 .flags = IORESOURCE_IRQ,
708 static struct platform_device mpdma0_device = {
709 .name = "sh-dma-engine",
711 .resource = sh73a0_mpdma_resources,
712 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
714 .platform_data = &sh73a0_mpdma_platform_data,
718 static struct resource pmu_resources[] = {
720 .start = gic_spi(55),
722 .flags = IORESOURCE_IRQ,
725 .start = gic_spi(56),
727 .flags = IORESOURCE_IRQ,
731 static struct platform_device pmu_device = {
734 .num_resources = ARRAY_SIZE(pmu_resources),
735 .resource = pmu_resources,
738 /* an IPMMU module for ICB */
739 static struct resource ipmmu_resources[] = {
740 DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
743 static const char * const ipmmu_dev_names[] = {
744 "sh_mobile_lcdc_fb.0",
747 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
748 .dev_names = ipmmu_dev_names,
749 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
752 static struct platform_device ipmmu_device = {
756 .platform_data = &ipmmu_platform_data,
758 .resource = ipmmu_resources,
759 .num_resources = ARRAY_SIZE(ipmmu_resources),
762 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
763 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
766 static struct resource irqpin0_resources[] = {
767 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
768 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
769 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
770 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
771 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
772 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
773 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
774 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
775 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
776 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
777 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
778 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
779 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
782 static struct platform_device irqpin0_device = {
783 .name = "renesas_intc_irqpin",
785 .resource = irqpin0_resources,
786 .num_resources = ARRAY_SIZE(irqpin0_resources),
788 .platform_data = &irqpin0_platform_data,
792 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
793 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
794 .control_parent = true, /* Disable spurious IRQ10 */
797 static struct resource irqpin1_resources[] = {
798 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
799 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
800 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
801 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
802 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
803 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
804 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
805 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
806 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
807 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
808 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
809 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
810 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
813 static struct platform_device irqpin1_device = {
814 .name = "renesas_intc_irqpin",
816 .resource = irqpin1_resources,
817 .num_resources = ARRAY_SIZE(irqpin1_resources),
819 .platform_data = &irqpin1_platform_data,
823 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
824 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
827 static struct resource irqpin2_resources[] = {
828 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
829 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
830 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
831 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
832 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
833 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
834 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
835 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
836 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
837 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
838 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
839 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
840 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
843 static struct platform_device irqpin2_device = {
844 .name = "renesas_intc_irqpin",
846 .resource = irqpin2_resources,
847 .num_resources = ARRAY_SIZE(irqpin2_resources),
849 .platform_data = &irqpin2_platform_data,
853 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
854 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
857 static struct resource irqpin3_resources[] = {
858 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
859 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
860 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
861 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
862 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
863 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
864 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
865 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
866 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
867 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
868 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
869 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
870 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
873 static struct platform_device irqpin3_device = {
874 .name = "renesas_intc_irqpin",
876 .resource = irqpin3_resources,
877 .num_resources = ARRAY_SIZE(irqpin3_resources),
879 .platform_data = &irqpin3_platform_data,
883 static struct platform_device *sh73a0_devices_dt[] __initdata = {
896 static struct platform_device *sh73a0_early_devices[] __initdata = {
902 static struct platform_device *sh73a0_late_devices[] __initdata = {
917 #define SRCR2 IOMEM(0xe61580b0)
919 void __init sh73a0_add_standard_devices(void)
921 /* Clear software reset bit on SY-DMAC module */
922 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
924 platform_add_devices(sh73a0_devices_dt,
925 ARRAY_SIZE(sh73a0_devices_dt));
926 platform_add_devices(sh73a0_early_devices,
927 ARRAY_SIZE(sh73a0_early_devices));
928 platform_add_devices(sh73a0_late_devices,
929 ARRAY_SIZE(sh73a0_late_devices));
932 void __init sh73a0_init_delay(void)
934 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
937 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
938 void __init __weak sh73a0_register_twd(void) { }
940 void __init sh73a0_earlytimer_init(void)
944 shmobile_earlytimer_init();
945 sh73a0_register_twd();
948 void __init sh73a0_add_early_devices(void)
950 early_platform_add_devices(sh73a0_devices_dt,
951 ARRAY_SIZE(sh73a0_devices_dt));
952 early_platform_add_devices(sh73a0_early_devices,
953 ARRAY_SIZE(sh73a0_early_devices));
955 /* setup early console here as well */
956 shmobile_setup_console();
961 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
965 void __init sh73a0_add_standard_devices_dt(void)
967 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
969 /* clocks are setup late during boot in the case of DT */
972 platform_add_devices(sh73a0_devices_dt,
973 ARRAY_SIZE(sh73a0_devices_dt));
974 of_platform_populate(NULL, of_default_bus_match_table,
975 sh73a0_auxdata_lookup, NULL);
977 /* Instantiate cpufreq-cpu0 */
978 platform_device_register_full(&devinfo);
981 static const char *sh73a0_boards_compat_dt[] __initdata = {
986 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
987 .smp = smp_ops(sh73a0_smp_ops),
988 .map_io = sh73a0_map_io,
989 .init_early = sh73a0_init_delay,
990 .nr_irqs = NR_IRQS_LEGACY,
991 .init_irq = irqchip_init,
992 .init_machine = sh73a0_add_standard_devices_dt,
993 .dt_compat = sh73a0_boards_compat_dt,
995 #endif /* CONFIG_USE_OF */