2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_dma.h>
31 #include <linux/sh_intc.h>
32 #include <linux/sh_timer.h>
33 #include <mach/hardware.h>
34 #include <mach/sh73a0.h>
35 #include <asm/mach-types.h>
36 #include <asm/mach/arch.h>
38 static struct plat_sci_port scif0_platform_data = {
39 .mapbase = 0xe6c40000,
40 .flags = UPF_BOOT_AUTOCONF,
41 .scscr = SCSCR_RE | SCSCR_TE,
42 .scbrr_algo_id = SCBRR_ALGO_4,
44 .irqs = { gic_spi(72), gic_spi(72),
45 gic_spi(72), gic_spi(72) },
48 static struct platform_device scif0_device = {
52 .platform_data = &scif0_platform_data,
56 static struct plat_sci_port scif1_platform_data = {
57 .mapbase = 0xe6c50000,
58 .flags = UPF_BOOT_AUTOCONF,
59 .scscr = SCSCR_RE | SCSCR_TE,
60 .scbrr_algo_id = SCBRR_ALGO_4,
62 .irqs = { gic_spi(73), gic_spi(73),
63 gic_spi(73), gic_spi(73) },
66 static struct platform_device scif1_device = {
70 .platform_data = &scif1_platform_data,
74 static struct plat_sci_port scif2_platform_data = {
75 .mapbase = 0xe6c60000,
76 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE,
78 .scbrr_algo_id = SCBRR_ALGO_4,
80 .irqs = { gic_spi(74), gic_spi(74),
81 gic_spi(74), gic_spi(74) },
84 static struct platform_device scif2_device = {
88 .platform_data = &scif2_platform_data,
92 static struct plat_sci_port scif3_platform_data = {
93 .mapbase = 0xe6c70000,
94 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_RE | SCSCR_TE,
96 .scbrr_algo_id = SCBRR_ALGO_4,
98 .irqs = { gic_spi(75), gic_spi(75),
99 gic_spi(75), gic_spi(75) },
102 static struct platform_device scif3_device = {
106 .platform_data = &scif3_platform_data,
110 static struct plat_sci_port scif4_platform_data = {
111 .mapbase = 0xe6c80000,
112 .flags = UPF_BOOT_AUTOCONF,
113 .scscr = SCSCR_RE | SCSCR_TE,
114 .scbrr_algo_id = SCBRR_ALGO_4,
116 .irqs = { gic_spi(78), gic_spi(78),
117 gic_spi(78), gic_spi(78) },
120 static struct platform_device scif4_device = {
124 .platform_data = &scif4_platform_data,
128 static struct plat_sci_port scif5_platform_data = {
129 .mapbase = 0xe6cb0000,
130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_RE | SCSCR_TE,
132 .scbrr_algo_id = SCBRR_ALGO_4,
134 .irqs = { gic_spi(79), gic_spi(79),
135 gic_spi(79), gic_spi(79) },
138 static struct platform_device scif5_device = {
142 .platform_data = &scif5_platform_data,
146 static struct plat_sci_port scif6_platform_data = {
147 .mapbase = 0xe6cc0000,
148 .flags = UPF_BOOT_AUTOCONF,
149 .scscr = SCSCR_RE | SCSCR_TE,
150 .scbrr_algo_id = SCBRR_ALGO_4,
152 .irqs = { gic_spi(156), gic_spi(156),
153 gic_spi(156), gic_spi(156) },
156 static struct platform_device scif6_device = {
160 .platform_data = &scif6_platform_data,
164 static struct plat_sci_port scif7_platform_data = {
165 .mapbase = 0xe6cd0000,
166 .flags = UPF_BOOT_AUTOCONF,
167 .scscr = SCSCR_RE | SCSCR_TE,
168 .scbrr_algo_id = SCBRR_ALGO_4,
170 .irqs = { gic_spi(143), gic_spi(143),
171 gic_spi(143), gic_spi(143) },
174 static struct platform_device scif7_device = {
178 .platform_data = &scif7_platform_data,
182 static struct plat_sci_port scif8_platform_data = {
183 .mapbase = 0xe6c30000,
184 .flags = UPF_BOOT_AUTOCONF,
185 .scscr = SCSCR_RE | SCSCR_TE,
186 .scbrr_algo_id = SCBRR_ALGO_4,
188 .irqs = { gic_spi(80), gic_spi(80),
189 gic_spi(80), gic_spi(80) },
192 static struct platform_device scif8_device = {
196 .platform_data = &scif8_platform_data,
200 static struct sh_timer_config cmt10_platform_data = {
202 .channel_offset = 0x10,
204 .clockevent_rating = 125,
205 .clocksource_rating = 125,
208 static struct resource cmt10_resources[] = {
213 .flags = IORESOURCE_MEM,
216 .start = gic_spi(65),
217 .flags = IORESOURCE_IRQ,
221 static struct platform_device cmt10_device = {
225 .platform_data = &cmt10_platform_data,
227 .resource = cmt10_resources,
228 .num_resources = ARRAY_SIZE(cmt10_resources),
232 static struct sh_timer_config tmu00_platform_data = {
234 .channel_offset = 0x4,
236 .clockevent_rating = 200,
239 static struct resource tmu00_resources[] = {
244 .flags = IORESOURCE_MEM,
247 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
248 .flags = IORESOURCE_IRQ,
252 static struct platform_device tmu00_device = {
256 .platform_data = &tmu00_platform_data,
258 .resource = tmu00_resources,
259 .num_resources = ARRAY_SIZE(tmu00_resources),
262 static struct sh_timer_config tmu01_platform_data = {
264 .channel_offset = 0x10,
266 .clocksource_rating = 200,
269 static struct resource tmu01_resources[] = {
274 .flags = IORESOURCE_MEM,
277 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
278 .flags = IORESOURCE_IRQ,
282 static struct platform_device tmu01_device = {
286 .platform_data = &tmu01_platform_data,
288 .resource = tmu01_resources,
289 .num_resources = ARRAY_SIZE(tmu01_resources),
292 static struct resource i2c0_resources[] = {
296 .end = 0xe6820425 - 1,
297 .flags = IORESOURCE_MEM,
300 .start = gic_spi(167),
302 .flags = IORESOURCE_IRQ,
306 static struct resource i2c1_resources[] = {
310 .end = 0xe6822425 - 1,
311 .flags = IORESOURCE_MEM,
314 .start = gic_spi(51),
316 .flags = IORESOURCE_IRQ,
320 static struct resource i2c2_resources[] = {
324 .end = 0xe6824425 - 1,
325 .flags = IORESOURCE_MEM,
328 .start = gic_spi(171),
330 .flags = IORESOURCE_IRQ,
334 static struct resource i2c3_resources[] = {
338 .end = 0xe6826425 - 1,
339 .flags = IORESOURCE_MEM,
342 .start = gic_spi(183),
344 .flags = IORESOURCE_IRQ,
348 static struct resource i2c4_resources[] = {
352 .end = 0xe6828425 - 1,
353 .flags = IORESOURCE_MEM,
356 .start = gic_spi(187),
358 .flags = IORESOURCE_IRQ,
362 static struct platform_device i2c0_device = {
363 .name = "i2c-sh_mobile",
365 .resource = i2c0_resources,
366 .num_resources = ARRAY_SIZE(i2c0_resources),
369 static struct platform_device i2c1_device = {
370 .name = "i2c-sh_mobile",
372 .resource = i2c1_resources,
373 .num_resources = ARRAY_SIZE(i2c1_resources),
376 static struct platform_device i2c2_device = {
377 .name = "i2c-sh_mobile",
379 .resource = i2c2_resources,
380 .num_resources = ARRAY_SIZE(i2c2_resources),
383 static struct platform_device i2c3_device = {
384 .name = "i2c-sh_mobile",
386 .resource = i2c3_resources,
387 .num_resources = ARRAY_SIZE(i2c3_resources),
390 static struct platform_device i2c4_device = {
391 .name = "i2c-sh_mobile",
393 .resource = i2c4_resources,
394 .num_resources = ARRAY_SIZE(i2c4_resources),
397 /* Transmit sizes and respective CHCR register values */
408 /* log2(size / 8) - used to calculate number of transfers */
410 [XMIT_SZ_8BIT] = 0, \
411 [XMIT_SZ_16BIT] = 1, \
412 [XMIT_SZ_32BIT] = 2, \
413 [XMIT_SZ_64BIT] = 3, \
414 [XMIT_SZ_128BIT] = 4, \
415 [XMIT_SZ_256BIT] = 5, \
416 [XMIT_SZ_512BIT] = 6, \
419 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
420 #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
421 #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
423 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
425 .slave_id = SHDMA_SLAVE_SCIF0_TX,
427 .chcr = CHCR_TX(XMIT_SZ_8BIT),
430 .slave_id = SHDMA_SLAVE_SCIF0_RX,
432 .chcr = CHCR_RX(XMIT_SZ_8BIT),
435 .slave_id = SHDMA_SLAVE_SCIF1_TX,
437 .chcr = CHCR_TX(XMIT_SZ_8BIT),
440 .slave_id = SHDMA_SLAVE_SCIF1_RX,
442 .chcr = CHCR_RX(XMIT_SZ_8BIT),
445 .slave_id = SHDMA_SLAVE_SCIF2_TX,
447 .chcr = CHCR_TX(XMIT_SZ_8BIT),
450 .slave_id = SHDMA_SLAVE_SCIF2_RX,
452 .chcr = CHCR_RX(XMIT_SZ_8BIT),
455 .slave_id = SHDMA_SLAVE_SCIF3_TX,
457 .chcr = CHCR_TX(XMIT_SZ_8BIT),
460 .slave_id = SHDMA_SLAVE_SCIF3_RX,
462 .chcr = CHCR_RX(XMIT_SZ_8BIT),
465 .slave_id = SHDMA_SLAVE_SCIF4_TX,
467 .chcr = CHCR_TX(XMIT_SZ_8BIT),
470 .slave_id = SHDMA_SLAVE_SCIF4_RX,
472 .chcr = CHCR_RX(XMIT_SZ_8BIT),
475 .slave_id = SHDMA_SLAVE_SCIF5_TX,
477 .chcr = CHCR_TX(XMIT_SZ_8BIT),
480 .slave_id = SHDMA_SLAVE_SCIF5_RX,
482 .chcr = CHCR_RX(XMIT_SZ_8BIT),
485 .slave_id = SHDMA_SLAVE_SCIF6_TX,
487 .chcr = CHCR_TX(XMIT_SZ_8BIT),
490 .slave_id = SHDMA_SLAVE_SCIF6_RX,
492 .chcr = CHCR_RX(XMIT_SZ_8BIT),
495 .slave_id = SHDMA_SLAVE_SCIF7_TX,
497 .chcr = CHCR_TX(XMIT_SZ_8BIT),
500 .slave_id = SHDMA_SLAVE_SCIF7_RX,
502 .chcr = CHCR_RX(XMIT_SZ_8BIT),
505 .slave_id = SHDMA_SLAVE_SCIF8_TX,
507 .chcr = CHCR_TX(XMIT_SZ_8BIT),
510 .slave_id = SHDMA_SLAVE_SCIF8_RX,
512 .chcr = CHCR_RX(XMIT_SZ_8BIT),
515 .slave_id = SHDMA_SLAVE_SDHI0_TX,
517 .chcr = CHCR_TX(XMIT_SZ_16BIT),
520 .slave_id = SHDMA_SLAVE_SDHI0_RX,
522 .chcr = CHCR_RX(XMIT_SZ_16BIT),
525 .slave_id = SHDMA_SLAVE_SDHI1_TX,
527 .chcr = CHCR_TX(XMIT_SZ_16BIT),
530 .slave_id = SHDMA_SLAVE_SDHI1_RX,
532 .chcr = CHCR_RX(XMIT_SZ_16BIT),
535 .slave_id = SHDMA_SLAVE_SDHI2_TX,
537 .chcr = CHCR_TX(XMIT_SZ_16BIT),
540 .slave_id = SHDMA_SLAVE_SDHI2_RX,
542 .chcr = CHCR_RX(XMIT_SZ_16BIT),
545 .slave_id = SHDMA_SLAVE_MMCIF_TX,
547 .chcr = CHCR_TX(XMIT_SZ_32BIT),
550 .slave_id = SHDMA_SLAVE_MMCIF_RX,
552 .chcr = CHCR_RX(XMIT_SZ_32BIT),
557 #define DMAE_CHANNEL(_offset) \
559 .offset = _offset - 0x20, \
560 .dmars = _offset - 0x20 + 0x40, \
563 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
564 DMAE_CHANNEL(0x8000),
565 DMAE_CHANNEL(0x8080),
566 DMAE_CHANNEL(0x8100),
567 DMAE_CHANNEL(0x8180),
568 DMAE_CHANNEL(0x8200),
569 DMAE_CHANNEL(0x8280),
570 DMAE_CHANNEL(0x8300),
571 DMAE_CHANNEL(0x8380),
572 DMAE_CHANNEL(0x8400),
573 DMAE_CHANNEL(0x8480),
574 DMAE_CHANNEL(0x8500),
575 DMAE_CHANNEL(0x8580),
576 DMAE_CHANNEL(0x8600),
577 DMAE_CHANNEL(0x8680),
578 DMAE_CHANNEL(0x8700),
579 DMAE_CHANNEL(0x8780),
580 DMAE_CHANNEL(0x8800),
581 DMAE_CHANNEL(0x8880),
582 DMAE_CHANNEL(0x8900),
583 DMAE_CHANNEL(0x8980),
586 static const unsigned int ts_shift[] = TS_SHIFT;
588 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
589 .slave = sh73a0_dmae_slaves,
590 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
591 .channel = sh73a0_dmae_channels,
592 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
595 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
596 .ts_high_mask = 0x00300000,
597 .ts_shift = ts_shift,
598 .ts_shift_num = ARRAY_SIZE(ts_shift),
599 .dmaor_init = DMAOR_DME,
602 static struct resource sh73a0_dmae_resources[] = {
604 /* Registers including DMAOR and channels including DMARSx */
606 .end = 0xfe008a00 - 1,
607 .flags = IORESOURCE_MEM,
611 .start = gic_spi(129),
613 .flags = IORESOURCE_IRQ,
616 /* IRQ for channels 0-19 */
617 .start = gic_spi(109),
619 .flags = IORESOURCE_IRQ,
623 static struct platform_device dma0_device = {
624 .name = "sh-dma-engine",
626 .resource = sh73a0_dmae_resources,
627 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
629 .platform_data = &sh73a0_dmae_platform_data,
633 static struct platform_device *sh73a0_early_devices[] __initdata = {
648 static struct platform_device *sh73a0_late_devices[] __initdata = {
657 #define SRCR2 0xe61580b0
659 void __init sh73a0_add_standard_devices(void)
661 /* Clear software reset bit on SY-DMAC module */
662 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
664 platform_add_devices(sh73a0_early_devices,
665 ARRAY_SIZE(sh73a0_early_devices));
666 platform_add_devices(sh73a0_late_devices,
667 ARRAY_SIZE(sh73a0_late_devices));
670 void __init sh73a0_add_early_devices(void)
672 early_platform_add_devices(sh73a0_early_devices,
673 ARRAY_SIZE(sh73a0_early_devices));