2 * arch/arm/mach-spear3xx/spear310.c
4 * SPEAr310 machine source file
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/ptrace.h>
16 #include <mach/generic.h>
17 #include <mach/spear.h>
18 #include <plat/shirq.h>
20 /* pad multiplexing support */
21 /* muxing registers */
22 #define PAD_MUX_CONFIG_REG 0x08
25 struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
28 .mask = PMX_TIMER_3_4_MASK,
32 struct pmx_dev pmx_emi_cs_0_1_4_5 = {
33 .name = "emi_cs_0_1_4_5",
34 .modes = pmx_emi_cs_0_1_4_5_modes,
35 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
39 struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
42 .mask = PMX_TIMER_1_2_MASK,
46 struct pmx_dev pmx_emi_cs_2_3 = {
48 .modes = pmx_emi_cs_2_3_modes,
49 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
53 struct pmx_dev_mode pmx_uart1_modes[] = {
56 .mask = PMX_FIRDA_MASK,
60 struct pmx_dev pmx_uart1 = {
62 .modes = pmx_uart1_modes,
63 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
67 struct pmx_dev_mode pmx_uart2_modes[] = {
70 .mask = PMX_TIMER_1_2_MASK,
74 struct pmx_dev pmx_uart2 = {
76 .modes = pmx_uart2_modes,
77 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
81 struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
84 .mask = PMX_UART0_MODEM_MASK,
88 struct pmx_dev pmx_uart3_4_5 = {
90 .modes = pmx_uart3_4_5_modes,
91 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
95 struct pmx_dev_mode pmx_fsmc_modes[] = {
98 .mask = PMX_SSP_CS_MASK,
102 struct pmx_dev pmx_fsmc = {
104 .modes = pmx_fsmc_modes,
105 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
109 struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
112 .mask = PMX_MII_MASK,
116 struct pmx_dev pmx_rs485_0_1 = {
118 .modes = pmx_rs485_0_1_modes,
119 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
123 struct pmx_dev_mode pmx_tdm0_modes[] = {
126 .mask = PMX_MII_MASK,
130 struct pmx_dev pmx_tdm0 = {
132 .modes = pmx_tdm0_modes,
133 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
137 /* pmx driver structure */
138 struct pmx_driver pmx_driver = {
139 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
142 /* Add spear310 specific devices here */
144 /* spear3xx shared irq */
145 struct shirq_dev_config shirq_ras1_config[] = {
148 .status_mask = SMII0_IRQ_MASK,
151 .status_mask = SMII1_IRQ_MASK,
154 .status_mask = SMII2_IRQ_MASK,
157 .status_mask = SMII3_IRQ_MASK,
159 .virq = VIRQ_WAKEUP_SMII0,
160 .status_mask = WAKEUP_SMII0_IRQ_MASK,
162 .virq = VIRQ_WAKEUP_SMII1,
163 .status_mask = WAKEUP_SMII1_IRQ_MASK,
165 .virq = VIRQ_WAKEUP_SMII2,
166 .status_mask = WAKEUP_SMII2_IRQ_MASK,
168 .virq = VIRQ_WAKEUP_SMII3,
169 .status_mask = WAKEUP_SMII3_IRQ_MASK,
173 struct spear_shirq shirq_ras1 = {
174 .irq = IRQ_GEN_RAS_1,
175 .dev_config = shirq_ras1_config,
176 .dev_count = ARRAY_SIZE(shirq_ras1_config),
179 .status_reg = INT_STS_MASK_REG,
180 .status_reg_mask = SHIRQ_RAS1_MASK,
185 struct shirq_dev_config shirq_ras2_config[] = {
188 .status_mask = UART1_IRQ_MASK,
191 .status_mask = UART2_IRQ_MASK,
194 .status_mask = UART3_IRQ_MASK,
197 .status_mask = UART4_IRQ_MASK,
200 .status_mask = UART5_IRQ_MASK,
204 struct spear_shirq shirq_ras2 = {
205 .irq = IRQ_GEN_RAS_2,
206 .dev_config = shirq_ras2_config,
207 .dev_count = ARRAY_SIZE(shirq_ras2_config),
210 .status_reg = INT_STS_MASK_REG,
211 .status_reg_mask = SHIRQ_RAS2_MASK,
216 struct shirq_dev_config shirq_ras3_config[] = {
219 .status_mask = EMI_IRQ_MASK,
223 struct spear_shirq shirq_ras3 = {
224 .irq = IRQ_GEN_RAS_3,
225 .dev_config = shirq_ras3_config,
226 .dev_count = ARRAY_SIZE(shirq_ras3_config),
229 .status_reg = INT_STS_MASK_REG,
230 .status_reg_mask = SHIRQ_RAS3_MASK,
235 struct shirq_dev_config shirq_intrcomm_ras_config[] = {
237 .virq = VIRQ_TDM_HDLC,
238 .status_mask = TDM_HDLC_IRQ_MASK,
240 .virq = VIRQ_RS485_0,
241 .status_mask = RS485_0_IRQ_MASK,
243 .virq = VIRQ_RS485_1,
244 .status_mask = RS485_1_IRQ_MASK,
248 struct spear_shirq shirq_intrcomm_ras = {
249 .irq = IRQ_INTRCOMM_RAS_ARM,
250 .dev_config = shirq_intrcomm_ras_config,
251 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
254 .status_reg = INT_STS_MASK_REG,
255 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
260 /* spear310 routines */
261 void __init spear310_init(void)
266 /* call spear3xx family common init function */
269 /* shared irq registeration */
270 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE);
273 shirq_ras1.regs.base = base;
274 ret = spear_shirq_register(&shirq_ras1);
276 printk(KERN_ERR "Error registering Shared IRQ 1\n");
279 shirq_ras2.regs.base = base;
280 ret = spear_shirq_register(&shirq_ras2);
282 printk(KERN_ERR "Error registering Shared IRQ 2\n");
285 shirq_ras3.regs.base = base;
286 ret = spear_shirq_register(&shirq_ras3);
288 printk(KERN_ERR "Error registering Shared IRQ 3\n");
291 shirq_intrcomm_ras.regs.base = base;
292 ret = spear_shirq_register(&shirq_intrcomm_ras);
294 printk(KERN_ERR "Error registering Shared IRQ 4\n");
298 void spear310_pmx_init(void)
300 spear_pmx_init(&pmx_driver, SPEAR310_SOC_CONFIG_BASE,
301 SPEAR310_SOC_CONFIG_SIZE);