2 * arch/arm/mach-spear3xx/spear310.c
4 * SPEAr310 machine source file
6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #define pr_fmt(fmt) "SPEAr310: " fmt
16 #include <linux/amba/pl08x.h>
17 #include <linux/amba/serial.h>
18 #include <linux/of_platform.h>
19 #include <asm/hardware/vic.h>
20 #include <asm/mach/arch.h>
21 #include <plat/shirq.h>
22 #include <mach/generic.h>
23 #include <mach/spear.h>
25 #define SPEAR310_UART1_BASE UL(0xB2000000)
26 #define SPEAR310_UART2_BASE UL(0xB2080000)
27 #define SPEAR310_UART3_BASE UL(0xB2100000)
28 #define SPEAR310_UART4_BASE UL(0xB2180000)
29 #define SPEAR310_UART5_BASE UL(0xB2200000)
30 #define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
32 /* Interrupt registers offsets and masks */
33 #define SPEAR310_INT_STS_MASK_REG 0x04
34 #define SPEAR310_SMII0_IRQ_MASK (1 << 0)
35 #define SPEAR310_SMII1_IRQ_MASK (1 << 1)
36 #define SPEAR310_SMII2_IRQ_MASK (1 << 2)
37 #define SPEAR310_SMII3_IRQ_MASK (1 << 3)
38 #define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
39 #define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
40 #define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
41 #define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
42 #define SPEAR310_UART1_IRQ_MASK (1 << 8)
43 #define SPEAR310_UART2_IRQ_MASK (1 << 9)
44 #define SPEAR310_UART3_IRQ_MASK (1 << 10)
45 #define SPEAR310_UART4_IRQ_MASK (1 << 11)
46 #define SPEAR310_UART5_IRQ_MASK (1 << 12)
47 #define SPEAR310_EMI_IRQ_MASK (1 << 13)
48 #define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
49 #define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
50 #define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
52 #define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
53 #define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
54 #define SPEAR310_SHIRQ_RAS3_MASK 0x02000
55 #define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
57 /* SPEAr310 Virtual irq definitions */
58 /* IRQs sharing IRQ_GEN_RAS_1 */
59 #define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
60 #define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
61 #define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
62 #define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
63 #define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
64 #define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
65 #define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
66 #define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
68 /* IRQs sharing IRQ_GEN_RAS_2 */
69 #define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
70 #define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
71 #define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
72 #define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
73 #define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
75 /* IRQs sharing IRQ_GEN_RAS_3 */
76 #define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
77 #define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
79 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
80 #define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
81 #define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
82 #define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
85 /* spear3xx shared irq */
86 static struct shirq_dev_config shirq_ras1_config[] = {
88 .virq = SPEAR310_VIRQ_SMII0,
89 .status_mask = SPEAR310_SMII0_IRQ_MASK,
91 .virq = SPEAR310_VIRQ_SMII1,
92 .status_mask = SPEAR310_SMII1_IRQ_MASK,
94 .virq = SPEAR310_VIRQ_SMII2,
95 .status_mask = SPEAR310_SMII2_IRQ_MASK,
97 .virq = SPEAR310_VIRQ_SMII3,
98 .status_mask = SPEAR310_SMII3_IRQ_MASK,
100 .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
101 .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
103 .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
104 .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
106 .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
107 .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
109 .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
110 .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
114 static struct spear_shirq shirq_ras1 = {
115 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
116 .dev_config = shirq_ras1_config,
117 .dev_count = ARRAY_SIZE(shirq_ras1_config),
120 .status_reg = SPEAR310_INT_STS_MASK_REG,
121 .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
126 static struct shirq_dev_config shirq_ras2_config[] = {
128 .virq = SPEAR310_VIRQ_UART1,
129 .status_mask = SPEAR310_UART1_IRQ_MASK,
131 .virq = SPEAR310_VIRQ_UART2,
132 .status_mask = SPEAR310_UART2_IRQ_MASK,
134 .virq = SPEAR310_VIRQ_UART3,
135 .status_mask = SPEAR310_UART3_IRQ_MASK,
137 .virq = SPEAR310_VIRQ_UART4,
138 .status_mask = SPEAR310_UART4_IRQ_MASK,
140 .virq = SPEAR310_VIRQ_UART5,
141 .status_mask = SPEAR310_UART5_IRQ_MASK,
145 static struct spear_shirq shirq_ras2 = {
146 .irq = SPEAR3XX_IRQ_GEN_RAS_2,
147 .dev_config = shirq_ras2_config,
148 .dev_count = ARRAY_SIZE(shirq_ras2_config),
151 .status_reg = SPEAR310_INT_STS_MASK_REG,
152 .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
157 static struct shirq_dev_config shirq_ras3_config[] = {
159 .virq = SPEAR310_VIRQ_EMI,
160 .status_mask = SPEAR310_EMI_IRQ_MASK,
164 static struct spear_shirq shirq_ras3 = {
165 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
166 .dev_config = shirq_ras3_config,
167 .dev_count = ARRAY_SIZE(shirq_ras3_config),
170 .status_reg = SPEAR310_INT_STS_MASK_REG,
171 .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
176 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
178 .virq = SPEAR310_VIRQ_TDM_HDLC,
179 .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
181 .virq = SPEAR310_VIRQ_RS485_0,
182 .status_mask = SPEAR310_RS485_0_IRQ_MASK,
184 .virq = SPEAR310_VIRQ_RS485_1,
185 .status_mask = SPEAR310_RS485_1_IRQ_MASK,
189 static struct spear_shirq shirq_intrcomm_ras = {
190 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
191 .dev_config = shirq_intrcomm_ras_config,
192 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
195 .status_reg = SPEAR310_INT_STS_MASK_REG,
196 .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
201 /* DMAC platform data's slave info */
202 struct pl08x_channel_data spear310_dma_info[] = {
204 .bus_id = "uart0_rx",
208 .periph_buses = PL08X_AHB1,
210 .bus_id = "uart0_tx",
214 .periph_buses = PL08X_AHB1,
220 .periph_buses = PL08X_AHB1,
226 .periph_buses = PL08X_AHB1,
232 .periph_buses = PL08X_AHB1,
238 .periph_buses = PL08X_AHB1,
244 .periph_buses = PL08X_AHB1,
250 .periph_buses = PL08X_AHB1,
256 .periph_buses = PL08X_AHB1,
258 .bus_id = "from_jpeg",
262 .periph_buses = PL08X_AHB1,
264 .bus_id = "uart1_rx",
268 .periph_buses = PL08X_AHB1,
270 .bus_id = "uart1_tx",
274 .periph_buses = PL08X_AHB1,
276 .bus_id = "uart2_rx",
280 .periph_buses = PL08X_AHB1,
282 .bus_id = "uart2_tx",
286 .periph_buses = PL08X_AHB1,
288 .bus_id = "uart3_rx",
292 .periph_buses = PL08X_AHB1,
294 .bus_id = "uart3_tx",
298 .periph_buses = PL08X_AHB1,
300 .bus_id = "uart4_rx",
304 .periph_buses = PL08X_AHB1,
306 .bus_id = "uart4_tx",
310 .periph_buses = PL08X_AHB1,
312 .bus_id = "uart5_rx",
316 .periph_buses = PL08X_AHB1,
318 .bus_id = "uart5_tx",
322 .periph_buses = PL08X_AHB1,
328 .periph_buses = PL08X_AHB1,
334 .periph_buses = PL08X_AHB1,
340 .periph_buses = PL08X_AHB1,
346 .periph_buses = PL08X_AHB1,
352 .periph_buses = PL08X_AHB1,
358 .periph_buses = PL08X_AHB1,
362 /* uart devices plat data */
363 static struct amba_pl011_data spear310_uart_data[] = {
365 .dma_filter = pl08x_filter_id,
366 .dma_tx_param = "uart1_tx",
367 .dma_rx_param = "uart1_rx",
369 .dma_filter = pl08x_filter_id,
370 .dma_tx_param = "uart2_tx",
371 .dma_rx_param = "uart2_rx",
373 .dma_filter = pl08x_filter_id,
374 .dma_tx_param = "uart3_tx",
375 .dma_rx_param = "uart3_rx",
377 .dma_filter = pl08x_filter_id,
378 .dma_tx_param = "uart4_tx",
379 .dma_rx_param = "uart4_rx",
381 .dma_filter = pl08x_filter_id,
382 .dma_tx_param = "uart5_tx",
383 .dma_rx_param = "uart5_rx",
387 /* Add SPEAr310 auxdata to pass platform data */
388 static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
389 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
391 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
393 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
394 &spear310_uart_data[0]),
395 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
396 &spear310_uart_data[1]),
397 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
398 &spear310_uart_data[2]),
399 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
400 &spear310_uart_data[3]),
401 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
402 &spear310_uart_data[4]),
406 static void __init spear310_dt_init(void)
411 pl080_plat_data.slave_channels = spear310_dma_info;
412 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
414 of_platform_populate(NULL, of_default_bus_match_table,
415 spear310_auxdata_lookup, NULL);
417 /* shared irq registration */
418 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
421 shirq_ras1.regs.base = base;
422 ret = spear_shirq_register(&shirq_ras1);
424 pr_err("Error registering Shared IRQ 1\n");
427 shirq_ras2.regs.base = base;
428 ret = spear_shirq_register(&shirq_ras2);
430 pr_err("Error registering Shared IRQ 2\n");
433 shirq_ras3.regs.base = base;
434 ret = spear_shirq_register(&shirq_ras3);
436 pr_err("Error registering Shared IRQ 3\n");
439 shirq_intrcomm_ras.regs.base = base;
440 ret = spear_shirq_register(&shirq_intrcomm_ras);
442 pr_err("Error registering Shared IRQ 4\n");
446 static const char * const spear310_dt_board_compat[] = {
452 static void __init spear310_map_io(void)
457 DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
458 .map_io = spear310_map_io,
459 .init_irq = spear3xx_dt_init_irq,
460 .handle_irq = vic_handle_irq,
461 .timer = &spear3xx_timer,
462 .init_machine = spear310_dt_init,
463 .restart = spear_restart,
464 .dt_compat = spear310_dt_board_compat,