arch/arm/mach-spear3xx/spear320.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear320.c
   3  *
   4  * SPEAr320 machine source file
   5  *
   6  * Copyright (C) 2009-2012 ST Microelectronics
   7  * Viresh Kumar <viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) "SPEAr320: " fmt
  15
  16 #include <linux/amba/pl022.h>
  17 #include <linux/amba/pl08x.h>
  18 #include <linux/amba/serial.h>
  19 #include <linux/of_platform.h>
  20 #include <asm/hardware/vic.h>
  21 #include <asm/mach/arch.h>
  22 #include <plat/shirq.h>
  23 #include <mach/generic.h>
  24 #include <mach/spear.h>
  25
  26 #define SPEAR320_UART1_BASE             UL(0xA3000000)
  27 #define SPEAR320_UART2_BASE             UL(0xA4000000)
  28 #define SPEAR320_SSP0_BASE              UL(0xA5000000)
  29 #define SPEAR320_SSP1_BASE              UL(0xA6000000)
  30 #define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
  31
  32 /* Interrupt registers offsets and masks */
  33 #define SPEAR320_INT_STS_MASK_REG               0x04
  34 #define SPEAR320_INT_CLR_MASK_REG               0x04
  35 #define SPEAR320_INT_ENB_MASK_REG               0x08
  36 #define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
  37 #define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
  38 #define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
  39 #define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
  40 #define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
  41 #define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
  42 #define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
  43 #define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
  44 #define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
  45 #define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
  46 #define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
  47 #define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
  48 #define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
  49 #define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
  50 #define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
  51 #define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
  52 #define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
  53 #define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
  54
  55 #define SPEAR320_SHIRQ_RAS1_MASK                0x000380
  56 #define SPEAR320_SHIRQ_RAS3_MASK                0x000007
  57 #define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
  58
  59 /* SPEAr320 Virtual irq definitions */
  60 /* IRQs sharing IRQ_GEN_RAS_1 */
  61 #define SPEAR320_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 0)
  62 #define SPEAR320_VIRQ_CLCD                      (SPEAR3XX_VIRQ_START + 1)
  63 #define SPEAR320_VIRQ_SPP                       (SPEAR3XX_VIRQ_START + 2)
  64
  65 /* IRQs sharing IRQ_GEN_RAS_2 */
  66 #define SPEAR320_IRQ_SDHCI                      SPEAR3XX_IRQ_GEN_RAS_2
  67
  68 /* IRQs sharing IRQ_GEN_RAS_3 */
  69 #define SPEAR320_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 3)
  70 #define SPEAR320_VIRQ_I2S_PLAY                  (SPEAR3XX_VIRQ_START + 4)
  71 #define SPEAR320_VIRQ_I2S_REC                   (SPEAR3XX_VIRQ_START + 5)
  72
  73 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
  74 #define SPEAR320_VIRQ_CANU                      (SPEAR3XX_VIRQ_START + 6)
  75 #define SPEAR320_VIRQ_CANL                      (SPEAR3XX_VIRQ_START + 7)
  76 #define SPEAR320_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
  77 #define SPEAR320_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
  78 #define SPEAR320_VIRQ_SSP1                      (SPEAR3XX_VIRQ_START + 10)
  79 #define SPEAR320_VIRQ_SSP2                      (SPEAR3XX_VIRQ_START + 11)
  80 #define SPEAR320_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 12)
  81 #define SPEAR320_VIRQ_MII1_SMII1                (SPEAR3XX_VIRQ_START + 13)
  82 #define SPEAR320_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 14)
  83 #define SPEAR320_VIRQ_WAKEUP_MII1_SMII1         (SPEAR3XX_VIRQ_START + 15)
  84 #define SPEAR320_VIRQ_I2C1                      (SPEAR3XX_VIRQ_START + 16)
  85
  86 /* spear3xx shared irq */
  87 static struct shirq_dev_config shirq_ras1_config[] = {
  88         {
  89                 .virq = SPEAR320_VIRQ_EMI,
  90                 .status_mask = SPEAR320_EMI_IRQ_MASK,
  91                 .clear_mask = SPEAR320_EMI_IRQ_MASK,
  92         }, {
  93                 .virq = SPEAR320_VIRQ_CLCD,
  94                 .status_mask = SPEAR320_CLCD_IRQ_MASK,
  95                 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
  96         }, {
  97                 .virq = SPEAR320_VIRQ_SPP,
  98                 .status_mask = SPEAR320_SPP_IRQ_MASK,
  99                 .clear_mask = SPEAR320_SPP_IRQ_MASK,
 100         },
 101 };
 102
 103 static struct spear_shirq shirq_ras1 = {
 104         .irq = SPEAR3XX_IRQ_GEN_RAS_1,
 105         .dev_config = shirq_ras1_config,
 106         .dev_count = ARRAY_SIZE(shirq_ras1_config),
 107         .regs = {
 108                 .enb_reg = -1,
 109                 .status_reg = SPEAR320_INT_STS_MASK_REG,
 110                 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
 111                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
 112                 .reset_to_clear = 1,
 113         },
 114 };
 115
 116 static struct shirq_dev_config shirq_ras3_config[] = {
 117         {
 118                 .virq = SPEAR320_VIRQ_PLGPIO,
 119                 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
 120                 .status_mask = SPEAR320_GPIO_IRQ_MASK,
 121                 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
 122         }, {
 123                 .virq = SPEAR320_VIRQ_I2S_PLAY,
 124                 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
 125                 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
 126                 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
 127         }, {
 128                 .virq = SPEAR320_VIRQ_I2S_REC,
 129                 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
 130                 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
 131                 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
 132         },
 133 };
 134
 135 static struct spear_shirq shirq_ras3 = {
 136         .irq = SPEAR3XX_IRQ_GEN_RAS_3,
 137         .dev_config = shirq_ras3_config,
 138         .dev_count = ARRAY_SIZE(shirq_ras3_config),
 139         .regs = {
 140                 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
 141                 .reset_to_enb = 1,
 142                 .status_reg = SPEAR320_INT_STS_MASK_REG,
 143                 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
 144                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
 145                 .reset_to_clear = 1,
 146         },
 147 };
 148
 149 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 150         {
 151                 .virq = SPEAR320_VIRQ_CANU,
 152                 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
 153                 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
 154         }, {
 155                 .virq = SPEAR320_VIRQ_CANL,
 156                 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
 157                 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
 158         }, {
 159                 .virq = SPEAR320_VIRQ_UART1,
 160                 .status_mask = SPEAR320_UART1_IRQ_MASK,
 161                 .clear_mask = SPEAR320_UART1_IRQ_MASK,
 162         }, {
 163                 .virq = SPEAR320_VIRQ_UART2,
 164                 .status_mask = SPEAR320_UART2_IRQ_MASK,
 165                 .clear_mask = SPEAR320_UART2_IRQ_MASK,
 166         }, {
 167                 .virq = SPEAR320_VIRQ_SSP1,
 168                 .status_mask = SPEAR320_SSP1_IRQ_MASK,
 169                 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
 170         }, {
 171                 .virq = SPEAR320_VIRQ_SSP2,
 172                 .status_mask = SPEAR320_SSP2_IRQ_MASK,
 173                 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
 174         }, {
 175                 .virq = SPEAR320_VIRQ_SMII0,
 176                 .status_mask = SPEAR320_SMII0_IRQ_MASK,
 177                 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
 178         }, {
 179                 .virq = SPEAR320_VIRQ_MII1_SMII1,
 180                 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
 181                 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
 182         }, {
 183                 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
 184                 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
 185                 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
 186         }, {
 187                 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
 188                 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
 189                 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
 190         }, {
 191                 .virq = SPEAR320_VIRQ_I2C1,
 192                 .status_mask = SPEAR320_I2C1_IRQ_MASK,
 193                 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
 194         },
 195 };
 196
 197 static struct spear_shirq shirq_intrcomm_ras = {
 198         .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
 199         .dev_config = shirq_intrcomm_ras_config,
 200         .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
 201         .regs = {
 202                 .enb_reg = -1,
 203                 .status_reg = SPEAR320_INT_STS_MASK_REG,
 204                 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
 205                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
 206                 .reset_to_clear = 1,
 207         },
 208 };
 209
 210 /* DMAC platform data's slave info */
 211 struct pl08x_channel_data spear320_dma_info[] = {
 212         {
 213                 .bus_id = "uart0_rx",
 214                 .min_signal = 2,
 215                 .max_signal = 2,
 216                 .muxval = 0,
 217                 .cctl = 0,
 218                 .periph_buses = PL08X_AHB1,
 219         }, {
 220                 .bus_id = "uart0_tx",
 221                 .min_signal = 3,
 222                 .max_signal = 3,
 223                 .muxval = 0,
 224                 .cctl = 0,
 225                 .periph_buses = PL08X_AHB1,
 226         }, {
 227                 .bus_id = "ssp0_rx",
 228                 .min_signal = 8,
 229                 .max_signal = 8,
 230                 .muxval = 0,
 231                 .cctl = 0,
 232                 .periph_buses = PL08X_AHB1,
 233         }, {
 234                 .bus_id = "ssp0_tx",
 235                 .min_signal = 9,
 236                 .max_signal = 9,
 237                 .muxval = 0,
 238                 .cctl = 0,
 239                 .periph_buses = PL08X_AHB1,
 240         }, {
 241                 .bus_id = "i2c0_rx",
 242                 .min_signal = 10,
 243                 .max_signal = 10,
 244                 .muxval = 0,
 245                 .cctl = 0,
 246                 .periph_buses = PL08X_AHB1,
 247         }, {
 248                 .bus_id = "i2c0_tx",
 249                 .min_signal = 11,
 250                 .max_signal = 11,
 251                 .muxval = 0,
 252                 .cctl = 0,
 253                 .periph_buses = PL08X_AHB1,
 254         }, {
 255                 .bus_id = "irda",
 256                 .min_signal = 12,
 257                 .max_signal = 12,
 258                 .muxval = 0,
 259                 .cctl = 0,
 260                 .periph_buses = PL08X_AHB1,
 261         }, {
 262                 .bus_id = "adc",
 263                 .min_signal = 13,
 264                 .max_signal = 13,
 265                 .muxval = 0,
 266                 .cctl = 0,
 267                 .periph_buses = PL08X_AHB1,
 268         }, {
 269                 .bus_id = "to_jpeg",
 270                 .min_signal = 14,
 271                 .max_signal = 14,
 272                 .muxval = 0,
 273                 .cctl = 0,
 274                 .periph_buses = PL08X_AHB1,
 275         }, {
 276                 .bus_id = "from_jpeg",
 277                 .min_signal = 15,
 278                 .max_signal = 15,
 279                 .muxval = 0,
 280                 .cctl = 0,
 281                 .periph_buses = PL08X_AHB1,
 282         }, {
 283                 .bus_id = "ssp1_rx",
 284                 .min_signal = 0,
 285                 .max_signal = 0,
 286                 .muxval = 1,
 287                 .cctl = 0,
 288                 .periph_buses = PL08X_AHB2,
 289         }, {
 290                 .bus_id = "ssp1_tx",
 291                 .min_signal = 1,
 292                 .max_signal = 1,
 293                 .muxval = 1,
 294                 .cctl = 0,
 295                 .periph_buses = PL08X_AHB2,
 296         }, {
 297                 .bus_id = "ssp2_rx",
 298                 .min_signal = 2,
 299                 .max_signal = 2,
 300                 .muxval = 1,
 301                 .cctl = 0,
 302                 .periph_buses = PL08X_AHB2,
 303         }, {
 304                 .bus_id = "ssp2_tx",
 305                 .min_signal = 3,
 306                 .max_signal = 3,
 307                 .muxval = 1,
 308                 .cctl = 0,
 309                 .periph_buses = PL08X_AHB2,
 310         }, {
 311                 .bus_id = "uart1_rx",
 312                 .min_signal = 4,
 313                 .max_signal = 4,
 314                 .muxval = 1,
 315                 .cctl = 0,
 316                 .periph_buses = PL08X_AHB2,
 317         }, {
 318                 .bus_id = "uart1_tx",
 319                 .min_signal = 5,
 320                 .max_signal = 5,
 321                 .muxval = 1,
 322                 .cctl = 0,
 323                 .periph_buses = PL08X_AHB2,
 324         }, {
 325                 .bus_id = "uart2_rx",
 326                 .min_signal = 6,
 327                 .max_signal = 6,
 328                 .muxval = 1,
 329                 .cctl = 0,
 330                 .periph_buses = PL08X_AHB2,
 331         }, {
 332                 .bus_id = "uart2_tx",
 333                 .min_signal = 7,
 334                 .max_signal = 7,
 335                 .muxval = 1,
 336                 .cctl = 0,
 337                 .periph_buses = PL08X_AHB2,
 338         }, {
 339                 .bus_id = "i2c1_rx",
 340                 .min_signal = 8,
 341                 .max_signal = 8,
 342                 .muxval = 1,
 343                 .cctl = 0,
 344                 .periph_buses = PL08X_AHB2,
 345         }, {
 346                 .bus_id = "i2c1_tx",
 347                 .min_signal = 9,
 348                 .max_signal = 9,
 349                 .muxval = 1,
 350                 .cctl = 0,
 351                 .periph_buses = PL08X_AHB2,
 352         }, {
 353                 .bus_id = "i2c2_rx",
 354                 .min_signal = 10,
 355                 .max_signal = 10,
 356                 .muxval = 1,
 357                 .cctl = 0,
 358                 .periph_buses = PL08X_AHB2,
 359         }, {
 360                 .bus_id = "i2c2_tx",
 361                 .min_signal = 11,
 362                 .max_signal = 11,
 363                 .muxval = 1,
 364                 .cctl = 0,
 365                 .periph_buses = PL08X_AHB2,
 366         }, {
 367                 .bus_id = "i2s_rx",
 368                 .min_signal = 12,
 369                 .max_signal = 12,
 370                 .muxval = 1,
 371                 .cctl = 0,
 372                 .periph_buses = PL08X_AHB2,
 373         }, {
 374                 .bus_id = "i2s_tx",
 375                 .min_signal = 13,
 376                 .max_signal = 13,
 377                 .muxval = 1,
 378                 .cctl = 0,
 379                 .periph_buses = PL08X_AHB2,
 380         }, {
 381                 .bus_id = "rs485_rx",
 382                 .min_signal = 14,
 383                 .max_signal = 14,
 384                 .muxval = 1,
 385                 .cctl = 0,
 386                 .periph_buses = PL08X_AHB2,
 387         }, {
 388                 .bus_id = "rs485_tx",
 389                 .min_signal = 15,
 390                 .max_signal = 15,
 391                 .muxval = 1,
 392                 .cctl = 0,
 393                 .periph_buses = PL08X_AHB2,
 394         },
 395 };
 396
 397 static struct pl022_ssp_controller spear320_ssp_data[] = {
 398         {
 399                 .bus_id = 1,
 400                 .enable_dma = 1,
 401                 .dma_filter = pl08x_filter_id,
 402                 .dma_tx_param = "ssp1_tx",
 403                 .dma_rx_param = "ssp1_rx",
 404                 .num_chipselect = 2,
 405         }, {
 406                 .bus_id = 2,
 407                 .enable_dma = 1,
 408                 .dma_filter = pl08x_filter_id,
 409                 .dma_tx_param = "ssp2_tx",
 410                 .dma_rx_param = "ssp2_rx",
 411                 .num_chipselect = 2,
 412         }
 413 };
 414
 415 static struct amba_pl011_data spear320_uart_data[] = {
 416         {
 417                 .dma_filter = pl08x_filter_id,
 418                 .dma_tx_param = "uart1_tx",
 419                 .dma_rx_param = "uart1_rx",
 420         }, {
 421                 .dma_filter = pl08x_filter_id,
 422                 .dma_tx_param = "uart2_tx",
 423                 .dma_rx_param = "uart2_rx",
 424         },
 425 };
 426
 427 /* Add SPEAr310 auxdata to pass platform data */
 428 static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
 429         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
 430                         &pl022_plat_data),
 431         OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
 432                         &pl080_plat_data),
 433         OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
 434                         &spear320_ssp_data[0]),
 435         OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
 436                         &spear320_ssp_data[1]),
 437         OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
 438                         &spear320_uart_data[0]),
 439         OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
 440                         &spear320_uart_data[1]),
 441         {}
 442 };
 443
 444 static void __init spear320_dt_init(void)
 445 {
 446         void __iomem *base;
 447         int ret;
 448
 449         pl080_plat_data.slave_channels = spear320_dma_info;
 450         pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
 451
 452         of_platform_populate(NULL, of_default_bus_match_table,
 453                         spear320_auxdata_lookup, NULL);
 454
 455         /* shared irq registration */
 456         base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
 457         if (base) {
 458                 /* shirq 1 */
 459                 shirq_ras1.regs.base = base;
 460                 ret = spear_shirq_register(&shirq_ras1);
 461                 if (ret)
 462                         pr_err("Error registering Shared IRQ 1\n");
 463
 464                 /* shirq 3 */
 465                 shirq_ras3.regs.base = base;
 466                 ret = spear_shirq_register(&shirq_ras3);
 467                 if (ret)
 468                         pr_err("Error registering Shared IRQ 3\n");
 469
 470                 /* shirq 4 */
 471                 shirq_intrcomm_ras.regs.base = base;
 472                 ret = spear_shirq_register(&shirq_intrcomm_ras);
 473                 if (ret)
 474                         pr_err("Error registering Shared IRQ 4\n");
 475         }
 476 }
 477
 478 static const char * const spear320_dt_board_compat[] = {
 479         "st,spear320",
 480         "st,spear320-evb",
 481         NULL,
 482 };
 483
 484 static void __init spear320_map_io(void)
 485 {
 486         spear3xx_map_io();
 487         spear320_clk_init();
 488 }
 489
 490 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
 491         .map_io         =       spear320_map_io,
 492         .init_irq       =       spear3xx_dt_init_irq,
 493         .handle_irq     =       vic_handle_irq,
 494         .timer          =       &spear3xx_timer,
 495         .init_machine   =       spear320_dt_init,
 496         .restart        =       spear_restart,
 497         .dt_compat      =       spear320_dt_board_compat,
 498 MACHINE_END