2 * arch/arm/mach-spear3xx/spear320.c
4 * SPEAr320 machine source file
6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #define pr_fmt(fmt) "SPEAr320: " fmt
16 #include <linux/amba/pl022.h>
17 #include <linux/amba/pl08x.h>
18 #include <linux/amba/serial.h>
19 #include <linux/of_platform.h>
20 #include <asm/hardware/vic.h>
21 #include <asm/mach/arch.h>
22 #include <plat/shirq.h>
23 #include <mach/generic.h>
24 #include <mach/spear.h>
26 #define SPEAR320_UART1_BASE UL(0xA3000000)
27 #define SPEAR320_UART2_BASE UL(0xA4000000)
28 #define SPEAR320_SSP0_BASE UL(0xA5000000)
29 #define SPEAR320_SSP1_BASE UL(0xA6000000)
30 #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
32 /* Interrupt registers offsets and masks */
33 #define SPEAR320_INT_STS_MASK_REG 0x04
34 #define SPEAR320_INT_CLR_MASK_REG 0x04
35 #define SPEAR320_INT_ENB_MASK_REG 0x08
36 #define SPEAR320_GPIO_IRQ_MASK (1 << 0)
37 #define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
38 #define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
39 #define SPEAR320_EMI_IRQ_MASK (1 << 7)
40 #define SPEAR320_CLCD_IRQ_MASK (1 << 8)
41 #define SPEAR320_SPP_IRQ_MASK (1 << 9)
42 #define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
43 #define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
44 #define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
45 #define SPEAR320_UART1_IRQ_MASK (1 << 13)
46 #define SPEAR320_UART2_IRQ_MASK (1 << 14)
47 #define SPEAR320_SSP1_IRQ_MASK (1 << 15)
48 #define SPEAR320_SSP2_IRQ_MASK (1 << 16)
49 #define SPEAR320_SMII0_IRQ_MASK (1 << 17)
50 #define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
51 #define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
52 #define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
53 #define SPEAR320_I2C1_IRQ_MASK (1 << 21)
55 #define SPEAR320_SHIRQ_RAS1_MASK 0x000380
56 #define SPEAR320_SHIRQ_RAS3_MASK 0x000007
57 #define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
59 /* SPEAr320 Virtual irq definitions */
60 /* IRQs sharing IRQ_GEN_RAS_1 */
61 #define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
62 #define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
63 #define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
65 /* IRQs sharing IRQ_GEN_RAS_2 */
66 #define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
68 /* IRQs sharing IRQ_GEN_RAS_3 */
69 #define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
70 #define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
71 #define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
73 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
74 #define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
75 #define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
76 #define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
77 #define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
78 #define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
79 #define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
80 #define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
81 #define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
82 #define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
83 #define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
84 #define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
86 /* spear3xx shared irq */
87 static struct shirq_dev_config shirq_ras1_config[] = {
89 .virq = SPEAR320_VIRQ_EMI,
90 .status_mask = SPEAR320_EMI_IRQ_MASK,
91 .clear_mask = SPEAR320_EMI_IRQ_MASK,
93 .virq = SPEAR320_VIRQ_CLCD,
94 .status_mask = SPEAR320_CLCD_IRQ_MASK,
95 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
97 .virq = SPEAR320_VIRQ_SPP,
98 .status_mask = SPEAR320_SPP_IRQ_MASK,
99 .clear_mask = SPEAR320_SPP_IRQ_MASK,
103 static struct spear_shirq shirq_ras1 = {
104 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
105 .dev_config = shirq_ras1_config,
106 .dev_count = ARRAY_SIZE(shirq_ras1_config),
109 .status_reg = SPEAR320_INT_STS_MASK_REG,
110 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
111 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
116 static struct shirq_dev_config shirq_ras3_config[] = {
118 .virq = SPEAR320_VIRQ_PLGPIO,
119 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
120 .status_mask = SPEAR320_GPIO_IRQ_MASK,
121 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
123 .virq = SPEAR320_VIRQ_I2S_PLAY,
124 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
125 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
126 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
128 .virq = SPEAR320_VIRQ_I2S_REC,
129 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
130 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
131 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
135 static struct spear_shirq shirq_ras3 = {
136 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
137 .dev_config = shirq_ras3_config,
138 .dev_count = ARRAY_SIZE(shirq_ras3_config),
140 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
142 .status_reg = SPEAR320_INT_STS_MASK_REG,
143 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
144 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
149 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
151 .virq = SPEAR320_VIRQ_CANU,
152 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
153 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
155 .virq = SPEAR320_VIRQ_CANL,
156 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
157 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
159 .virq = SPEAR320_VIRQ_UART1,
160 .status_mask = SPEAR320_UART1_IRQ_MASK,
161 .clear_mask = SPEAR320_UART1_IRQ_MASK,
163 .virq = SPEAR320_VIRQ_UART2,
164 .status_mask = SPEAR320_UART2_IRQ_MASK,
165 .clear_mask = SPEAR320_UART2_IRQ_MASK,
167 .virq = SPEAR320_VIRQ_SSP1,
168 .status_mask = SPEAR320_SSP1_IRQ_MASK,
169 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
171 .virq = SPEAR320_VIRQ_SSP2,
172 .status_mask = SPEAR320_SSP2_IRQ_MASK,
173 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
175 .virq = SPEAR320_VIRQ_SMII0,
176 .status_mask = SPEAR320_SMII0_IRQ_MASK,
177 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
179 .virq = SPEAR320_VIRQ_MII1_SMII1,
180 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
181 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
183 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
184 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
185 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
187 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
188 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
189 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
191 .virq = SPEAR320_VIRQ_I2C1,
192 .status_mask = SPEAR320_I2C1_IRQ_MASK,
193 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
197 static struct spear_shirq shirq_intrcomm_ras = {
198 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
199 .dev_config = shirq_intrcomm_ras_config,
200 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
203 .status_reg = SPEAR320_INT_STS_MASK_REG,
204 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
205 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
210 /* DMAC platform data's slave info */
211 struct pl08x_channel_data spear320_dma_info[] = {
213 .bus_id = "uart0_rx",
218 .periph_buses = PL08X_AHB1,
220 .bus_id = "uart0_tx",
225 .periph_buses = PL08X_AHB1,
232 .periph_buses = PL08X_AHB1,
239 .periph_buses = PL08X_AHB1,
246 .periph_buses = PL08X_AHB1,
253 .periph_buses = PL08X_AHB1,
260 .periph_buses = PL08X_AHB1,
267 .periph_buses = PL08X_AHB1,
274 .periph_buses = PL08X_AHB1,
276 .bus_id = "from_jpeg",
281 .periph_buses = PL08X_AHB1,
288 .periph_buses = PL08X_AHB2,
295 .periph_buses = PL08X_AHB2,
302 .periph_buses = PL08X_AHB2,
309 .periph_buses = PL08X_AHB2,
311 .bus_id = "uart1_rx",
316 .periph_buses = PL08X_AHB2,
318 .bus_id = "uart1_tx",
323 .periph_buses = PL08X_AHB2,
325 .bus_id = "uart2_rx",
330 .periph_buses = PL08X_AHB2,
332 .bus_id = "uart2_tx",
337 .periph_buses = PL08X_AHB2,
344 .periph_buses = PL08X_AHB2,
351 .periph_buses = PL08X_AHB2,
358 .periph_buses = PL08X_AHB2,
365 .periph_buses = PL08X_AHB2,
372 .periph_buses = PL08X_AHB2,
379 .periph_buses = PL08X_AHB2,
381 .bus_id = "rs485_rx",
386 .periph_buses = PL08X_AHB2,
388 .bus_id = "rs485_tx",
393 .periph_buses = PL08X_AHB2,
397 static struct pl022_ssp_controller spear320_ssp_data[] = {
401 .dma_filter = pl08x_filter_id,
402 .dma_tx_param = "ssp1_tx",
403 .dma_rx_param = "ssp1_rx",
408 .dma_filter = pl08x_filter_id,
409 .dma_tx_param = "ssp2_tx",
410 .dma_rx_param = "ssp2_rx",
415 static struct amba_pl011_data spear320_uart_data[] = {
417 .dma_filter = pl08x_filter_id,
418 .dma_tx_param = "uart1_tx",
419 .dma_rx_param = "uart1_rx",
421 .dma_filter = pl08x_filter_id,
422 .dma_tx_param = "uart2_tx",
423 .dma_rx_param = "uart2_rx",
427 /* Add SPEAr310 auxdata to pass platform data */
428 static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
429 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
431 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
433 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
434 &spear320_ssp_data[0]),
435 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
436 &spear320_ssp_data[1]),
437 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
438 &spear320_uart_data[0]),
439 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
440 &spear320_uart_data[1]),
444 static void __init spear320_dt_init(void)
449 pl080_plat_data.slave_channels = spear320_dma_info;
450 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
452 of_platform_populate(NULL, of_default_bus_match_table,
453 spear320_auxdata_lookup, NULL);
455 /* shared irq registration */
456 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
459 shirq_ras1.regs.base = base;
460 ret = spear_shirq_register(&shirq_ras1);
462 pr_err("Error registering Shared IRQ 1\n");
465 shirq_ras3.regs.base = base;
466 ret = spear_shirq_register(&shirq_ras3);
468 pr_err("Error registering Shared IRQ 3\n");
471 shirq_intrcomm_ras.regs.base = base;
472 ret = spear_shirq_register(&shirq_intrcomm_ras);
474 pr_err("Error registering Shared IRQ 4\n");
478 static const char * const spear320_dt_board_compat[] = {
484 static void __init spear320_map_io(void)
490 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
491 .map_io = spear320_map_io,
492 .init_irq = spear3xx_dt_init_irq,
493 .handle_irq = vic_handle_irq,
494 .timer = &spear3xx_timer,
495 .init_machine = spear320_dt_init,
496 .restart = spear_restart,
497 .dt_compat = spear320_dt_board_compat,