arch/arm/mach-spear3xx/spear320.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear320.c
   3  *
   4  * SPEAr320 machine source file
   5  *
   6  * Copyright (C) 2009-2012 ST Microelectronics
   7  * Viresh Kumar <viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) "SPEAr320: " fmt
  15
  16 #include <linux/amba/pl022.h>
  17 #include <linux/amba/pl08x.h>
  18 #include <linux/amba/serial.h>
  19 #include <linux/of_platform.h>
  20 #include <asm/hardware/vic.h>
  21 #include <asm/mach/arch.h>
  22 #include <plat/shirq.h>
  23 #include <mach/generic.h>
  24 #include <mach/hardware.h>
  25
  26 /* spear3xx shared irq */
  27 static struct shirq_dev_config shirq_ras1_config[] = {
  28         {
  29                 .virq = SPEAR320_VIRQ_EMI,
  30                 .status_mask = SPEAR320_EMI_IRQ_MASK,
  31                 .clear_mask = SPEAR320_EMI_IRQ_MASK,
  32         }, {
  33                 .virq = SPEAR320_VIRQ_CLCD,
  34                 .status_mask = SPEAR320_CLCD_IRQ_MASK,
  35                 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
  36         }, {
  37                 .virq = SPEAR320_VIRQ_SPP,
  38                 .status_mask = SPEAR320_SPP_IRQ_MASK,
  39                 .clear_mask = SPEAR320_SPP_IRQ_MASK,
  40         },
  41 };
  42
  43 static struct spear_shirq shirq_ras1 = {
  44         .irq = SPEAR3XX_IRQ_GEN_RAS_1,
  45         .dev_config = shirq_ras1_config,
  46         .dev_count = ARRAY_SIZE(shirq_ras1_config),
  47         .regs = {
  48                 .enb_reg = -1,
  49                 .status_reg = SPEAR320_INT_STS_MASK_REG,
  50                 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
  51                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
  52                 .reset_to_clear = 1,
  53         },
  54 };
  55
  56 static struct shirq_dev_config shirq_ras3_config[] = {
  57         {
  58                 .virq = SPEAR320_VIRQ_PLGPIO,
  59                 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
  60                 .status_mask = SPEAR320_GPIO_IRQ_MASK,
  61                 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
  62         }, {
  63                 .virq = SPEAR320_VIRQ_I2S_PLAY,
  64                 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
  65                 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
  66                 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
  67         }, {
  68                 .virq = SPEAR320_VIRQ_I2S_REC,
  69                 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
  70                 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
  71                 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
  72         },
  73 };
  74
  75 static struct spear_shirq shirq_ras3 = {
  76         .irq = SPEAR3XX_IRQ_GEN_RAS_3,
  77         .dev_config = shirq_ras3_config,
  78         .dev_count = ARRAY_SIZE(shirq_ras3_config),
  79         .regs = {
  80                 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
  81                 .reset_to_enb = 1,
  82                 .status_reg = SPEAR320_INT_STS_MASK_REG,
  83                 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
  84                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
  85                 .reset_to_clear = 1,
  86         },
  87 };
  88
  89 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
  90         {
  91                 .virq = SPEAR320_VIRQ_CANU,
  92                 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
  93                 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
  94         }, {
  95                 .virq = SPEAR320_VIRQ_CANL,
  96                 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
  97                 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
  98         }, {
  99                 .virq = SPEAR320_VIRQ_UART1,
 100                 .status_mask = SPEAR320_UART1_IRQ_MASK,
 101                 .clear_mask = SPEAR320_UART1_IRQ_MASK,
 102         }, {
 103                 .virq = SPEAR320_VIRQ_UART2,
 104                 .status_mask = SPEAR320_UART2_IRQ_MASK,
 105                 .clear_mask = SPEAR320_UART2_IRQ_MASK,
 106         }, {
 107                 .virq = SPEAR320_VIRQ_SSP1,
 108                 .status_mask = SPEAR320_SSP1_IRQ_MASK,
 109                 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
 110         }, {
 111                 .virq = SPEAR320_VIRQ_SSP2,
 112                 .status_mask = SPEAR320_SSP2_IRQ_MASK,
 113                 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
 114         }, {
 115                 .virq = SPEAR320_VIRQ_SMII0,
 116                 .status_mask = SPEAR320_SMII0_IRQ_MASK,
 117                 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
 118         }, {
 119                 .virq = SPEAR320_VIRQ_MII1_SMII1,
 120                 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
 121                 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
 122         }, {
 123                 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
 124                 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
 125                 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
 126         }, {
 127                 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
 128                 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
 129                 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
 130         }, {
 131                 .virq = SPEAR320_VIRQ_I2C1,
 132                 .status_mask = SPEAR320_I2C1_IRQ_MASK,
 133                 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
 134         },
 135 };
 136
 137 static struct spear_shirq shirq_intrcomm_ras = {
 138         .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
 139         .dev_config = shirq_intrcomm_ras_config,
 140         .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
 141         .regs = {
 142                 .enb_reg = -1,
 143                 .status_reg = SPEAR320_INT_STS_MASK_REG,
 144                 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
 145                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
 146                 .reset_to_clear = 1,
 147         },
 148 };
 149
 150 /* DMAC platform data's slave info */
 151 struct pl08x_channel_data spear320_dma_info[] = {
 152         {
 153                 .bus_id = "uart0_rx",
 154                 .min_signal = 2,
 155                 .max_signal = 2,
 156                 .muxval = 0,
 157                 .cctl = 0,
 158                 .periph_buses = PL08X_AHB1,
 159         }, {
 160                 .bus_id = "uart0_tx",
 161                 .min_signal = 3,
 162                 .max_signal = 3,
 163                 .muxval = 0,
 164                 .cctl = 0,
 165                 .periph_buses = PL08X_AHB1,
 166         }, {
 167                 .bus_id = "ssp0_rx",
 168                 .min_signal = 8,
 169                 .max_signal = 8,
 170                 .muxval = 0,
 171                 .cctl = 0,
 172                 .periph_buses = PL08X_AHB1,
 173         }, {
 174                 .bus_id = "ssp0_tx",
 175                 .min_signal = 9,
 176                 .max_signal = 9,
 177                 .muxval = 0,
 178                 .cctl = 0,
 179                 .periph_buses = PL08X_AHB1,
 180         }, {
 181                 .bus_id = "i2c0_rx",
 182                 .min_signal = 10,
 183                 .max_signal = 10,
 184                 .muxval = 0,
 185                 .cctl = 0,
 186                 .periph_buses = PL08X_AHB1,
 187         }, {
 188                 .bus_id = "i2c0_tx",
 189                 .min_signal = 11,
 190                 .max_signal = 11,
 191                 .muxval = 0,
 192                 .cctl = 0,
 193                 .periph_buses = PL08X_AHB1,
 194         }, {
 195                 .bus_id = "irda",
 196                 .min_signal = 12,
 197                 .max_signal = 12,
 198                 .muxval = 0,
 199                 .cctl = 0,
 200                 .periph_buses = PL08X_AHB1,
 201         }, {
 202                 .bus_id = "adc",
 203                 .min_signal = 13,
 204                 .max_signal = 13,
 205                 .muxval = 0,
 206                 .cctl = 0,
 207                 .periph_buses = PL08X_AHB1,
 208         }, {
 209                 .bus_id = "to_jpeg",
 210                 .min_signal = 14,
 211                 .max_signal = 14,
 212                 .muxval = 0,
 213                 .cctl = 0,
 214                 .periph_buses = PL08X_AHB1,
 215         }, {
 216                 .bus_id = "from_jpeg",
 217                 .min_signal = 15,
 218                 .max_signal = 15,
 219                 .muxval = 0,
 220                 .cctl = 0,
 221                 .periph_buses = PL08X_AHB1,
 222         }, {
 223                 .bus_id = "ssp1_rx",
 224                 .min_signal = 0,
 225                 .max_signal = 0,
 226                 .muxval = 1,
 227                 .cctl = 0,
 228                 .periph_buses = PL08X_AHB2,
 229         }, {
 230                 .bus_id = "ssp1_tx",
 231                 .min_signal = 1,
 232                 .max_signal = 1,
 233                 .muxval = 1,
 234                 .cctl = 0,
 235                 .periph_buses = PL08X_AHB2,
 236         }, {
 237                 .bus_id = "ssp2_rx",
 238                 .min_signal = 2,
 239                 .max_signal = 2,
 240                 .muxval = 1,
 241                 .cctl = 0,
 242                 .periph_buses = PL08X_AHB2,
 243         }, {
 244                 .bus_id = "ssp2_tx",
 245                 .min_signal = 3,
 246                 .max_signal = 3,
 247                 .muxval = 1,
 248                 .cctl = 0,
 249                 .periph_buses = PL08X_AHB2,
 250         }, {
 251                 .bus_id = "uart1_rx",
 252                 .min_signal = 4,
 253                 .max_signal = 4,
 254                 .muxval = 1,
 255                 .cctl = 0,
 256                 .periph_buses = PL08X_AHB2,
 257         }, {
 258                 .bus_id = "uart1_tx",
 259                 .min_signal = 5,
 260                 .max_signal = 5,
 261                 .muxval = 1,
 262                 .cctl = 0,
 263                 .periph_buses = PL08X_AHB2,
 264         }, {
 265                 .bus_id = "uart2_rx",
 266                 .min_signal = 6,
 267                 .max_signal = 6,
 268                 .muxval = 1,
 269                 .cctl = 0,
 270                 .periph_buses = PL08X_AHB2,
 271         }, {
 272                 .bus_id = "uart2_tx",
 273                 .min_signal = 7,
 274                 .max_signal = 7,
 275                 .muxval = 1,
 276                 .cctl = 0,
 277                 .periph_buses = PL08X_AHB2,
 278         }, {
 279                 .bus_id = "i2c1_rx",
 280                 .min_signal = 8,
 281                 .max_signal = 8,
 282                 .muxval = 1,
 283                 .cctl = 0,
 284                 .periph_buses = PL08X_AHB2,
 285         }, {
 286                 .bus_id = "i2c1_tx",
 287                 .min_signal = 9,
 288                 .max_signal = 9,
 289                 .muxval = 1,
 290                 .cctl = 0,
 291                 .periph_buses = PL08X_AHB2,
 292         }, {
 293                 .bus_id = "i2c2_rx",
 294                 .min_signal = 10,
 295                 .max_signal = 10,
 296                 .muxval = 1,
 297                 .cctl = 0,
 298                 .periph_buses = PL08X_AHB2,
 299         }, {
 300                 .bus_id = "i2c2_tx",
 301                 .min_signal = 11,
 302                 .max_signal = 11,
 303                 .muxval = 1,
 304                 .cctl = 0,
 305                 .periph_buses = PL08X_AHB2,
 306         }, {
 307                 .bus_id = "i2s_rx",
 308                 .min_signal = 12,
 309                 .max_signal = 12,
 310                 .muxval = 1,
 311                 .cctl = 0,
 312                 .periph_buses = PL08X_AHB2,
 313         }, {
 314                 .bus_id = "i2s_tx",
 315                 .min_signal = 13,
 316                 .max_signal = 13,
 317                 .muxval = 1,
 318                 .cctl = 0,
 319                 .periph_buses = PL08X_AHB2,
 320         }, {
 321                 .bus_id = "rs485_rx",
 322                 .min_signal = 14,
 323                 .max_signal = 14,
 324                 .muxval = 1,
 325                 .cctl = 0,
 326                 .periph_buses = PL08X_AHB2,
 327         }, {
 328                 .bus_id = "rs485_tx",
 329                 .min_signal = 15,
 330                 .max_signal = 15,
 331                 .muxval = 1,
 332                 .cctl = 0,
 333                 .periph_buses = PL08X_AHB2,
 334         },
 335 };
 336
 337 static struct pl022_ssp_controller spear320_ssp_data[] = {
 338         {
 339                 .bus_id = 1,
 340                 .enable_dma = 1,
 341                 .dma_filter = pl08x_filter_id,
 342                 .dma_tx_param = "ssp1_tx",
 343                 .dma_rx_param = "ssp1_rx",
 344                 .num_chipselect = 2,
 345         }, {
 346                 .bus_id = 2,
 347                 .enable_dma = 1,
 348                 .dma_filter = pl08x_filter_id,
 349                 .dma_tx_param = "ssp2_tx",
 350                 .dma_rx_param = "ssp2_rx",
 351                 .num_chipselect = 2,
 352         }
 353 };
 354
 355 static struct amba_pl011_data spear320_uart_data[] = {
 356         {
 357                 .dma_filter = pl08x_filter_id,
 358                 .dma_tx_param = "uart1_tx",
 359                 .dma_rx_param = "uart1_rx",
 360         }, {
 361                 .dma_filter = pl08x_filter_id,
 362                 .dma_tx_param = "uart2_tx",
 363                 .dma_rx_param = "uart2_rx",
 364         },
 365 };
 366
 367 /* Add SPEAr310 auxdata to pass platform data */
 368 static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
 369         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
 370                         &pl022_plat_data),
 371         OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
 372                         &pl080_plat_data),
 373         OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
 374                         &spear320_ssp_data[0]),
 375         OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
 376                         &spear320_ssp_data[1]),
 377         OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
 378                         &spear320_uart_data[0]),
 379         OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
 380                         &spear320_uart_data[1]),
 381         {}
 382 };
 383
 384 static void __init spear320_dt_init(void)
 385 {
 386         void __iomem *base;
 387         int ret;
 388
 389         pl080_plat_data.slave_channels = spear320_dma_info;
 390         pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
 391
 392         of_platform_populate(NULL, of_default_bus_match_table,
 393                         spear320_auxdata_lookup, NULL);
 394
 395         /* shared irq registration */
 396         base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
 397         if (base) {
 398                 /* shirq 1 */
 399                 shirq_ras1.regs.base = base;
 400                 ret = spear_shirq_register(&shirq_ras1);
 401                 if (ret)
 402                         pr_err("Error registering Shared IRQ 1\n");
 403
 404                 /* shirq 3 */
 405                 shirq_ras3.regs.base = base;
 406                 ret = spear_shirq_register(&shirq_ras3);
 407                 if (ret)
 408                         pr_err("Error registering Shared IRQ 3\n");
 409
 410                 /* shirq 4 */
 411                 shirq_intrcomm_ras.regs.base = base;
 412                 ret = spear_shirq_register(&shirq_intrcomm_ras);
 413                 if (ret)
 414                         pr_err("Error registering Shared IRQ 4\n");
 415         }
 416 }
 417
 418 static const char * const spear320_dt_board_compat[] = {
 419         "st,spear320",
 420         "st,spear320-evb",
 421         NULL,
 422 };
 423
 424 static void __init spear320_map_io(void)
 425 {
 426         spear3xx_map_io();
 427         spear320_clk_init();
 428 }
 429
 430 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
 431         .map_io         =       spear320_map_io,
 432         .init_irq       =       spear3xx_dt_init_irq,
 433         .handle_irq     =       vic_handle_irq,
 434         .timer          =       &spear3xx_timer,
 435         .init_machine   =       spear320_dt_init,
 436         .restart        =       spear_restart,
 437         .dt_compat      =       spear320_dt_board_compat,
 438 MACHINE_END