2 * Lowlevel clock handling for Telechips TCC8xxx SoCs
4 * Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de>
6 * Licensed under the terms of the GPL v2
10 #include <linux/delay.h>
11 #include <linux/err.h>
13 #include <linux/module.h>
14 #include <linux/spinlock.h>
15 #include <linux/clkdev.h>
17 #include <mach/clock.h>
18 #include <mach/irqs.h>
19 #include <mach/tcc8k-regs.h>
23 #define BCLKCTR0 (CKC_BASE + BCLKCTR0_OFFS)
24 #define BCLKCTR1 (CKC_BASE + BCLKCTR1_OFFS)
26 #define ACLKREF (CKC_BASE + ACLKREF_OFFS)
27 #define ACLKUART0 (CKC_BASE + ACLKUART0_OFFS)
28 #define ACLKUART1 (CKC_BASE + ACLKUART1_OFFS)
29 #define ACLKUART2 (CKC_BASE + ACLKUART2_OFFS)
30 #define ACLKUART3 (CKC_BASE + ACLKUART3_OFFS)
31 #define ACLKUART4 (CKC_BASE + ACLKUART4_OFFS)
32 #define ACLKI2C (CKC_BASE + ACLKI2C_OFFS)
33 #define ACLKADC (CKC_BASE + ACLKADC_OFFS)
34 #define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
35 #define ACLKLCD (CKC_BASE + ACLKLCD_OFFS)
36 #define ACLKSDH0 (CKC_BASE + ACLKSDH0_OFFS)
37 #define ACLKSDH1 (CKC_BASE + ACLKSDH1_OFFS)
38 #define ACLKSPI0 (CKC_BASE + ACLKSPI0_OFFS)
39 #define ACLKSPI1 (CKC_BASE + ACLKSPI1_OFFS)
40 #define ACLKSPDIF (CKC_BASE + ACLKSPDIF_OFFS)
41 #define ACLKC3DEC (CKC_BASE + ACLKC3DEC_OFFS)
42 #define ACLKCAN0 (CKC_BASE + ACLKCAN0_OFFS)
43 #define ACLKCAN1 (CKC_BASE + ACLKCAN1_OFFS)
44 #define ACLKGSB0 (CKC_BASE + ACLKGSB0_OFFS)
45 #define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS)
46 #define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS)
47 #define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS)
48 #define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
49 #define ACLKTCT (CKC_BASE + ACLKTCT_OFFS)
50 #define ACLKTCX (CKC_BASE + ACLKTCX_OFFS)
51 #define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS)
53 #define ACLK_MAX_DIV (0xfff + 1)
55 /* Crystal frequencies */
56 static unsigned long xi_rate, xti_rate;
58 static void __iomem *pll_cfg_addr(int pll)
61 case 0: return (CKC_BASE + PLL0CFG_OFFS);
62 case 1: return (CKC_BASE + PLL1CFG_OFFS);
63 case 2: return (CKC_BASE + PLL2CFG_OFFS);
69 static int pll_enable(int pll, int enable)
72 void __iomem *addr = pll_cfg_addr(pll);
74 reg = __raw_readl(addr);
80 __raw_writel(reg, addr);
84 static int xi_enable(int enable)
88 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
94 __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
98 static int root_clk_enable(enum root_clks src)
101 case CLK_SRC_PLL0: return pll_enable(0, 1);
102 case CLK_SRC_PLL1: return pll_enable(1, 1);
103 case CLK_SRC_PLL2: return pll_enable(2, 1);
104 case CLK_SRC_XI: return xi_enable(1);
111 static int root_clk_disable(enum root_clks root_src)
114 case CLK_SRC_PLL0: return pll_enable(0, 0);
115 case CLK_SRC_PLL1: return pll_enable(1, 0);
116 case CLK_SRC_PLL2: return pll_enable(2, 0);
117 case CLK_SRC_XI: return xi_enable(0);
124 static int enable_clk(struct clk *clk)
128 if (clk->root_id != CLK_SRC_NOROOT)
129 return root_clk_enable(clk->root_id);
132 reg = __raw_readl(clk->aclkreg);
134 __raw_writel(reg, clk->aclkreg);
137 reg = __raw_readl(clk->bclkctr);
138 reg |= 1 << clk->bclk_shift;
139 __raw_writel(reg, clk->bclkctr);
144 static void disable_clk(struct clk *clk)
148 if (clk->root_id != CLK_SRC_NOROOT) {
149 root_clk_disable(clk->root_id);
154 reg = __raw_readl(clk->bclkctr);
155 reg &= ~(1 << clk->bclk_shift);
156 __raw_writel(reg, clk->bclkctr);
159 reg = __raw_readl(clk->aclkreg);
161 __raw_writel(reg, clk->aclkreg);
165 static unsigned long get_rate_pll(int pll)
168 unsigned long s, m, p;
169 void __iomem *addr = pll_cfg_addr(pll);
171 reg = __raw_readl(addr);
172 s = (reg >> 16) & 0x07;
173 m = (reg >> 8) & 0xff;
176 return (m * xi_rate) / (p * (1 << s));
179 static unsigned long get_rate_pll_div(int pll)
182 unsigned long div = 0;
187 addr = CKC_BASE + CLKDIVC0_OFFS;
188 reg = __raw_readl(addr);
189 if (reg & CLKDIVC0_P0E)
190 div = (reg >> 24) & 0x3f;
193 addr = CKC_BASE + CLKDIVC0_OFFS;
194 reg = __raw_readl(addr);
195 if (reg & CLKDIVC0_P1E)
196 div = (reg >> 16) & 0x3f;
199 addr = CKC_BASE + CLKDIVC1_OFFS;
200 reg = __raw_readl(addr);
201 if (reg & CLKDIVC1_P2E)
205 return get_rate_pll(pll) / (div + 1);
208 static unsigned long get_rate_xi_div(void)
210 unsigned long div = 0;
211 u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
213 if (reg & CLKDIVC0_XE)
214 div = (reg >> 8) & 0x3f;
216 return xi_rate / (div + 1);
219 static unsigned long get_rate_xti_div(void)
221 unsigned long div = 0;
222 u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
224 if (reg & CLKDIVC0_XTE)
227 return xti_rate / (div + 1);
230 static unsigned long root_clk_get_rate(enum root_clks src)
233 case CLK_SRC_PLL0: return get_rate_pll(0);
234 case CLK_SRC_PLL1: return get_rate_pll(1);
235 case CLK_SRC_PLL2: return get_rate_pll(2);
236 case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
237 case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
238 case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
239 case CLK_SRC_XI: return xi_rate;
240 case CLK_SRC_XTI: return xti_rate;
241 case CLK_SRC_XIDIV: return get_rate_xi_div();
242 case CLK_SRC_XTIDIV: return get_rate_xti_div();
247 static unsigned long aclk_get_rate(struct clk *clk)
253 reg = __raw_readl(clk->aclkreg);
255 src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
256 return root_clk_get_rate(src) / (div + 1);
259 static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
261 unsigned long div, src, freq, r1, r2;
266 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
268 freq = root_clk_get_rate(src);
272 if (div >= ACLK_MAX_DIV)
275 r2 = freq / (div + 1);
276 if ((rate - r2) < (r1 - rate))
282 static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
286 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
289 return root_clk_get_rate(src) / aclk_best_div(clk, rate);
292 static int aclk_set_rate(struct clk *clk, unsigned long rate)
296 reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
297 reg |= aclk_best_div(clk, rate) - 1;
298 __raw_writel(reg, clk->aclkreg);
302 static unsigned long get_rate_sys(struct clk *clk)
306 src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
307 return root_clk_get_rate(src);
310 static unsigned long get_rate_bus(struct clk *clk)
314 div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
315 return get_rate_sys(clk) / (div + 1);
318 static unsigned long get_rate_cpu(struct clk *clk)
320 unsigned int reg, div, fsys, fbus;
322 fbus = get_rate_bus(clk);
323 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
326 fsys = get_rate_sys(clk);
327 div = (reg >> 16) & 0x0f;
328 return fbus + ((fsys - fbus) * (div + 1)) / 16;
331 static unsigned long get_rate_root(struct clk *clk)
333 return root_clk_get_rate(clk->root_id);
336 static int aclk_set_parent(struct clk *clock, struct clk *parent)
340 if (clock->parent == parent)
343 clock->parent = parent;
348 if (parent->root_id == CLK_SRC_NOROOT)
350 reg = __raw_readl(clock->aclkreg);
351 reg &= ~ACLK_SEL_MASK;
352 reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
353 __raw_writel(reg, clock->aclkreg);
358 #define DEFINE_ROOT_CLOCK(name, ri, p) \
359 static struct clk name = { \
361 .get_rate = get_rate_root, \
362 .enable = enable_clk, \
363 .disable = disable_clk, \
367 #define DEFINE_SPECIAL_CLOCK(name, gr, p) \
368 static struct clk name = { \
369 .root_id = CLK_SRC_NOROOT, \
374 #define DEFINE_ACLOCK(name, bc, bs, ar) \
375 static struct clk name = { \
376 .root_id = CLK_SRC_NOROOT, \
380 .get_rate = aclk_get_rate, \
381 .set_rate = aclk_set_rate, \
382 .round_rate = aclk_round_rate, \
383 .enable = enable_clk, \
384 .disable = disable_clk, \
385 .set_parent = aclk_set_parent, \
388 #define DEFINE_BCLOCK(name, bc, bs, gr, p) \
389 static struct clk name = { \
390 .root_id = CLK_SRC_NOROOT, \
394 .enable = enable_clk, \
395 .disable = disable_clk, \
399 DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
400 DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
401 DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
402 DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
403 DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
404 DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
405 DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
406 DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
407 DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
408 DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
410 /* The following 3 clocks are special and are initialized explicitly later */
411 DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
412 DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
413 DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
415 DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
416 DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
417 DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
418 DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
419 DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
420 DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
421 DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
422 DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
423 DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
424 DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
425 DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
426 DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
427 DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
428 DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
429 DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
430 DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
431 DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
432 DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
433 DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
434 DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
435 DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
436 DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
437 DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
438 DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
439 DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
440 DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
442 DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
443 DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
444 DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
445 DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
446 DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
447 DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
448 DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
449 DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
450 DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
451 DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
452 DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
453 DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
454 DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
455 DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
456 DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
457 DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
458 DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
459 DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
460 DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
461 DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
462 DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
463 DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
465 #define _REGISTER_CLOCK(d, n, c) \
472 static struct clk_lookup lookups[] = {
473 _REGISTER_CLOCK(NULL, "bus", bus)
474 _REGISTER_CLOCK(NULL, "cpu", cpu)
475 _REGISTER_CLOCK(NULL, "tct", tct)
476 _REGISTER_CLOCK(NULL, "tcx", tcx)
477 _REGISTER_CLOCK(NULL, "tcz", tcz)
478 _REGISTER_CLOCK(NULL, "ref", ref)
479 _REGISTER_CLOCK(NULL, "dai0", dai0)
480 _REGISTER_CLOCK(NULL, "pic", pic)
481 _REGISTER_CLOCK(NULL, "tc", tc)
482 _REGISTER_CLOCK(NULL, "gpio", gpio)
483 _REGISTER_CLOCK(NULL, "usbd", usbd)
484 _REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
485 _REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
486 _REGISTER_CLOCK("tcc-i2c", NULL, i2c)
487 _REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
488 _REGISTER_CLOCK(NULL, "ecc", ecc)
489 _REGISTER_CLOCK(NULL, "adc", adc)
490 _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
491 _REGISTER_CLOCK(NULL, "gdma0", gdma0)
492 _REGISTER_CLOCK(NULL, "lcd", lcd)
493 _REGISTER_CLOCK(NULL, "rtc", rtc)
494 _REGISTER_CLOCK(NULL, "nfc", nfc)
495 _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
496 _REGISTER_CLOCK(NULL, "g2d", g2d)
497 _REGISTER_CLOCK(NULL, "gdma1", gdma1)
498 _REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
499 _REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
500 _REGISTER_CLOCK(NULL, "mscl", mscl)
501 _REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
502 _REGISTER_CLOCK(NULL, "bdma", bdma)
503 _REGISTER_CLOCK(NULL, "adma0", adma0)
504 _REGISTER_CLOCK(NULL, "spdif", spdif)
505 _REGISTER_CLOCK(NULL, "scfg", scfg)
506 _REGISTER_CLOCK(NULL, "cid", cid)
507 _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
508 _REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
509 _REGISTER_CLOCK(NULL, "dai1", dai1)
510 _REGISTER_CLOCK(NULL, "adma1", adma1)
511 _REGISTER_CLOCK(NULL, "c3dec", c3dec)
512 _REGISTER_CLOCK("tcc-can.0", NULL, can0)
513 _REGISTER_CLOCK("tcc-can.1", NULL, can1)
514 _REGISTER_CLOCK(NULL, "gps", gps)
515 _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
516 _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
517 _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
518 _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
519 _REGISTER_CLOCK(NULL, "gdma2", gdma2)
520 _REGISTER_CLOCK(NULL, "gdma3", gdma3)
521 _REGISTER_CLOCK(NULL, "ddrc", ddrc)
522 _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
525 static struct clk *root_clk_by_index(enum root_clks src)
528 case CLK_SRC_PLL0: return &pll0;
529 case CLK_SRC_PLL1: return &pll1;
530 case CLK_SRC_PLL2: return &pll2;
531 case CLK_SRC_PLL0DIV: return &pll0div;
532 case CLK_SRC_PLL1DIV: return &pll1div;
533 case CLK_SRC_PLL2DIV: return &pll2div;
534 case CLK_SRC_XI: return ξ
535 case CLK_SRC_XTI: return &xti;
536 case CLK_SRC_XIDIV: return &xidiv;
537 case CLK_SRC_XTIDIV: return &xtidiv;
538 default: return NULL;
542 static void find_aclk_parent(struct clk *clk)
550 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
553 clock = root_clk_by_index(src);
558 clk->set_parent = aclk_set_parent;
561 void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
568 /* fixup parents and add the clock */
569 for (i = 0; i < ARRAY_SIZE(lookups); i++) {
570 find_aclk_parent(lookups[i].clk);
571 clkdev_add(&lookups[i]);
573 tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32);