2 * arch/arm/mach-tegra/board-dt-tegra30.c
4 * NVIDIA Tegra30 device tree board support
6 * Copyright (C) 2011 NVIDIA Corporation
10 * arch/arm/mach-tegra/board-dt-tegra20.c
12 * Copyright (C) 2010 Secret Lab Technologies, Ltd.
13 * Copyright (C) 2010 Google, Inc.
15 * This software is licensed under the terms of the GNU General Public
16 * License version 2, as published by the Free Software Foundation, and
17 * may be copied, distributed, and modified under those terms.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
26 #include <linux/kernel.h>
28 #include <linux/of_address.h>
29 #include <linux/of_fdt.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
33 #include <asm/mach/arch.h>
34 #include <asm/hardware/gic.h>
39 static struct of_device_id tegra_dt_match_table[] __initdata = {
40 { .compatible = "simple-bus", },
44 struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
45 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
46 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
47 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
48 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
49 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
50 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
51 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
52 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
53 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
54 OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
58 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
59 /* name parent rate enabled */
60 { "uarta", "pll_p", 408000000, true },
61 { "pll_a", "pll_p_out1", 564480000, true },
62 { "pll_a_out0", "pll_a", 11289600, true },
63 { "extern1", "pll_a_out0", 0, true },
64 { "clk_out_1", "extern1", 0, true },
65 { "i2s0", "pll_a_out0", 11289600, false},
66 { "i2s1", "pll_a_out0", 11289600, false},
67 { "i2s2", "pll_a_out0", 11289600, false},
68 { "i2s3", "pll_a_out0", 11289600, false},
69 { "i2s4", "pll_a_out0", 11289600, false},
73 static void __init tegra30_dt_init(void)
75 tegra_clk_init_from_table(tegra_dt_clk_init_table);
77 of_platform_populate(NULL, tegra_dt_match_table,
78 tegra30_auxdata_lookup, NULL);
81 static const char *tegra30_dt_board_compat[] = {
86 DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
87 .map_io = tegra_map_common_io,
88 .init_early = tegra30_init_early,
89 .init_irq = tegra_dt_init_irq,
90 .handle_irq = gic_handle_irq,
91 .timer = &tegra_timer,
92 .init_machine = tegra30_dt_init,
93 .restart = tegra_assert_system_reset,
94 .dt_compat = tegra30_dt_board_compat,