2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra SoC common clock control functions */
22 #include <asm/arch/clock.h>
23 #include <asm/arch/tegra.h>
24 #include <asm/arch-tegra/ap.h>
25 #include <asm/arch-tegra/clk_rst.h>
26 #include <asm/arch-tegra/pmc.h>
27 #include <asm/arch-tegra/timer.h>
32 * This is our record of the current clock rate of each clock. We don't
33 * fill all of these in since we are only really interested in clocks which
36 static unsigned pll_rate[CLOCK_ID_COUNT];
39 * The oscillator frequency is fixed to one of four set values. Based on this
40 * the other clocks are set up appropriately.
42 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
51 /* return 1 if a peripheral ID is in range */
52 #define clock_type_id_isvalid(id) ((id) >= 0 && \
53 (id) < CLOCK_TYPE_COUNT)
55 char pllp_valid = 1; /* PLLP is set up correctly */
57 /* return 1 if a periphc_internal_id is in range */
58 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
61 /* number of clock outputs of a PLL */
62 static const u8 pll_num_clkouts[] = {
71 int clock_get_osc_bypass(void)
73 struct clk_rst_ctlr *clkrst =
74 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
77 reg = readl(&clkrst->crc_osc_ctrl);
78 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
81 /* Returns a pointer to the registers of the given pll */
82 static struct clk_pll *get_pll(enum clock_id clkid)
84 struct clk_rst_ctlr *clkrst =
85 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
87 assert(clock_id_is_pll(clkid));
88 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
89 debug("%s: Invalid PLL %d\n", __func__, clkid);
92 return &clkrst->crc_pll[clkid];
95 __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
100 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
101 u32 *divp, u32 *cpcon, u32 *lfcon)
103 struct clk_pll *pll = get_pll(clkid);
104 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
107 assert(clkid != CLOCK_ID_USB);
109 /* Safety check, adds to code size but is small */
110 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
112 data = readl(&pll->pll_base);
113 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
114 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
115 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
116 data = readl(&pll->pll_misc);
117 /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
118 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
119 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
124 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
125 u32 divp, u32 cpcon, u32 lfcon)
127 struct clk_pll *pll = NULL;
128 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
131 if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
132 pll = get_pll(clkid);
135 * pllinfo has the m/n/p and kcp/kvco mask and shift
136 * values for all of the PLLs used in U-Boot, with any
137 * SoC differences accounted for.
139 misc_data = readl(&pll->pll_misc); /* preserve EN_LOCKDET, etc. */
140 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift) | (cpcon << pllinfo->kcp_shift);
141 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift) | (lfcon << pllinfo->kvco_shift);
143 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
144 data |= divp << pllinfo->p_shift;
145 data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
148 writel(misc_data, &pll->pll_misc);
149 writel(data, &pll->pll_base);
151 struct clk_pll_simple *pll = clock_get_simple_pll(clkid);
154 debug("%s: Uknown simple PLL %d\n", __func__, clkid);
157 writel(misc_data, &pll->pll_misc);
158 writel(data, &pll->pll_base);
161 /* calculate the stable time */
162 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
165 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
168 u32 *reg = get_periph_source_reg(periph_id);
173 value &= ~OUT_CLK_SOURCE_31_30_MASK;
174 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
176 value &= ~OUT_CLK_DIVISOR_MASK;
177 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
182 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
185 u32 *reg = get_periph_source_reg(periph_id);
188 case MASK_BITS_31_30:
189 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
190 source << OUT_CLK_SOURCE_31_30_SHIFT);
193 case MASK_BITS_31_29:
194 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
195 source << OUT_CLK_SOURCE_31_29_SHIFT);
198 case MASK_BITS_31_28:
199 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
200 source << OUT_CLK_SOURCE_31_28_SHIFT);
210 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
212 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
216 * Given the parent's rate and the required rate for the children, this works
217 * out the peripheral clock divider to use, in 7.1 binary format.
219 * @param divider_bits number of divider bits (8 or 16)
220 * @param parent_rate clock rate of parent clock in Hz
221 * @param rate required clock rate for this clock
222 * @return divider which should be used
224 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
227 u64 divider = parent_rate * 2;
228 unsigned max_divider = 1 << divider_bits;
231 do_div(divider, rate);
233 if ((s64)divider - 2 < 0)
236 if ((s64)divider - 2 >= max_divider)
242 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
244 struct clk_pll *pll = get_pll(clkid);
245 int data = 0, div = 0, offset = 0;
247 if (!clock_id_is_pll(clkid))
250 if (pllout + 1 > pll_num_clkouts[clkid])
253 div = clk_get_divider(8, pll_rate[clkid], rate);
258 /* out2 and out4 are in the high part of the register */
259 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
262 data = (div << PLL_OUT_RATIO_SHIFT) |
263 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
264 clrsetbits_le32(&pll->pll_out[pllout >> 1],
265 PLL_OUT_RATIO_MASK << offset, data << offset);
271 * Given the parent's rate and the divider in 7.1 format, this works out the
272 * resulting peripheral clock rate.
274 * @param parent_rate clock rate of parent clock in Hz
275 * @param divider which should be used in 7.1 format
276 * @return effective clock rate of peripheral
278 static unsigned long get_rate_from_divider(unsigned long parent_rate,
283 rate = (u64)parent_rate * 2;
284 do_div(rate, divider + 2);
288 unsigned long clock_get_periph_rate(enum periph_id periph_id,
289 enum clock_id parent)
291 u32 *reg = get_periph_source_reg(periph_id);
293 return get_rate_from_divider(pll_rate[parent],
294 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
298 * Find the best available 7.1 format divisor given a parent clock rate and
299 * required child clock rate. This function assumes that a second-stage
300 * divisor is available which can divide by powers of 2 from 1 to 256.
302 * @param divider_bits number of divider bits (8 or 16)
303 * @param parent_rate clock rate of parent clock in Hz
304 * @param rate required clock rate for this clock
305 * @param extra_div value for the second-stage divisor (not set if this
306 * function returns -1.
307 * @return divider which should be used, or -1 if nothing is valid
310 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
311 unsigned long rate, int *extra_div)
314 int best_divider = -1;
315 int best_error = rate;
317 /* try dividers from 1 to 256 and find closest match */
318 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
319 unsigned divided_parent = parent_rate >> shift;
320 int divider = clk_get_divider(divider_bits, divided_parent,
322 unsigned effective_rate = get_rate_from_divider(divided_parent,
324 int error = rate - effective_rate;
326 /* Given a valid divider, look for the lowest error */
327 if (divider != -1 && error < best_error) {
329 *extra_div = 1 << shift;
330 best_divider = divider;
334 /* return what we found - *extra_div will already be set */
339 * Adjust peripheral PLL to use the given divider and source.
341 * @param periph_id peripheral to adjust
342 * @param source Source number (0-3 or 0-7)
343 * @param mux_bits Number of mux bits (2 or 4)
344 * @param divider Required divider in 7.1 or 15.1 format
345 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
346 * for this peripheral)
348 static int adjust_periph_pll(enum periph_id periph_id, int source,
349 int mux_bits, unsigned divider)
351 u32 *reg = get_periph_source_reg(periph_id);
353 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
354 divider << OUT_CLK_DIVISOR_SHIFT);
357 /* work out the source clock and set it */
361 clock_ll_set_source_bits(periph_id, mux_bits, source);
367 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
368 enum clock_id parent, unsigned rate, int *extra_div)
370 unsigned effective_rate;
371 int mux_bits, divider_bits, source;
375 /* work out the source clock and set it */
376 source = get_periph_clock_source(periph_id, parent, &mux_bits,
379 divider = find_best_divider(divider_bits, pll_rate[parent],
384 assert(divider >= 0);
385 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
387 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
388 get_periph_source_reg(periph_id),
389 readl(get_periph_source_reg(periph_id)));
391 /* Check what we ended up with. This shouldn't matter though */
392 effective_rate = clock_get_periph_rate(periph_id, parent);
394 effective_rate /= *extra_div;
395 if (rate != effective_rate)
396 debug("Requested clock rate %u not honored (got %u)\n",
397 rate, effective_rate);
398 return effective_rate;
401 unsigned clock_start_periph_pll(enum periph_id periph_id,
402 enum clock_id parent, unsigned rate)
404 unsigned effective_rate;
406 reset_set_enable(periph_id, 1);
407 clock_enable(periph_id);
409 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
412 reset_set_enable(periph_id, 0);
413 return effective_rate;
416 void clock_enable(enum periph_id clkid)
418 clock_set_enable(clkid, 1);
421 void clock_disable(enum periph_id clkid)
423 clock_set_enable(clkid, 0);
426 void reset_periph(enum periph_id periph_id, int us_delay)
428 /* Put peripheral into reset */
429 reset_set_enable(periph_id, 1);
433 reset_set_enable(periph_id, 0);
438 void reset_cmplx_set_enable(int cpu, int which, int reset)
440 struct clk_rst_ctlr *clkrst =
441 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
444 /* Form the mask, which depends on the cpu chosen (2 or 4) */
445 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
448 /* either enable or disable those reset for that CPU */
450 writel(mask, &clkrst->crc_cpu_cmplx_set);
452 writel(mask, &clkrst->crc_cpu_cmplx_clr);
455 unsigned clock_get_rate(enum clock_id clkid)
459 u64 parent_rate, rate;
460 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
462 parent_rate = osc_freq[clock_get_osc_freq()];
463 if (clkid == CLOCK_ID_OSC)
466 pll = get_pll(clkid);
469 base = readl(&pll->pll_base);
471 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
472 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
474 * PLLU uses p_mask/p_shift for VCO on all but T210,
475 * T210 uses normal DIVP. Handled in pllinfo table.
477 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
483 * Set the output frequency you want for each PLL clock.
484 * PLL output frequencies are programmed by setting their N, M and P values.
485 * The governing equations are:
486 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
487 * where Fo is the output frequency from the PLL.
488 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
489 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
490 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
492 * @param n PLL feedback divider(DIVN)
493 * @param m PLL input divider(DIVN)
494 * @param p post divider(DIVP)
495 * @param cpcon base PLL charge pump(CPCON)
496 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
497 * be overriden), 1 if PLL is already correct
499 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
501 u32 base_reg, misc_reg;
503 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
505 pll = get_pll(clkid);
507 base_reg = readl(&pll->pll_base);
509 /* Set BYPASS, m, n and p to PLL_BASE */
510 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
511 base_reg |= m << pllinfo->m_shift;
513 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
514 base_reg |= n << pllinfo->n_shift;
516 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
517 base_reg |= p << pllinfo->p_shift;
519 if (clkid == CLOCK_ID_PERIPH) {
521 * If the PLL is already set up, check that it is correct
522 * and record this info for clock_verify() to check.
524 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
525 base_reg |= PLL_ENABLE_MASK;
526 if (base_reg != readl(&pll->pll_base))
528 return pllp_valid ? 1 : -1;
530 base_reg |= PLL_BASE_OVRRIDE_MASK;
533 base_reg |= PLL_BYPASS_MASK;
534 writel(base_reg, &pll->pll_base);
536 /* Set cpcon (KCP) to PLL_MISC */
537 misc_reg = readl(&pll->pll_misc);
538 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
539 misc_reg |= cpcon << pllinfo->kcp_shift;
540 writel(misc_reg, &pll->pll_misc);
543 base_reg |= PLL_ENABLE_MASK;
544 writel(base_reg, &pll->pll_base);
547 base_reg &= ~PLL_BYPASS_MASK;
548 writel(base_reg, &pll->pll_base);
553 void clock_ll_start_uart(enum periph_id periph_id)
555 /* Assert UART reset and enable clock */
556 reset_set_enable(periph_id, 1);
557 clock_enable(periph_id);
558 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
563 /* De-assert reset to UART */
564 reset_set_enable(periph_id, 0);
567 #ifdef CONFIG_OF_CONTROL
568 int clock_decode_periph_id(const void *blob, int node)
574 err = fdtdec_get_int_array(blob, node, "clocks", cell,
578 id = clk_id_to_periph_id(cell[1]);
579 assert(clock_periph_id_isvalid(id));
582 #endif /* CONFIG_OF_CONTROL */
584 int clock_verify(void)
586 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
587 u32 reg = readl(&pll->pll_base);
590 printf("Warning: PLLP %x is not correct\n", reg);
593 debug("PLLP %x is correct\n", reg);
597 void clock_init(void)
599 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
600 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
601 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
602 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
603 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
604 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
605 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
606 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
608 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
609 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
610 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
611 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
612 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
613 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
614 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
617 static void set_avp_clock_source(u32 src)
619 struct clk_rst_ctlr *clkrst =
620 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
623 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
624 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
625 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
626 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
627 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
628 writel(val, &clkrst->crc_sclk_brst_pol);
633 * This function is useful on Tegra30, and any later SoCs that have compatible
634 * PLLP configuration registers.
635 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
637 void tegra30_set_up_pllp(void)
639 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
643 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
644 * run up to 275MHz. On power on, the default sytem clock source is set
645 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
646 * 408MHz which is beyond system clock's upper limit.
648 * The fix is to set the system clock to CLK_M before initializing PLLP,
649 * and then switch back to PLLP_OUT4, which has an appropriate divider
650 * configured, after PLLP has been configured
652 set_avp_clock_source(SCLK_SOURCE_CLKM);
655 * PLLP output frequency set to 408Mhz
656 * PLLC output frequency set to 228Mhz
658 switch (clock_get_osc_freq()) {
659 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
660 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
661 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
664 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
665 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
666 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
669 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
670 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
671 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
673 case CLOCK_OSC_FREQ_19_2:
676 * These are not supported. It is too early to print a
677 * message and the UART likely won't work anyway due to the
678 * oscillator being wrong.
683 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
686 /* Assert RSTN before enable */
687 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
688 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
689 /* Set divisor and reenable */
690 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
691 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
692 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
693 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
694 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
697 /* Assert RSTN before enable */
698 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
699 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
700 /* Set divisor and reenable */
701 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
702 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
703 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
704 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
705 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
707 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
710 int clock_external_output(int clk_id)
712 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
714 if (clk_id >= 1 && clk_id <= 3) {
715 setbits_le32(&pmc->pmc_clk_out_cntrl,
716 1 << (2 + (clk_id - 1) * 8));
718 printf("%s: Unknown output clock id %d\n", __func__, clk_id);