arch/arm/mach-tegra/cpuidle-tegra30.c

   1 /*
   2  * CPU idle driver for Tegra CPUs
   3  *
   4  * Copyright (c) 2010-2012, NVIDIA Corporation.
   5  * Copyright (c) 2011 Google, Inc.
   6  * Author: Colin Cross <ccross@android.com>
   7  *         Gary King <gking@nvidia.com>
   8  *
   9  * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/cpuidle.h>
  25 #include <linux/cpu_pm.h>
  26 #include <linux/clockchips.h>
  27 #include <linux/clk/tegra.h>
  28
  29 #include <asm/cpuidle.h>
  30 #include <asm/proc-fns.h>
  31 #include <asm/suspend.h>
  32 #include <asm/smp_plat.h>
  33
  34 #include "pm.h"
  35 #include "sleep.h"
  36
  37 #ifdef CONFIG_PM_SLEEP
  38 static int tegra30_idle_lp2(struct cpuidle_device *dev,
  39                             struct cpuidle_driver *drv,
  40                             int index);
  41 #endif
  42
  43 static struct cpuidle_driver tegra_idle_driver = {
  44         .name = "tegra_idle",
  45         .owner = THIS_MODULE,
  46         .en_core_tk_irqen = 1,
  47 #ifdef CONFIG_PM_SLEEP
  48         .state_count = 2,
  49 #else
  50         .state_count = 1,
  51 #endif
  52         .states = {
  53                 [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
  54 #ifdef CONFIG_PM_SLEEP
  55                 [1] = {
  56                         .enter                  = tegra30_idle_lp2,
  57                         .exit_latency           = 2000,
  58                         .target_residency       = 2200,
  59                         .power_usage            = 0,
  60                         .flags                  = CPUIDLE_FLAG_TIME_VALID,
  61                         .name                   = "powered-down",
  62                         .desc                   = "CPU power gated",
  63                 },
  64 #endif
  65         },
  66 };
  67
  68 static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
  69
  70 #ifdef CONFIG_PM_SLEEP
  71 static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
  72                                            struct cpuidle_driver *drv,
  73                                            int index)
  74 {
  75         /* All CPUs entering LP2 is not working.
  76          * Don't let CPU0 enter LP2 when any secondary CPU is online.
  77          */
  78         if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
  79                 cpu_do_idle();
  80                 return false;
  81         }
  82
  83         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
  84
  85         tegra_idle_lp2_last();
  86
  87         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
  88
  89         return true;
  90 }
  91
  92 #ifdef CONFIG_SMP
  93 static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
  94                                         struct cpuidle_driver *drv,
  95                                         int index)
  96 {
  97         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
  98
  99         smp_wmb();
 100
 101         cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
 102
 103         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 104
 105         return true;
 106 }
 107 #else
 108 static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 109                                                struct cpuidle_driver *drv,
 110                                                int index)
 111 {
 112         return true;
 113 }
 114 #endif
 115
 116 static int tegra30_idle_lp2(struct cpuidle_device *dev,
 117                             struct cpuidle_driver *drv,
 118                             int index)
 119 {
 120         u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
 121         bool entered_lp2 = false;
 122         bool last_cpu;
 123
 124         local_fiq_disable();
 125
 126         last_cpu = tegra_set_cpu_in_lp2(cpu);
 127         cpu_pm_enter();
 128
 129         if (cpu == 0) {
 130                 if (last_cpu)
 131                         entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
 132                                                                      index);
 133                 else
 134                         cpu_do_idle();
 135         } else {
 136                 entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
 137         }
 138
 139         cpu_pm_exit();
 140         tegra_clear_cpu_in_lp2(cpu);
 141
 142         local_fiq_enable();
 143
 144         smp_rmb();
 145
 146         return (entered_lp2) ? index : 0;
 147 }
 148 #endif
 149
 150 int __init tegra30_cpuidle_init(void)
 151 {
 152         int ret;
 153         unsigned int cpu;
 154         struct cpuidle_device *dev;
 155         struct cpuidle_driver *drv = &tegra_idle_driver;
 156
 157 #ifdef CONFIG_PM_SLEEP
 158         tegra_tear_down_cpu = tegra30_tear_down_cpu;
 159 #endif
 160
 161         ret = cpuidle_register_driver(&tegra_idle_driver);
 162         if (ret) {
 163                 pr_err("CPUidle driver registration failed\n");
 164                 return ret;
 165         }
 166
 167         for_each_possible_cpu(cpu) {
 168                 dev = &per_cpu(tegra_idle_device, cpu);
 169                 dev->cpu = cpu;
 170
 171                 dev->state_count = drv->state_count;
 172                 ret = cpuidle_register_device(dev);
 173                 if (ret) {
 174                         pr_err("CPU%u: CPUidle device registration failed\n",
 175                                 cpu);
 176                         return ret;
 177                 }
 178         }
 179         return 0;
 180 }