arch/arm/mach-tegra/flowctrl.c

   1 /*
   2  * arch/arm/mach-tegra/flowctrl.c
   3  *
   4  * functions and macros to control the flowcontroller
   5  *
   6  * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/cpumask.h>
  25
  26 #include "flowctrl.h"
  27 #include "iomap.h"
  28
  29 u8 flowctrl_offset_halt_cpu[] = {
  30         FLOW_CTRL_HALT_CPU0_EVENTS,
  31         FLOW_CTRL_HALT_CPU1_EVENTS,
  32         FLOW_CTRL_HALT_CPU1_EVENTS + 8,
  33         FLOW_CTRL_HALT_CPU1_EVENTS + 16,
  34 };
  35
  36 u8 flowctrl_offset_cpu_csr[] = {
  37         FLOW_CTRL_CPU0_CSR,
  38         FLOW_CTRL_CPU1_CSR,
  39         FLOW_CTRL_CPU1_CSR + 8,
  40         FLOW_CTRL_CPU1_CSR + 16,
  41 };
  42
  43 static void flowctrl_update(u8 offset, u32 value)
  44 {
  45         void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
  46
  47         writel(value, addr);
  48
  49         /* ensure the update has reached the flow controller */
  50         wmb();
  51         readl_relaxed(addr);
  52 }
  53
  54 u32 flowctrl_read_cpu_csr(unsigned int cpuid)
  55 {
  56         u8 offset = flowctrl_offset_cpu_csr[cpuid];
  57         void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
  58
  59         return readl(addr);
  60 }
  61
  62 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
  63 {
  64         return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
  65 }
  66
  67 void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
  68 {
  69         return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
  70 }
  71
  72 void flowctrl_cpu_suspend_enter(unsigned int cpuid)
  73 {
  74         unsigned int reg;
  75         int i;
  76
  77         reg = flowctrl_read_cpu_csr(cpuid);
  78         reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
  79         reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
  80         reg |= FLOW_CTRL_CSR_INTR_FLAG;                 /* clear intr flag */
  81         reg |= FLOW_CTRL_CSR_EVENT_FLAG;                /* clear event flag */
  82         reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; /* pwr gating on wfi */
  83         reg |= FLOW_CTRL_CSR_ENABLE;                    /* pwr gating */
  84         flowctrl_write_cpu_csr(cpuid, reg);
  85
  86         for (i = 0; i < num_possible_cpus(); i++) {
  87                 if (i == cpuid)
  88                         continue;
  89                 reg = flowctrl_read_cpu_csr(i);
  90                 reg |= FLOW_CTRL_CSR_EVENT_FLAG;
  91                 reg |= FLOW_CTRL_CSR_INTR_FLAG;
  92                 flowctrl_write_cpu_csr(i, reg);
  93         }
  94 }
  95
  96 void flowctrl_cpu_suspend_exit(unsigned int cpuid)
  97 {
  98         unsigned int reg;
  99
 100         /* Disable powergating via flow controller for CPU0 */
 101         reg = flowctrl_read_cpu_csr(cpuid);
 102         reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
 103         reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
 104         reg &= ~FLOW_CTRL_CSR_ENABLE;                   /* clear enable */
 105         reg |= FLOW_CTRL_CSR_INTR_FLAG;                 /* clear intr */
 106         reg |= FLOW_CTRL_CSR_EVENT_FLAG;                /* clear event */
 107         flowctrl_write_cpu_csr(cpuid, reg);
 108 }