2 * arch/arm/mach-tegra/pci.c
4 * PCIe host controller driver for TEGRA(2) SOCs
6 * Copyright (c) 2010, CompuLab, Ltd.
7 * Author: Mike Rapoport <mike@compulab.co.il>
9 * Based on NVIDIA PCIe driver
10 * Copyright (c) 2008-2009, NVIDIA Corporation.
12 * Bits taken from arch/arm/mach-dove/pcie.c
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
29 #include <linux/kernel.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/export.h>
37 #include <asm/sizes.h>
38 #include <asm/mach/pci.h>
40 #include <mach/iomap.h>
42 #include <mach/powergate.h>
46 /* Hack - need to parse this from DT */
47 #define INT_PCIE_INTR 130
49 /* register definitions */
50 #define AFI_OFFSET 0x3800
51 #define PADS_OFFSET 0x3000
52 #define RP0_OFFSET 0x0000
53 #define RP1_OFFSET 0x1000
55 #define AFI_AXI_BAR0_SZ 0x00
56 #define AFI_AXI_BAR1_SZ 0x04
57 #define AFI_AXI_BAR2_SZ 0x08
58 #define AFI_AXI_BAR3_SZ 0x0c
59 #define AFI_AXI_BAR4_SZ 0x10
60 #define AFI_AXI_BAR5_SZ 0x14
62 #define AFI_AXI_BAR0_START 0x18
63 #define AFI_AXI_BAR1_START 0x1c
64 #define AFI_AXI_BAR2_START 0x20
65 #define AFI_AXI_BAR3_START 0x24
66 #define AFI_AXI_BAR4_START 0x28
67 #define AFI_AXI_BAR5_START 0x2c
69 #define AFI_FPCI_BAR0 0x30
70 #define AFI_FPCI_BAR1 0x34
71 #define AFI_FPCI_BAR2 0x38
72 #define AFI_FPCI_BAR3 0x3c
73 #define AFI_FPCI_BAR4 0x40
74 #define AFI_FPCI_BAR5 0x44
76 #define AFI_CACHE_BAR0_SZ 0x48
77 #define AFI_CACHE_BAR0_ST 0x4c
78 #define AFI_CACHE_BAR1_SZ 0x50
79 #define AFI_CACHE_BAR1_ST 0x54
81 #define AFI_MSI_BAR_SZ 0x60
82 #define AFI_MSI_FPCI_BAR_ST 0x64
83 #define AFI_MSI_AXI_BAR_ST 0x68
85 #define AFI_CONFIGURATION 0xac
86 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
88 #define AFI_FPCI_ERROR_MASKS 0xb0
90 #define AFI_INTR_MASK 0xb4
91 #define AFI_INTR_MASK_INT_MASK (1 << 0)
92 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
94 #define AFI_INTR_CODE 0xb8
95 #define AFI_INTR_CODE_MASK 0xf
96 #define AFI_INTR_MASTER_ABORT 4
97 #define AFI_INTR_LEGACY 6
99 #define AFI_INTR_SIGNATURE 0xbc
100 #define AFI_SM_INTR_ENABLE 0xc4
102 #define AFI_AFI_INTR_ENABLE 0xc8
103 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
104 #define AFI_INTR_EN_INI_DECERR (1 << 1)
105 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
106 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
107 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
108 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
109 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
110 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
112 #define AFI_PCIE_CONFIG 0x0f8
113 #define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1)
114 #define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2)
115 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
116 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
117 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
119 #define AFI_FUSE 0x104
120 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
122 #define AFI_PEX0_CTRL 0x110
123 #define AFI_PEX1_CTRL 0x118
124 #define AFI_PEX_CTRL_RST (1 << 0)
125 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
127 #define RP_VEND_XP 0x00000F00
128 #define RP_VEND_XP_DL_UP (1 << 30)
130 #define RP_LINK_CONTROL_STATUS 0x00000090
131 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
133 #define PADS_CTL_SEL 0x0000009C
135 #define PADS_CTL 0x000000A0
136 #define PADS_CTL_IDDQ_1L (1 << 0)
137 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
138 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
140 #define PADS_PLL_CTL 0x000000B8
141 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
142 #define PADS_PLL_CTL_LOCKDET (1 << 8)
143 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
144 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
145 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
146 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
147 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
148 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
149 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
151 /* PMC access is required for PCIE xclk (un)clamping */
152 #define PMC_SCRATCH42 0x144
153 #define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
155 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
157 #define pmc_writel(value, reg) \
158 __raw_writel(value, reg_pmc_base + (reg))
159 #define pmc_readl(reg) \
160 __raw_readl(reg_pmc_base + (reg))
163 * Tegra2 defines 1GB in the AXI address map for PCIe.
165 * That address space is split into different regions, with sizes and
166 * offsets as follows:
168 * 0x80000000 - 0x80003fff - PCI controller registers
169 * 0x80004000 - 0x80103fff - PCI configuration space
170 * 0x80104000 - 0x80203fff - PCI extended configuration space
171 * 0x80203fff - 0x803fffff - unused
172 * 0x80400000 - 0x8040ffff - downstream IO
173 * 0x80410000 - 0x8fffffff - unused
174 * 0x90000000 - 0x9fffffff - non-prefetchable memory
175 * 0xa0000000 - 0xbfffffff - prefetchable memory
177 #define PCIE_REGS_SZ SZ_16K
178 #define PCIE_CFG_OFF PCIE_REGS_SZ
179 #define PCIE_CFG_SZ SZ_1M
180 #define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF)
181 #define PCIE_EXT_CFG_SZ SZ_1M
182 #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
184 #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
185 #define MEM_SIZE_0 SZ_128M
186 #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
187 #define MEM_SIZE_1 SZ_128M
188 #define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1)
189 #define PREFETCH_MEM_SIZE_0 SZ_128M
190 #define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
191 #define PREFETCH_MEM_SIZE_1 SZ_128M
193 #define PCIE_CONF_BUS(b) ((b) << 16)
194 #define PCIE_CONF_DEV(d) ((d) << 11)
195 #define PCIE_CONF_FUNC(f) ((f) << 8)
196 #define PCIE_CONF_REG(r) \
197 (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
199 struct tegra_pcie_port {
206 char mem_space_name[16];
207 char prefetch_space_name[20];
208 struct resource res[2];
211 struct tegra_pcie_info {
212 struct tegra_pcie_port port[2];
216 struct resource res_mmio;
220 struct clk *pcie_xclk;
224 static struct tegra_pcie_info tegra_pcie;
226 static inline void afi_writel(u32 value, unsigned long offset)
228 writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
231 static inline u32 afi_readl(unsigned long offset)
233 return readl(offset + AFI_OFFSET + tegra_pcie.regs);
236 static inline void pads_writel(u32 value, unsigned long offset)
238 writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
241 static inline u32 pads_readl(unsigned long offset)
243 return readl(offset + PADS_OFFSET + tegra_pcie.regs);
246 static struct tegra_pcie_port *bus_to_port(int bus)
250 for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
251 int rbus = tegra_pcie.port[i].root_bus_nr;
252 if (rbus != -1 && rbus == bus)
256 return i >= 0 ? tegra_pcie.port + i : NULL;
259 static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
260 int where, int size, u32 *val)
262 struct tegra_pcie_port *pp = bus_to_port(bus->number);
268 return PCIBIOS_DEVICE_NOT_FOUND;
271 addr = pp->base + (where & ~0x3);
273 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
274 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
275 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
276 PCIE_CONF_REG(where));
282 *val = (*val >> (8 * (where & 3))) & 0xff;
284 *val = (*val >> (8 * (where & 3))) & 0xffff;
286 return PCIBIOS_SUCCESSFUL;
289 static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
290 int where, int size, u32 val)
292 struct tegra_pcie_port *pp = bus_to_port(bus->number);
300 return PCIBIOS_DEVICE_NOT_FOUND;
302 addr = pp->base + (where & ~0x3);
304 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
305 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
306 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
307 PCIE_CONF_REG(where));
312 return PCIBIOS_SUCCESSFUL;
316 mask = ~(0xffff << ((where & 0x3) * 8));
318 mask = ~(0xff << ((where & 0x3) * 8));
320 return PCIBIOS_BAD_REGISTER_NUMBER;
322 tmp = readl(addr) & mask;
323 tmp |= val << ((where & 0x3) * 8);
326 return PCIBIOS_SUCCESSFUL;
329 static struct pci_ops tegra_pcie_ops = {
330 .read = tegra_pcie_read_conf,
331 .write = tegra_pcie_write_conf,
334 static void __devinit tegra_pcie_fixup_bridge(struct pci_dev *dev)
338 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
339 pci_read_config_word(dev, PCI_COMMAND, ®);
340 reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
341 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
342 pci_write_config_word(dev, PCI_COMMAND, reg);
345 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
347 /* Tegra PCIE root complex wrongly reports device class */
348 static void __devinit tegra_pcie_fixup_class(struct pci_dev *dev)
350 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
352 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
353 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
355 /* Tegra PCIE requires relaxed ordering */
356 static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
358 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
360 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
362 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
364 struct tegra_pcie_port *pp;
366 if (nr >= tegra_pcie.num_ports)
369 pp = tegra_pcie.port + nr;
370 pp->root_bus_nr = sys->busnr;
372 pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
377 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
378 "PCIe %d MEM", pp->index);
379 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
380 pp->res[0].name = pp->mem_space_name;
381 if (pp->index == 0) {
382 pp->res[0].start = MEM_BASE_0;
383 pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
385 pp->res[0].start = MEM_BASE_1;
386 pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
388 pp->res[0].flags = IORESOURCE_MEM;
389 if (request_resource(&iomem_resource, &pp->res[0]))
390 panic("Request PCIe Memory resource failed\n");
391 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
394 * IORESOURCE_MEM | IORESOURCE_PREFETCH
396 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
397 "PCIe %d PREFETCH MEM", pp->index);
398 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
399 pp->res[1].name = pp->prefetch_space_name;
400 if (pp->index == 0) {
401 pp->res[1].start = PREFETCH_MEM_BASE_0;
402 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
404 pp->res[1].start = PREFETCH_MEM_BASE_1;
405 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
407 pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
408 if (request_resource(&iomem_resource, &pp->res[1]))
409 panic("Request PCIe Prefetch Memory resource failed\n");
410 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
415 static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
417 return INT_PCIE_INTR;
420 static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
421 struct pci_sys_data *sys)
423 struct tegra_pcie_port *pp;
425 if (nr >= tegra_pcie.num_ports)
428 pp = tegra_pcie.port + nr;
429 pp->root_bus_nr = sys->busnr;
431 return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys,
435 static struct hw_pci tegra_pcie_hw __initdata = {
437 .setup = tegra_pcie_setup,
438 .scan = tegra_pcie_scan_bus,
439 .map_irq = tegra_pcie_map_irq,
443 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
445 const char *err_msg[] = {
452 "Response decoding error",
453 "AXI response decoding error",
454 "Transcation timeout",
459 code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
460 signature = afi_readl(AFI_INTR_SIGNATURE);
461 afi_writel(0, AFI_INTR_CODE);
463 if (code == AFI_INTR_LEGACY)
466 if (code >= ARRAY_SIZE(err_msg))
470 * do not pollute kernel log with master abort reports since they
471 * happen a lot during enumeration
473 if (code == AFI_INTR_MASTER_ABORT)
474 pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
476 pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
481 static void tegra_pcie_setup_translations(void)
487 /* Bar 0: config Bar */
488 fpci_bar = ((u32)0xfdff << 16);
490 axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
491 afi_writel(axi_address, AFI_AXI_BAR0_START);
492 afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
493 afi_writel(fpci_bar, AFI_FPCI_BAR0);
495 /* Bar 1: extended config Bar */
496 fpci_bar = ((u32)0xfe1 << 20);
497 size = PCIE_EXT_CFG_SZ;
498 axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
499 afi_writel(axi_address, AFI_AXI_BAR1_START);
500 afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
501 afi_writel(fpci_bar, AFI_FPCI_BAR1);
503 /* Bar 2: downstream IO bar */
504 fpci_bar = ((__u32)0xfdfc << 16);
506 axi_address = TEGRA_PCIE_IO_BASE;
507 afi_writel(axi_address, AFI_AXI_BAR2_START);
508 afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
509 afi_writel(fpci_bar, AFI_FPCI_BAR2);
511 /* Bar 3: prefetchable memory BAR */
512 fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
513 size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1;
514 axi_address = PREFETCH_MEM_BASE_0;
515 afi_writel(axi_address, AFI_AXI_BAR3_START);
516 afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
517 afi_writel(fpci_bar, AFI_FPCI_BAR3);
519 /* Bar 4: non prefetchable memory BAR */
520 fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1;
521 size = MEM_SIZE_0 + MEM_SIZE_1;
522 axi_address = MEM_BASE_0;
523 afi_writel(axi_address, AFI_AXI_BAR4_START);
524 afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
525 afi_writel(fpci_bar, AFI_FPCI_BAR4);
527 /* Bar 5: NULL out the remaining BAR as it is not used */
531 afi_writel(axi_address, AFI_AXI_BAR5_START);
532 afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
533 afi_writel(fpci_bar, AFI_FPCI_BAR5);
535 /* map all upstream transactions as uncached */
536 afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
537 afi_writel(0, AFI_CACHE_BAR0_SZ);
538 afi_writel(0, AFI_CACHE_BAR1_ST);
539 afi_writel(0, AFI_CACHE_BAR1_SZ);
542 afi_writel(0, AFI_MSI_FPCI_BAR_ST);
543 afi_writel(0, AFI_MSI_BAR_SZ);
544 afi_writel(0, AFI_MSI_AXI_BAR_ST);
545 afi_writel(0, AFI_MSI_BAR_SZ);
548 static int tegra_pcie_enable_controller(void)
553 /* Enable slot clock and pulse the reset signals */
554 for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
555 val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN;
556 afi_writel(val, reg);
557 val &= ~AFI_PEX_CTRL_RST;
558 afi_writel(val, reg);
560 val = afi_readl(reg) | AFI_PEX_CTRL_RST;
561 afi_writel(val, reg);
564 /* Enable dual controller and both ports */
565 val = afi_readl(AFI_PCIE_CONFIG);
566 val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
567 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
568 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
569 val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
570 afi_writel(val, AFI_PCIE_CONFIG);
572 val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
573 afi_writel(val, AFI_FUSE);
575 /* Initialze internal PHY, enable up to 16 PCIE lanes */
576 pads_writel(0x0, PADS_CTL_SEL);
578 /* override IDDQ to 1 on all 4 lanes */
579 val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
580 pads_writel(val, PADS_CTL);
583 * set up PHY PLL inputs select PLLE output as refclock,
584 * set TX ref sel to div10 (not div5)
586 val = pads_readl(PADS_PLL_CTL);
587 val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
588 val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
589 pads_writel(val, PADS_PLL_CTL);
591 /* take PLL out of reset */
592 val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
593 pads_writel(val, PADS_PLL_CTL);
596 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
597 * This doesn't exist in the documentation
599 pads_writel(0xfa5cfa5c, 0xc8);
601 /* Wait for the PLL to lock */
604 val = pads_readl(PADS_PLL_CTL);
605 usleep_range(1000, 1000);
606 if (--timeout == 0) {
607 pr_err("Tegra PCIe error: timeout waiting for PLL\n");
610 } while (!(val & PADS_PLL_CTL_LOCKDET));
612 /* turn off IDDQ override */
613 val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
614 pads_writel(val, PADS_CTL);
616 /* enable TX/RX data */
617 val = pads_readl(PADS_CTL);
618 val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
619 pads_writel(val, PADS_CTL);
621 /* Take the PCIe interface module out of reset */
622 tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
624 /* Finally enable PCIe */
625 val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
626 afi_writel(val, AFI_CONFIGURATION);
628 val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
629 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
630 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
631 afi_writel(val, AFI_AFI_INTR_ENABLE);
632 afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
634 /* FIXME: No MSI for now, only INT */
635 afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
637 /* Disable all execptions */
638 afi_writel(0, AFI_FPCI_ERROR_MASKS);
643 static void tegra_pcie_xclk_clamp(bool clamp)
647 reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
650 reg |= PMC_SCRATCH42_PCX_CLAMP;
652 pmc_writel(reg, PMC_SCRATCH42);
655 static void tegra_pcie_power_off(void)
657 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
658 tegra_periph_reset_assert(tegra_pcie.afi_clk);
659 tegra_periph_reset_assert(tegra_pcie.pex_clk);
661 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
662 tegra_pcie_xclk_clamp(true);
665 static int tegra_pcie_power_regate(void)
669 tegra_pcie_power_off();
671 tegra_pcie_xclk_clamp(true);
673 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
674 tegra_periph_reset_assert(tegra_pcie.afi_clk);
676 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
679 pr_err("PCIE: powerup sequence failed: %d\n", err);
683 tegra_periph_reset_deassert(tegra_pcie.afi_clk);
685 tegra_pcie_xclk_clamp(false);
687 clk_prepare_enable(tegra_pcie.afi_clk);
688 clk_prepare_enable(tegra_pcie.pex_clk);
689 return clk_prepare_enable(tegra_pcie.pll_e);
692 static int tegra_pcie_clocks_get(void)
696 tegra_pcie.pex_clk = clk_get(NULL, "pex");
697 if (IS_ERR(tegra_pcie.pex_clk))
698 return PTR_ERR(tegra_pcie.pex_clk);
700 tegra_pcie.afi_clk = clk_get(NULL, "afi");
701 if (IS_ERR(tegra_pcie.afi_clk)) {
702 err = PTR_ERR(tegra_pcie.afi_clk);
706 tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
707 if (IS_ERR(tegra_pcie.pcie_xclk)) {
708 err = PTR_ERR(tegra_pcie.pcie_xclk);
712 tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
713 if (IS_ERR(tegra_pcie.pll_e)) {
714 err = PTR_ERR(tegra_pcie.pll_e);
721 clk_put(tegra_pcie.pcie_xclk);
723 clk_put(tegra_pcie.afi_clk);
725 clk_put(tegra_pcie.pex_clk);
730 static void tegra_pcie_clocks_put(void)
732 clk_put(tegra_pcie.pll_e);
733 clk_put(tegra_pcie.pcie_xclk);
734 clk_put(tegra_pcie.afi_clk);
735 clk_put(tegra_pcie.pex_clk);
738 static int __init tegra_pcie_get_resources(void)
742 err = tegra_pcie_clocks_get();
744 pr_err("PCIE: failed to get clocks: %d\n", err);
748 err = tegra_pcie_power_regate();
750 pr_err("PCIE: failed to power up: %d\n", err);
754 tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
755 if (tegra_pcie.regs == NULL) {
756 pr_err("PCIE: Failed to map PCI/AFI registers\n");
761 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
762 IRQF_SHARED, "PCIE", &tegra_pcie);
764 pr_err("PCIE: Failed to register IRQ: %d\n", err);
767 set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
772 iounmap(tegra_pcie.regs);
774 tegra_pcie_power_off();
776 tegra_pcie_clocks_put();
782 * FIXME: If there are no PCIe cards attached, then calling this function
783 * can result in the increase of the bootup time as there are big timeout
786 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
787 static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
795 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
797 reg = readl(pp->base + RP_VEND_XP);
799 if (reg & RP_VEND_XP_DL_UP)
807 pr_err("PCIE: port %d: link down, retrying\n", idx);
811 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
813 reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
815 if (reg & 0x20000000)
823 /* Pulse the PEX reset */
824 reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
825 afi_writel(reg, reset_reg);
827 reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
828 afi_writel(reg, reset_reg);
836 static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
838 struct tegra_pcie_port *pp;
840 pp = tegra_pcie.port + tegra_pcie.num_ports;
843 pp->base = tegra_pcie.regs + offset;
844 pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
848 printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
852 tegra_pcie.num_ports++;
854 pp->root_bus_nr = -1;
855 memset(pp->res, 0, sizeof(pp->res));
858 int __init tegra_pcie_init(bool init_port0, bool init_port1)
862 if (!(init_port0 || init_port1))
867 err = tegra_pcie_get_resources();
871 err = tegra_pcie_enable_controller();
875 /* setup the AFI address translations */
876 tegra_pcie_setup_translations();
879 tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
882 tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
884 pci_common_init(&tegra_pcie_hw);