2 * arch/arm/mach-tegra/pci.c
4 * PCIe host controller driver for TEGRA(2) SOCs
6 * Copyright (c) 2010, CompuLab, Ltd.
7 * Author: Mike Rapoport <mike@compulab.co.il>
9 * Based on NVIDIA PCIe driver
10 * Copyright (c) 2008-2009, NVIDIA Corporation.
12 * Bits taken from arch/arm/mach-dove/pcie.c
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
29 #include <linux/kernel.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/export.h>
36 #include <linux/clk/tegra.h>
37 #include <linux/tegra-powergate.h>
39 #include <asm/sizes.h>
40 #include <asm/mach/pci.h>
45 /* Hack - need to parse this from DT */
46 #define INT_PCIE_INTR 130
48 /* register definitions */
49 #define AFI_OFFSET 0x3800
50 #define PADS_OFFSET 0x3000
51 #define RP0_OFFSET 0x0000
52 #define RP1_OFFSET 0x1000
54 #define AFI_AXI_BAR0_SZ 0x00
55 #define AFI_AXI_BAR1_SZ 0x04
56 #define AFI_AXI_BAR2_SZ 0x08
57 #define AFI_AXI_BAR3_SZ 0x0c
58 #define AFI_AXI_BAR4_SZ 0x10
59 #define AFI_AXI_BAR5_SZ 0x14
61 #define AFI_AXI_BAR0_START 0x18
62 #define AFI_AXI_BAR1_START 0x1c
63 #define AFI_AXI_BAR2_START 0x20
64 #define AFI_AXI_BAR3_START 0x24
65 #define AFI_AXI_BAR4_START 0x28
66 #define AFI_AXI_BAR5_START 0x2c
68 #define AFI_FPCI_BAR0 0x30
69 #define AFI_FPCI_BAR1 0x34
70 #define AFI_FPCI_BAR2 0x38
71 #define AFI_FPCI_BAR3 0x3c
72 #define AFI_FPCI_BAR4 0x40
73 #define AFI_FPCI_BAR5 0x44
75 #define AFI_CACHE_BAR0_SZ 0x48
76 #define AFI_CACHE_BAR0_ST 0x4c
77 #define AFI_CACHE_BAR1_SZ 0x50
78 #define AFI_CACHE_BAR1_ST 0x54
80 #define AFI_MSI_BAR_SZ 0x60
81 #define AFI_MSI_FPCI_BAR_ST 0x64
82 #define AFI_MSI_AXI_BAR_ST 0x68
84 #define AFI_CONFIGURATION 0xac
85 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
87 #define AFI_FPCI_ERROR_MASKS 0xb0
89 #define AFI_INTR_MASK 0xb4
90 #define AFI_INTR_MASK_INT_MASK (1 << 0)
91 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
93 #define AFI_INTR_CODE 0xb8
94 #define AFI_INTR_CODE_MASK 0xf
95 #define AFI_INTR_MASTER_ABORT 4
96 #define AFI_INTR_LEGACY 6
98 #define AFI_INTR_SIGNATURE 0xbc
99 #define AFI_SM_INTR_ENABLE 0xc4
101 #define AFI_AFI_INTR_ENABLE 0xc8
102 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
103 #define AFI_INTR_EN_INI_DECERR (1 << 1)
104 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
105 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
106 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
107 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
108 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
109 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
111 #define AFI_PCIE_CONFIG 0x0f8
112 #define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1)
113 #define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2)
114 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
115 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
116 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
118 #define AFI_FUSE 0x104
119 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
121 #define AFI_PEX0_CTRL 0x110
122 #define AFI_PEX1_CTRL 0x118
123 #define AFI_PEX_CTRL_RST (1 << 0)
124 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
126 #define RP_VEND_XP 0x00000F00
127 #define RP_VEND_XP_DL_UP (1 << 30)
129 #define RP_LINK_CONTROL_STATUS 0x00000090
130 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
132 #define PADS_CTL_SEL 0x0000009C
134 #define PADS_CTL 0x000000A0
135 #define PADS_CTL_IDDQ_1L (1 << 0)
136 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
137 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
139 #define PADS_PLL_CTL 0x000000B8
140 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
141 #define PADS_PLL_CTL_LOCKDET (1 << 8)
142 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
143 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
144 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
145 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
146 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
147 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
148 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
150 /* PMC access is required for PCIE xclk (un)clamping */
151 #define PMC_SCRATCH42 0x144
152 #define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
154 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
156 #define pmc_writel(value, reg) \
157 __raw_writel(value, reg_pmc_base + (reg))
158 #define pmc_readl(reg) \
159 __raw_readl(reg_pmc_base + (reg))
162 * Tegra2 defines 1GB in the AXI address map for PCIe.
164 * That address space is split into different regions, with sizes and
165 * offsets as follows:
167 * 0x80000000 - 0x80003fff - PCI controller registers
168 * 0x80004000 - 0x80103fff - PCI configuration space
169 * 0x80104000 - 0x80203fff - PCI extended configuration space
170 * 0x80203fff - 0x803fffff - unused
171 * 0x80400000 - 0x8040ffff - downstream IO
172 * 0x80410000 - 0x8fffffff - unused
173 * 0x90000000 - 0x9fffffff - non-prefetchable memory
174 * 0xa0000000 - 0xbfffffff - prefetchable memory
176 #define PCIE_REGS_SZ SZ_16K
177 #define PCIE_CFG_OFF PCIE_REGS_SZ
178 #define PCIE_CFG_SZ SZ_1M
179 #define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF)
180 #define PCIE_EXT_CFG_SZ SZ_1M
181 #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
183 #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
184 #define MEM_SIZE_0 SZ_128M
185 #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
186 #define MEM_SIZE_1 SZ_128M
187 #define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1)
188 #define PREFETCH_MEM_SIZE_0 SZ_128M
189 #define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
190 #define PREFETCH_MEM_SIZE_1 SZ_128M
192 #define PCIE_CONF_BUS(b) ((b) << 16)
193 #define PCIE_CONF_DEV(d) ((d) << 11)
194 #define PCIE_CONF_FUNC(f) ((f) << 8)
195 #define PCIE_CONF_REG(r) \
196 (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
198 struct tegra_pcie_port {
205 char mem_space_name[16];
206 char prefetch_space_name[20];
207 struct resource res[2];
210 struct tegra_pcie_info {
211 struct tegra_pcie_port port[2];
215 struct resource res_mmio;
219 struct clk *pcie_xclk;
223 static struct tegra_pcie_info tegra_pcie;
225 static inline void afi_writel(u32 value, unsigned long offset)
227 writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
230 static inline u32 afi_readl(unsigned long offset)
232 return readl(offset + AFI_OFFSET + tegra_pcie.regs);
235 static inline void pads_writel(u32 value, unsigned long offset)
237 writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
240 static inline u32 pads_readl(unsigned long offset)
242 return readl(offset + PADS_OFFSET + tegra_pcie.regs);
245 static struct tegra_pcie_port *bus_to_port(int bus)
249 for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
250 int rbus = tegra_pcie.port[i].root_bus_nr;
251 if (rbus != -1 && rbus == bus)
255 return i >= 0 ? tegra_pcie.port + i : NULL;
258 static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 *val)
261 struct tegra_pcie_port *pp = bus_to_port(bus->number);
267 return PCIBIOS_DEVICE_NOT_FOUND;
270 addr = pp->base + (where & ~0x3);
272 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
273 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
274 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
275 PCIE_CONF_REG(where));
281 *val = (*val >> (8 * (where & 3))) & 0xff;
283 *val = (*val >> (8 * (where & 3))) & 0xffff;
285 return PCIBIOS_SUCCESSFUL;
288 static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
289 int where, int size, u32 val)
291 struct tegra_pcie_port *pp = bus_to_port(bus->number);
299 return PCIBIOS_DEVICE_NOT_FOUND;
301 addr = pp->base + (where & ~0x3);
303 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
304 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
305 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
306 PCIE_CONF_REG(where));
311 return PCIBIOS_SUCCESSFUL;
315 mask = ~(0xffff << ((where & 0x3) * 8));
317 mask = ~(0xff << ((where & 0x3) * 8));
319 return PCIBIOS_BAD_REGISTER_NUMBER;
321 tmp = readl(addr) & mask;
322 tmp |= val << ((where & 0x3) * 8);
325 return PCIBIOS_SUCCESSFUL;
328 static struct pci_ops tegra_pcie_ops = {
329 .read = tegra_pcie_read_conf,
330 .write = tegra_pcie_write_conf,
333 static void tegra_pcie_fixup_bridge(struct pci_dev *dev)
337 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
338 pci_read_config_word(dev, PCI_COMMAND, ®);
339 reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
340 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
341 pci_write_config_word(dev, PCI_COMMAND, reg);
344 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
346 /* Tegra PCIE root complex wrongly reports device class */
347 static void tegra_pcie_fixup_class(struct pci_dev *dev)
349 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
351 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
352 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
354 /* Tegra PCIE requires relaxed ordering */
355 static void tegra_pcie_relax_enable(struct pci_dev *dev)
357 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
359 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
361 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
363 struct tegra_pcie_port *pp;
365 if (nr >= tegra_pcie.num_ports)
368 pp = tegra_pcie.port + nr;
369 pp->root_bus_nr = sys->busnr;
371 pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
376 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
377 "PCIe %d MEM", pp->index);
378 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
379 pp->res[0].name = pp->mem_space_name;
380 if (pp->index == 0) {
381 pp->res[0].start = MEM_BASE_0;
382 pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
384 pp->res[0].start = MEM_BASE_1;
385 pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
387 pp->res[0].flags = IORESOURCE_MEM;
388 if (request_resource(&iomem_resource, &pp->res[0]))
389 panic("Request PCIe Memory resource failed\n");
390 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
393 * IORESOURCE_MEM | IORESOURCE_PREFETCH
395 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
396 "PCIe %d PREFETCH MEM", pp->index);
397 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
398 pp->res[1].name = pp->prefetch_space_name;
399 if (pp->index == 0) {
400 pp->res[1].start = PREFETCH_MEM_BASE_0;
401 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
403 pp->res[1].start = PREFETCH_MEM_BASE_1;
404 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
406 pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
407 if (request_resource(&iomem_resource, &pp->res[1]))
408 panic("Request PCIe Prefetch Memory resource failed\n");
409 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
414 static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
416 return INT_PCIE_INTR;
419 static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
420 struct pci_sys_data *sys)
422 struct tegra_pcie_port *pp;
424 if (nr >= tegra_pcie.num_ports)
427 pp = tegra_pcie.port + nr;
428 pp->root_bus_nr = sys->busnr;
430 return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys,
434 static struct hw_pci tegra_pcie_hw __initdata = {
436 .setup = tegra_pcie_setup,
437 .scan = tegra_pcie_scan_bus,
438 .map_irq = tegra_pcie_map_irq,
442 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
444 const char *err_msg[] = {
451 "Response decoding error",
452 "AXI response decoding error",
453 "Transcation timeout",
458 code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
459 signature = afi_readl(AFI_INTR_SIGNATURE);
460 afi_writel(0, AFI_INTR_CODE);
462 if (code == AFI_INTR_LEGACY)
465 if (code >= ARRAY_SIZE(err_msg))
469 * do not pollute kernel log with master abort reports since they
470 * happen a lot during enumeration
472 if (code == AFI_INTR_MASTER_ABORT)
473 pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
475 pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
480 static void tegra_pcie_setup_translations(void)
486 /* Bar 0: config Bar */
487 fpci_bar = ((u32)0xfdff << 16);
489 axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
490 afi_writel(axi_address, AFI_AXI_BAR0_START);
491 afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
492 afi_writel(fpci_bar, AFI_FPCI_BAR0);
494 /* Bar 1: extended config Bar */
495 fpci_bar = ((u32)0xfe1 << 20);
496 size = PCIE_EXT_CFG_SZ;
497 axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
498 afi_writel(axi_address, AFI_AXI_BAR1_START);
499 afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
500 afi_writel(fpci_bar, AFI_FPCI_BAR1);
502 /* Bar 2: downstream IO bar */
503 fpci_bar = ((__u32)0xfdfc << 16);
505 axi_address = TEGRA_PCIE_IO_BASE;
506 afi_writel(axi_address, AFI_AXI_BAR2_START);
507 afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
508 afi_writel(fpci_bar, AFI_FPCI_BAR2);
510 /* Bar 3: prefetchable memory BAR */
511 fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
512 size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1;
513 axi_address = PREFETCH_MEM_BASE_0;
514 afi_writel(axi_address, AFI_AXI_BAR3_START);
515 afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
516 afi_writel(fpci_bar, AFI_FPCI_BAR3);
518 /* Bar 4: non prefetchable memory BAR */
519 fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1;
520 size = MEM_SIZE_0 + MEM_SIZE_1;
521 axi_address = MEM_BASE_0;
522 afi_writel(axi_address, AFI_AXI_BAR4_START);
523 afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
524 afi_writel(fpci_bar, AFI_FPCI_BAR4);
526 /* Bar 5: NULL out the remaining BAR as it is not used */
530 afi_writel(axi_address, AFI_AXI_BAR5_START);
531 afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
532 afi_writel(fpci_bar, AFI_FPCI_BAR5);
534 /* map all upstream transactions as uncached */
535 afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
536 afi_writel(0, AFI_CACHE_BAR0_SZ);
537 afi_writel(0, AFI_CACHE_BAR1_ST);
538 afi_writel(0, AFI_CACHE_BAR1_SZ);
541 afi_writel(0, AFI_MSI_FPCI_BAR_ST);
542 afi_writel(0, AFI_MSI_BAR_SZ);
543 afi_writel(0, AFI_MSI_AXI_BAR_ST);
544 afi_writel(0, AFI_MSI_BAR_SZ);
547 static int tegra_pcie_enable_controller(void)
552 /* Enable slot clock and pulse the reset signals */
553 for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
554 val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN;
555 afi_writel(val, reg);
556 val &= ~AFI_PEX_CTRL_RST;
557 afi_writel(val, reg);
559 val = afi_readl(reg) | AFI_PEX_CTRL_RST;
560 afi_writel(val, reg);
563 /* Enable dual controller and both ports */
564 val = afi_readl(AFI_PCIE_CONFIG);
565 val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
566 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
567 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
568 val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
569 afi_writel(val, AFI_PCIE_CONFIG);
571 val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
572 afi_writel(val, AFI_FUSE);
574 /* Initialze internal PHY, enable up to 16 PCIE lanes */
575 pads_writel(0x0, PADS_CTL_SEL);
577 /* override IDDQ to 1 on all 4 lanes */
578 val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
579 pads_writel(val, PADS_CTL);
582 * set up PHY PLL inputs select PLLE output as refclock,
583 * set TX ref sel to div10 (not div5)
585 val = pads_readl(PADS_PLL_CTL);
586 val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
587 val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
588 pads_writel(val, PADS_PLL_CTL);
590 /* take PLL out of reset */
591 val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
592 pads_writel(val, PADS_PLL_CTL);
595 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
596 * This doesn't exist in the documentation
598 pads_writel(0xfa5cfa5c, 0xc8);
600 /* Wait for the PLL to lock */
603 val = pads_readl(PADS_PLL_CTL);
604 usleep_range(1000, 1000);
605 if (--timeout == 0) {
606 pr_err("Tegra PCIe error: timeout waiting for PLL\n");
609 } while (!(val & PADS_PLL_CTL_LOCKDET));
611 /* turn off IDDQ override */
612 val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
613 pads_writel(val, PADS_CTL);
615 /* enable TX/RX data */
616 val = pads_readl(PADS_CTL);
617 val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
618 pads_writel(val, PADS_CTL);
620 /* Take the PCIe interface module out of reset */
621 tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
623 /* Finally enable PCIe */
624 val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
625 afi_writel(val, AFI_CONFIGURATION);
627 val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
628 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
629 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
630 afi_writel(val, AFI_AFI_INTR_ENABLE);
631 afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
633 /* FIXME: No MSI for now, only INT */
634 afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
636 /* Disable all execptions */
637 afi_writel(0, AFI_FPCI_ERROR_MASKS);
642 static void tegra_pcie_xclk_clamp(bool clamp)
646 reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
649 reg |= PMC_SCRATCH42_PCX_CLAMP;
651 pmc_writel(reg, PMC_SCRATCH42);
654 static void tegra_pcie_power_off(void)
656 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
657 tegra_periph_reset_assert(tegra_pcie.afi_clk);
658 tegra_periph_reset_assert(tegra_pcie.pex_clk);
660 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
661 tegra_pcie_xclk_clamp(true);
664 static int tegra_pcie_power_regate(void)
668 tegra_pcie_power_off();
670 tegra_pcie_xclk_clamp(true);
672 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
673 tegra_periph_reset_assert(tegra_pcie.afi_clk);
675 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
678 pr_err("PCIE: powerup sequence failed: %d\n", err);
682 tegra_periph_reset_deassert(tegra_pcie.afi_clk);
684 tegra_pcie_xclk_clamp(false);
686 clk_prepare_enable(tegra_pcie.afi_clk);
687 clk_prepare_enable(tegra_pcie.pex_clk);
688 return clk_prepare_enable(tegra_pcie.pll_e);
691 static int tegra_pcie_clocks_get(void)
695 tegra_pcie.pex_clk = clk_get(NULL, "pex");
696 if (IS_ERR(tegra_pcie.pex_clk))
697 return PTR_ERR(tegra_pcie.pex_clk);
699 tegra_pcie.afi_clk = clk_get(NULL, "afi");
700 if (IS_ERR(tegra_pcie.afi_clk)) {
701 err = PTR_ERR(tegra_pcie.afi_clk);
705 tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
706 if (IS_ERR(tegra_pcie.pcie_xclk)) {
707 err = PTR_ERR(tegra_pcie.pcie_xclk);
711 tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
712 if (IS_ERR(tegra_pcie.pll_e)) {
713 err = PTR_ERR(tegra_pcie.pll_e);
720 clk_put(tegra_pcie.pcie_xclk);
722 clk_put(tegra_pcie.afi_clk);
724 clk_put(tegra_pcie.pex_clk);
729 static void tegra_pcie_clocks_put(void)
731 clk_put(tegra_pcie.pll_e);
732 clk_put(tegra_pcie.pcie_xclk);
733 clk_put(tegra_pcie.afi_clk);
734 clk_put(tegra_pcie.pex_clk);
737 static int __init tegra_pcie_get_resources(void)
741 err = tegra_pcie_clocks_get();
743 pr_err("PCIE: failed to get clocks: %d\n", err);
747 err = tegra_pcie_power_regate();
749 pr_err("PCIE: failed to power up: %d\n", err);
753 tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
754 if (tegra_pcie.regs == NULL) {
755 pr_err("PCIE: Failed to map PCI/AFI registers\n");
760 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
761 IRQF_SHARED, "PCIE", &tegra_pcie);
763 pr_err("PCIE: Failed to register IRQ: %d\n", err);
766 set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
771 iounmap(tegra_pcie.regs);
773 tegra_pcie_power_off();
775 tegra_pcie_clocks_put();
781 * FIXME: If there are no PCIe cards attached, then calling this function
782 * can result in the increase of the bootup time as there are big timeout
785 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
786 static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
794 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
796 reg = readl(pp->base + RP_VEND_XP);
798 if (reg & RP_VEND_XP_DL_UP)
806 pr_err("PCIE: port %d: link down, retrying\n", idx);
810 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
812 reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
814 if (reg & 0x20000000)
822 /* Pulse the PEX reset */
823 reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
824 afi_writel(reg, reset_reg);
826 reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
827 afi_writel(reg, reset_reg);
835 static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
837 struct tegra_pcie_port *pp;
839 pp = tegra_pcie.port + tegra_pcie.num_ports;
842 pp->base = tegra_pcie.regs + offset;
843 pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
847 printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
851 tegra_pcie.num_ports++;
853 pp->root_bus_nr = -1;
854 memset(pp->res, 0, sizeof(pp->res));
857 int __init tegra_pcie_init(bool init_port0, bool init_port1)
861 if (!(init_port0 || init_port1))
866 err = tegra_pcie_get_resources();
870 err = tegra_pcie_enable_controller();
874 /* setup the AFI address translations */
875 tegra_pcie_setup_translations();
878 tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
881 tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
883 pci_common_init(&tegra_pcie_hw);