2 * arch/arm/mach-tegra/pci.c
4 * PCIe host controller driver for TEGRA(2) SOCs
6 * Copyright (c) 2010, CompuLab, Ltd.
7 * Author: Mike Rapoport <mike@compulab.co.il>
9 * Based on NVIDIA PCIe driver
10 * Copyright (c) 2008-2009, NVIDIA Corporation.
12 * Bits taken from arch/arm/mach-dove/pcie.c
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
29 #include <linux/kernel.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
36 #include <asm/sizes.h>
37 #include <asm/mach/pci.h>
39 #include <mach/pinmux.h>
40 #include <mach/iomap.h>
42 #include <mach/powergate.h>
44 /* register definitions */
45 #define AFI_OFFSET 0x3800
46 #define PADS_OFFSET 0x3000
47 #define RP0_OFFSET 0x0000
48 #define RP1_OFFSET 0x1000
50 #define AFI_AXI_BAR0_SZ 0x00
51 #define AFI_AXI_BAR1_SZ 0x04
52 #define AFI_AXI_BAR2_SZ 0x08
53 #define AFI_AXI_BAR3_SZ 0x0c
54 #define AFI_AXI_BAR4_SZ 0x10
55 #define AFI_AXI_BAR5_SZ 0x14
57 #define AFI_AXI_BAR0_START 0x18
58 #define AFI_AXI_BAR1_START 0x1c
59 #define AFI_AXI_BAR2_START 0x20
60 #define AFI_AXI_BAR3_START 0x24
61 #define AFI_AXI_BAR4_START 0x28
62 #define AFI_AXI_BAR5_START 0x2c
64 #define AFI_FPCI_BAR0 0x30
65 #define AFI_FPCI_BAR1 0x34
66 #define AFI_FPCI_BAR2 0x38
67 #define AFI_FPCI_BAR3 0x3c
68 #define AFI_FPCI_BAR4 0x40
69 #define AFI_FPCI_BAR5 0x44
71 #define AFI_CACHE_BAR0_SZ 0x48
72 #define AFI_CACHE_BAR0_ST 0x4c
73 #define AFI_CACHE_BAR1_SZ 0x50
74 #define AFI_CACHE_BAR1_ST 0x54
76 #define AFI_MSI_BAR_SZ 0x60
77 #define AFI_MSI_FPCI_BAR_ST 0x64
78 #define AFI_MSI_AXI_BAR_ST 0x68
80 #define AFI_CONFIGURATION 0xac
81 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
83 #define AFI_FPCI_ERROR_MASKS 0xb0
85 #define AFI_INTR_MASK 0xb4
86 #define AFI_INTR_MASK_INT_MASK (1 << 0)
87 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
89 #define AFI_INTR_CODE 0xb8
90 #define AFI_INTR_CODE_MASK 0xf
91 #define AFI_INTR_MASTER_ABORT 4
92 #define AFI_INTR_LEGACY 6
94 #define AFI_INTR_SIGNATURE 0xbc
95 #define AFI_SM_INTR_ENABLE 0xc4
97 #define AFI_AFI_INTR_ENABLE 0xc8
98 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
99 #define AFI_INTR_EN_INI_DECERR (1 << 1)
100 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
101 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
102 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
103 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
104 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
105 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
107 #define AFI_PCIE_CONFIG 0x0f8
108 #define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1)
109 #define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2)
110 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
111 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
112 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
114 #define AFI_FUSE 0x104
115 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
117 #define AFI_PEX0_CTRL 0x110
118 #define AFI_PEX1_CTRL 0x118
119 #define AFI_PEX_CTRL_RST (1 << 0)
120 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
122 #define RP_VEND_XP 0x00000F00
123 #define RP_VEND_XP_DL_UP (1 << 30)
125 #define RP_LINK_CONTROL_STATUS 0x00000090
126 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
128 #define PADS_CTL_SEL 0x0000009C
130 #define PADS_CTL 0x000000A0
131 #define PADS_CTL_IDDQ_1L (1 << 0)
132 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
133 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
135 #define PADS_PLL_CTL 0x000000B8
136 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
137 #define PADS_PLL_CTL_LOCKDET (1 << 8)
138 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
139 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
140 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
141 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
142 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
143 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
144 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
146 /* PMC access is required for PCIE xclk (un)clamping */
147 #define PMC_SCRATCH42 0x144
148 #define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
150 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
152 #define pmc_writel(value, reg) \
153 __raw_writel(value, (u32)reg_pmc_base + (reg))
154 #define pmc_readl(reg) \
155 __raw_readl((u32)reg_pmc_base + (reg))
158 * Tegra2 defines 1GB in the AXI address map for PCIe.
160 * That address space is split into different regions, with sizes and
161 * offsets as follows:
163 * 0x80000000 - 0x80003fff - PCI controller registers
164 * 0x80004000 - 0x80103fff - PCI configuration space
165 * 0x80104000 - 0x80203fff - PCI extended configuration space
166 * 0x80203fff - 0x803fffff - unused
167 * 0x80400000 - 0x8040ffff - downstream IO
168 * 0x80410000 - 0x8fffffff - unused
169 * 0x90000000 - 0x9fffffff - non-prefetchable memory
170 * 0xa0000000 - 0xbfffffff - prefetchable memory
172 #define TEGRA_PCIE_BASE 0x80000000
174 #define PCIE_REGS_SZ SZ_16K
175 #define PCIE_CFG_OFF PCIE_REGS_SZ
176 #define PCIE_CFG_SZ SZ_1M
177 #define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF)
178 #define PCIE_EXT_CFG_SZ SZ_1M
179 #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
181 #define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M)
182 #define MMIO_SIZE SZ_64K
183 #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
184 #define MEM_SIZE_0 SZ_128M
185 #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
186 #define MEM_SIZE_1 SZ_128M
187 #define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1)
188 #define PREFETCH_MEM_SIZE_0 SZ_128M
189 #define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
190 #define PREFETCH_MEM_SIZE_1 SZ_128M
192 #define PCIE_CONF_BUS(b) ((b) << 16)
193 #define PCIE_CONF_DEV(d) ((d) << 11)
194 #define PCIE_CONF_FUNC(f) ((f) << 8)
195 #define PCIE_CONF_REG(r) \
196 (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
198 struct tegra_pcie_port {
205 char io_space_name[16];
206 char mem_space_name[16];
207 char prefetch_space_name[20];
208 struct resource res[3];
211 struct tegra_pcie_info {
212 struct tegra_pcie_port port[2];
216 struct resource res_mmio;
220 struct clk *pcie_xclk;
224 static struct tegra_pcie_info tegra_pcie = {
228 .end = MMIO_BASE + MMIO_SIZE - 1,
229 .flags = IORESOURCE_MEM,
233 void __iomem *tegra_pcie_io_base;
234 EXPORT_SYMBOL(tegra_pcie_io_base);
236 static inline void afi_writel(u32 value, unsigned long offset)
238 writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
241 static inline u32 afi_readl(unsigned long offset)
243 return readl(offset + AFI_OFFSET + tegra_pcie.regs);
246 static inline void pads_writel(u32 value, unsigned long offset)
248 writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
251 static inline u32 pads_readl(unsigned long offset)
253 return readl(offset + PADS_OFFSET + tegra_pcie.regs);
256 static struct tegra_pcie_port *bus_to_port(int bus)
260 for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
261 int rbus = tegra_pcie.port[i].root_bus_nr;
262 if (rbus != -1 && rbus == bus)
266 return i >= 0 ? tegra_pcie.port + i : NULL;
269 static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
270 int where, int size, u32 *val)
272 struct tegra_pcie_port *pp = bus_to_port(bus->number);
278 return PCIBIOS_DEVICE_NOT_FOUND;
281 addr = pp->base + (where & ~0x3);
283 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
284 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
285 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
286 PCIE_CONF_REG(where));
292 *val = (*val >> (8 * (where & 3))) & 0xff;
294 *val = (*val >> (8 * (where & 3))) & 0xffff;
296 return PCIBIOS_SUCCESSFUL;
299 static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
300 int where, int size, u32 val)
302 struct tegra_pcie_port *pp = bus_to_port(bus->number);
310 return PCIBIOS_DEVICE_NOT_FOUND;
312 addr = pp->base + (where & ~0x3);
314 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
315 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
316 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
317 PCIE_CONF_REG(where));
322 return PCIBIOS_SUCCESSFUL;
326 mask = ~(0xffff << ((where & 0x3) * 8));
328 mask = ~(0xff << ((where & 0x3) * 8));
330 return PCIBIOS_BAD_REGISTER_NUMBER;
332 tmp = readl(addr) & mask;
333 tmp |= val << ((where & 0x3) * 8);
336 return PCIBIOS_SUCCESSFUL;
339 static struct pci_ops tegra_pcie_ops = {
340 .read = tegra_pcie_read_conf,
341 .write = tegra_pcie_write_conf,
344 static void __devinit tegra_pcie_fixup_bridge(struct pci_dev *dev)
348 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
349 pci_read_config_word(dev, PCI_COMMAND, ®);
350 reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
351 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
352 pci_write_config_word(dev, PCI_COMMAND, reg);
355 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
357 /* Tegra PCIE root complex wrongly reports device class */
358 static void __devinit tegra_pcie_fixup_class(struct pci_dev *dev)
360 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
362 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
363 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
365 /* Tegra PCIE requires relaxed ordering */
366 static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
369 int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
372 dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
376 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
377 val16 |= PCI_EXP_DEVCTL_RELAX_EN;
378 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
380 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
382 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
384 struct tegra_pcie_port *pp;
386 if (nr >= tegra_pcie.num_ports)
389 pp = tegra_pcie.port + nr;
390 pp->root_bus_nr = sys->busnr;
395 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
396 "PCIe %d I/O", pp->index);
397 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
398 pp->res[0].name = pp->io_space_name;
399 if (pp->index == 0) {
400 pp->res[0].start = PCIBIOS_MIN_IO;
401 pp->res[0].end = pp->res[0].start + SZ_32K - 1;
403 pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K;
404 pp->res[0].end = IO_SPACE_LIMIT;
406 pp->res[0].flags = IORESOURCE_IO;
407 if (request_resource(&ioport_resource, &pp->res[0]))
408 panic("Request PCIe IO resource failed\n");
409 sys->resource[0] = &pp->res[0];
414 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
415 "PCIe %d MEM", pp->index);
416 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
417 pp->res[1].name = pp->mem_space_name;
418 if (pp->index == 0) {
419 pp->res[1].start = MEM_BASE_0;
420 pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1;
422 pp->res[1].start = MEM_BASE_1;
423 pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1;
425 pp->res[1].flags = IORESOURCE_MEM;
426 if (request_resource(&iomem_resource, &pp->res[1]))
427 panic("Request PCIe Memory resource failed\n");
428 sys->resource[1] = &pp->res[1];
431 * IORESOURCE_MEM | IORESOURCE_PREFETCH
433 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
434 "PCIe %d PREFETCH MEM", pp->index);
435 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
436 pp->res[2].name = pp->prefetch_space_name;
437 if (pp->index == 0) {
438 pp->res[2].start = PREFETCH_MEM_BASE_0;
439 pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1;
441 pp->res[2].start = PREFETCH_MEM_BASE_1;
442 pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1;
444 pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
445 if (request_resource(&iomem_resource, &pp->res[2]))
446 panic("Request PCIe Prefetch Memory resource failed\n");
447 sys->resource[2] = &pp->res[2];
452 static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
454 return INT_PCIE_INTR;
457 static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
458 struct pci_sys_data *sys)
460 struct tegra_pcie_port *pp;
462 if (nr >= tegra_pcie.num_ports)
465 pp = tegra_pcie.port + nr;
466 pp->root_bus_nr = sys->busnr;
468 return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys);
471 static struct hw_pci tegra_pcie_hw __initdata = {
473 .setup = tegra_pcie_setup,
474 .scan = tegra_pcie_scan_bus,
475 .swizzle = pci_std_swizzle,
476 .map_irq = tegra_pcie_map_irq,
480 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
482 const char *err_msg[] = {
489 "Response decoding error",
490 "AXI response decoding error",
491 "Transcation timeout",
496 code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
497 signature = afi_readl(AFI_INTR_SIGNATURE);
498 afi_writel(0, AFI_INTR_CODE);
500 if (code == AFI_INTR_LEGACY)
503 if (code >= ARRAY_SIZE(err_msg))
507 * do not pollute kernel log with master abort reports since they
508 * happen a lot during enumeration
510 if (code == AFI_INTR_MASTER_ABORT)
511 pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
513 pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
518 static void tegra_pcie_setup_translations(void)
524 /* Bar 0: config Bar */
525 fpci_bar = ((u32)0xfdff << 16);
527 axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
528 afi_writel(axi_address, AFI_AXI_BAR0_START);
529 afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
530 afi_writel(fpci_bar, AFI_FPCI_BAR0);
532 /* Bar 1: extended config Bar */
533 fpci_bar = ((u32)0xfe1 << 20);
534 size = PCIE_EXT_CFG_SZ;
535 axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
536 afi_writel(axi_address, AFI_AXI_BAR1_START);
537 afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
538 afi_writel(fpci_bar, AFI_FPCI_BAR1);
540 /* Bar 2: downstream IO bar */
541 fpci_bar = ((__u32)0xfdfc << 16);
543 axi_address = MMIO_BASE;
544 afi_writel(axi_address, AFI_AXI_BAR2_START);
545 afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
546 afi_writel(fpci_bar, AFI_FPCI_BAR2);
548 /* Bar 3: prefetchable memory BAR */
549 fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
550 size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1;
551 axi_address = PREFETCH_MEM_BASE_0;
552 afi_writel(axi_address, AFI_AXI_BAR3_START);
553 afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
554 afi_writel(fpci_bar, AFI_FPCI_BAR3);
556 /* Bar 4: non prefetchable memory BAR */
557 fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1;
558 size = MEM_SIZE_0 + MEM_SIZE_1;
559 axi_address = MEM_BASE_0;
560 afi_writel(axi_address, AFI_AXI_BAR4_START);
561 afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
562 afi_writel(fpci_bar, AFI_FPCI_BAR4);
564 /* Bar 5: NULL out the remaining BAR as it is not used */
568 afi_writel(axi_address, AFI_AXI_BAR5_START);
569 afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
570 afi_writel(fpci_bar, AFI_FPCI_BAR5);
572 /* map all upstream transactions as uncached */
573 afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
574 afi_writel(0, AFI_CACHE_BAR0_SZ);
575 afi_writel(0, AFI_CACHE_BAR1_ST);
576 afi_writel(0, AFI_CACHE_BAR1_SZ);
579 afi_writel(0, AFI_MSI_FPCI_BAR_ST);
580 afi_writel(0, AFI_MSI_BAR_SZ);
581 afi_writel(0, AFI_MSI_AXI_BAR_ST);
582 afi_writel(0, AFI_MSI_BAR_SZ);
585 static void tegra_pcie_enable_controller(void)
590 /* Enable slot clock and pulse the reset signals */
591 for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
592 val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN;
593 afi_writel(val, reg);
594 val &= ~AFI_PEX_CTRL_RST;
595 afi_writel(val, reg);
597 val = afi_readl(reg) | AFI_PEX_CTRL_RST;
598 afi_writel(val, reg);
601 /* Enable dual controller and both ports */
602 val = afi_readl(AFI_PCIE_CONFIG);
603 val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
604 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
605 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
606 val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
607 afi_writel(val, AFI_PCIE_CONFIG);
609 val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
610 afi_writel(val, AFI_FUSE);
612 /* Initialze internal PHY, enable up to 16 PCIE lanes */
613 pads_writel(0x0, PADS_CTL_SEL);
615 /* override IDDQ to 1 on all 4 lanes */
616 val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
617 pads_writel(val, PADS_CTL);
620 * set up PHY PLL inputs select PLLE output as refclock,
621 * set TX ref sel to div10 (not div5)
623 val = pads_readl(PADS_PLL_CTL);
624 val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
625 val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
626 pads_writel(val, PADS_PLL_CTL);
628 /* take PLL out of reset */
629 val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
630 pads_writel(val, PADS_PLL_CTL);
633 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
634 * This doesn't exist in the documentation
636 pads_writel(0xfa5cfa5c, 0xc8);
638 /* Wait for the PLL to lock */
640 val = pads_readl(PADS_PLL_CTL);
641 } while (!(val & PADS_PLL_CTL_LOCKDET));
643 /* turn off IDDQ override */
644 val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
645 pads_writel(val, PADS_CTL);
647 /* enable TX/RX data */
648 val = pads_readl(PADS_CTL);
649 val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
650 pads_writel(val, PADS_CTL);
652 /* Take the PCIe interface module out of reset */
653 tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
655 /* Finally enable PCIe */
656 val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
657 afi_writel(val, AFI_CONFIGURATION);
659 val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
660 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
661 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
662 afi_writel(val, AFI_AFI_INTR_ENABLE);
663 afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
665 /* FIXME: No MSI for now, only INT */
666 afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
668 /* Disable all execptions */
669 afi_writel(0, AFI_FPCI_ERROR_MASKS);
674 static void tegra_pcie_xclk_clamp(bool clamp)
678 reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
681 reg |= PMC_SCRATCH42_PCX_CLAMP;
683 pmc_writel(reg, PMC_SCRATCH42);
686 static void tegra_pcie_power_off(void)
688 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
689 tegra_periph_reset_assert(tegra_pcie.afi_clk);
690 tegra_periph_reset_assert(tegra_pcie.pex_clk);
692 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
693 tegra_pcie_xclk_clamp(true);
696 static int tegra_pcie_power_regate(void)
700 tegra_pcie_power_off();
702 tegra_pcie_xclk_clamp(true);
704 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
705 tegra_periph_reset_assert(tegra_pcie.afi_clk);
707 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
710 pr_err("PCIE: powerup sequence failed: %d\n", err);
714 tegra_periph_reset_deassert(tegra_pcie.afi_clk);
716 tegra_pcie_xclk_clamp(false);
718 clk_enable(tegra_pcie.afi_clk);
719 clk_enable(tegra_pcie.pex_clk);
720 return clk_enable(tegra_pcie.pll_e);
723 static int tegra_pcie_clocks_get(void)
727 tegra_pcie.pex_clk = clk_get(NULL, "pex");
728 if (IS_ERR(tegra_pcie.pex_clk))
729 return PTR_ERR(tegra_pcie.pex_clk);
731 tegra_pcie.afi_clk = clk_get(NULL, "afi");
732 if (IS_ERR(tegra_pcie.afi_clk)) {
733 err = PTR_ERR(tegra_pcie.afi_clk);
737 tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
738 if (IS_ERR(tegra_pcie.pcie_xclk)) {
739 err = PTR_ERR(tegra_pcie.pcie_xclk);
743 tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
744 if (IS_ERR(tegra_pcie.pll_e)) {
745 err = PTR_ERR(tegra_pcie.pll_e);
752 clk_put(tegra_pcie.pcie_xclk);
754 clk_put(tegra_pcie.afi_clk);
756 clk_put(tegra_pcie.pex_clk);
761 static void tegra_pcie_clocks_put(void)
763 clk_put(tegra_pcie.pll_e);
764 clk_put(tegra_pcie.pcie_xclk);
765 clk_put(tegra_pcie.afi_clk);
766 clk_put(tegra_pcie.pex_clk);
769 static int __init tegra_pcie_get_resources(void)
771 struct resource *res_mmio = &tegra_pcie.res_mmio;
774 err = tegra_pcie_clocks_get();
776 pr_err("PCIE: failed to get clocks: %d\n", err);
780 err = tegra_pcie_power_regate();
782 pr_err("PCIE: failed to power up: %d\n", err);
786 tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
787 if (tegra_pcie.regs == NULL) {
788 pr_err("PCIE: Failed to map PCI/AFI registers\n");
793 err = request_resource(&iomem_resource, res_mmio);
795 pr_err("PCIE: Failed to request resources: %d\n", err);
799 tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
800 resource_size(res_mmio));
801 if (tegra_pcie_io_base == NULL) {
802 pr_err("PCIE: Failed to map IO\n");
807 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
808 IRQF_SHARED, "PCIE", &tegra_pcie);
810 pr_err("PCIE: Failed to register IRQ: %d\n", err);
813 set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
818 iounmap(tegra_pcie_io_base);
820 release_resource(&tegra_pcie.res_mmio);
822 iounmap(tegra_pcie.regs);
824 tegra_pcie_power_off();
826 tegra_pcie_clocks_put();
832 * FIXME: If there are no PCIe cards attached, then calling this function
833 * can result in the increase of the bootup time as there are big timeout
836 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
837 static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
845 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
847 reg = readl(pp->base + RP_VEND_XP);
849 if (reg & RP_VEND_XP_DL_UP)
857 pr_err("PCIE: port %d: link down, retrying\n", idx);
861 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
863 reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
865 if (reg & 0x20000000)
873 /* Pulse the PEX reset */
874 reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
875 afi_writel(reg, reset_reg);
877 reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
878 afi_writel(reg, reset_reg);
886 static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
888 struct tegra_pcie_port *pp;
890 pp = tegra_pcie.port + tegra_pcie.num_ports;
893 pp->base = tegra_pcie.regs + offset;
894 pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
898 printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
902 tegra_pcie.num_ports++;
904 pp->root_bus_nr = -1;
905 memset(pp->res, 0, sizeof(pp->res));
908 int __init tegra_pcie_init(bool init_port0, bool init_port1)
912 if (!(init_port0 || init_port1))
917 err = tegra_pcie_get_resources();
921 tegra_pcie_enable_controller();
923 /* setup the AFI address translations */
924 tegra_pcie_setup_translations();
927 tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
930 tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
932 pci_common_init(&tegra_pcie_hw);