2 * linux/arch/arm/mach-tegra/pinmux.c
4 * Copyright (C) 2010 Google, Inc.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/spinlock.h>
24 #include <mach/iomap.h>
25 #include <mach/pinmux.h>
27 #define HSM_EN(reg) (((reg) >> 2) & 0x1)
28 #define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
29 #define LPMD(reg) (((reg) >> 4) & 0x3)
30 #define DRVDN(reg) (((reg) >> 12) & 0x1f)
31 #define DRVUP(reg) (((reg) >> 20) & 0x1f)
32 #define SLWR(reg) (((reg) >> 28) & 0x3)
33 #define SLWF(reg) (((reg) >> 30) & 0x3)
35 static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
36 static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
38 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
39 [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
40 [TEGRA_MUX_APB_CLK] = "APB_CLK",
41 [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
42 [TEGRA_MUX_CRT] = "CRT",
43 [TEGRA_MUX_DAP1] = "DAP1",
44 [TEGRA_MUX_DAP2] = "DAP2",
45 [TEGRA_MUX_DAP3] = "DAP3",
46 [TEGRA_MUX_DAP4] = "DAP4",
47 [TEGRA_MUX_DAP5] = "DAP5",
48 [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
49 [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
50 [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
51 [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
52 [TEGRA_MUX_GMI] = "GMI",
53 [TEGRA_MUX_GMI_INT] = "GMI_INT",
54 [TEGRA_MUX_HDMI] = "HDMI",
55 [TEGRA_MUX_I2C] = "I2C",
56 [TEGRA_MUX_I2C2] = "I2C2",
57 [TEGRA_MUX_I2C3] = "I2C3",
58 [TEGRA_MUX_IDE] = "IDE",
59 [TEGRA_MUX_IRDA] = "IRDA",
60 [TEGRA_MUX_KBC] = "KBC",
61 [TEGRA_MUX_MIO] = "MIO",
62 [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
63 [TEGRA_MUX_NAND] = "NAND",
64 [TEGRA_MUX_OSC] = "OSC",
65 [TEGRA_MUX_OWR] = "OWR",
66 [TEGRA_MUX_PCIE] = "PCIE",
67 [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
68 [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
69 [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
70 [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
71 [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
72 [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
73 [TEGRA_MUX_PWM] = "PWM",
74 [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
75 [TEGRA_MUX_PWR_ON] = "PWR_ON",
76 [TEGRA_MUX_RTCK] = "RTCK",
77 [TEGRA_MUX_SDIO1] = "SDIO1",
78 [TEGRA_MUX_SDIO2] = "SDIO2",
79 [TEGRA_MUX_SDIO3] = "SDIO3",
80 [TEGRA_MUX_SDIO4] = "SDIO4",
81 [TEGRA_MUX_SFLASH] = "SFLASH",
82 [TEGRA_MUX_SPDIF] = "SPDIF",
83 [TEGRA_MUX_SPI1] = "SPI1",
84 [TEGRA_MUX_SPI2] = "SPI2",
85 [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
86 [TEGRA_MUX_SPI3] = "SPI3",
87 [TEGRA_MUX_SPI4] = "SPI4",
88 [TEGRA_MUX_TRACE] = "TRACE",
89 [TEGRA_MUX_TWC] = "TWC",
90 [TEGRA_MUX_UARTA] = "UARTA",
91 [TEGRA_MUX_UARTB] = "UARTB",
92 [TEGRA_MUX_UARTC] = "UARTC",
93 [TEGRA_MUX_UARTD] = "UARTD",
94 [TEGRA_MUX_UARTE] = "UARTE",
95 [TEGRA_MUX_ULPI] = "ULPI",
96 [TEGRA_MUX_VI] = "VI",
97 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
98 [TEGRA_MUX_XIO] = "XIO",
99 [TEGRA_MUX_SAFE] = "<safe>",
102 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
103 [TEGRA_DRIVE_DIV_8] = "DIV_8",
104 [TEGRA_DRIVE_DIV_4] = "DIV_4",
105 [TEGRA_DRIVE_DIV_2] = "DIV_2",
106 [TEGRA_DRIVE_DIV_1] = "DIV_1",
109 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
110 [TEGRA_SLEW_FASTEST] = "FASTEST",
111 [TEGRA_SLEW_FAST] = "FAST",
112 [TEGRA_SLEW_SLOW] = "SLOW",
113 [TEGRA_SLEW_SLOWEST] = "SLOWEST",
116 static DEFINE_SPINLOCK(mux_lock);
118 static const char *pingroup_name(enum tegra_pingroup pg)
120 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
123 return pingroups[pg].name;
126 static const char *func_name(enum tegra_mux_func func)
128 if (func == TEGRA_MUX_RSVD1)
131 if (func == TEGRA_MUX_RSVD2)
134 if (func == TEGRA_MUX_RSVD3)
137 if (func == TEGRA_MUX_RSVD4)
140 if (func == TEGRA_MUX_NONE)
143 if (func < 0 || func >= TEGRA_MAX_MUX)
146 return tegra_mux_names[func];
150 static const char *tri_name(unsigned long val)
152 return val ? "TRISTATE" : "NORMAL";
155 static const char *pupd_name(unsigned long val)
173 static inline unsigned long pg_readl(unsigned long offset)
175 return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
178 static inline void pg_writel(unsigned long value, unsigned long offset)
180 writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
183 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
189 enum tegra_pingroup pg = config->pingroup;
190 enum tegra_mux_func func = config->func;
192 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
195 if (pingroups[pg].mux_reg < 0)
201 if (func == TEGRA_MUX_SAFE)
202 func = pingroups[pg].func_safe;
204 if (func & TEGRA_MUX_RSVD) {
207 for (i = 0; i < 4; i++) {
208 if (pingroups[pg].funcs[i] == func) {
218 spin_lock_irqsave(&mux_lock, flags);
220 reg = pg_readl(pingroups[pg].mux_reg);
221 reg &= ~(0x3 << pingroups[pg].mux_bit);
222 reg |= mux << pingroups[pg].mux_bit;
223 pg_writel(reg, pingroups[pg].mux_reg);
225 spin_unlock_irqrestore(&mux_lock, flags);
230 int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
231 enum tegra_tristate tristate)
236 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
239 if (pingroups[pg].tri_reg < 0)
242 spin_lock_irqsave(&mux_lock, flags);
244 reg = pg_readl(pingroups[pg].tri_reg);
245 reg &= ~(0x1 << pingroups[pg].tri_bit);
247 reg |= 1 << pingroups[pg].tri_bit;
248 pg_writel(reg, pingroups[pg].tri_reg);
250 spin_unlock_irqrestore(&mux_lock, flags);
255 int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
256 enum tegra_pullupdown pupd)
261 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
264 if (pingroups[pg].pupd_reg < 0)
267 if (pupd != TEGRA_PUPD_NORMAL &&
268 pupd != TEGRA_PUPD_PULL_DOWN &&
269 pupd != TEGRA_PUPD_PULL_UP)
273 spin_lock_irqsave(&mux_lock, flags);
275 reg = pg_readl(pingroups[pg].pupd_reg);
276 reg &= ~(0x3 << pingroups[pg].pupd_bit);
277 reg |= pupd << pingroups[pg].pupd_bit;
278 pg_writel(reg, pingroups[pg].pupd_reg);
280 spin_unlock_irqrestore(&mux_lock, flags);
285 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
287 enum tegra_pingroup pingroup = config->pingroup;
288 enum tegra_mux_func func = config->func;
289 enum tegra_pullupdown pupd = config->pupd;
290 enum tegra_tristate tristate = config->tristate;
293 if (pingroups[pingroup].mux_reg >= 0) {
294 err = tegra_pinmux_set_func(config);
296 pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
297 pingroup_name(pingroup), func_name(func), err);
300 if (pingroups[pingroup].pupd_reg >= 0) {
301 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
303 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
304 pingroup_name(pingroup), pupd_name(pupd), err);
307 if (pingroups[pingroup].tri_reg >= 0) {
308 err = tegra_pinmux_set_tristate(pingroup, tristate);
310 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
311 pingroup_name(pingroup), tri_name(func), err);
315 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
319 for (i = 0; i < len; i++)
320 tegra_pinmux_config_pingroup(&config[i]);
323 static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
325 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
328 return drive_pingroups[pg].name;
331 static const char *enable_name(unsigned long val)
333 return val ? "ENABLE" : "DISABLE";
336 static const char *drive_name(unsigned long val)
338 if (val >= TEGRA_MAX_DRIVE)
341 return tegra_drive_names[val];
344 static const char *slew_name(unsigned long val)
346 if (val >= TEGRA_MAX_SLEW)
349 return tegra_slew_names[val];
352 static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
357 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
360 if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
363 spin_lock_irqsave(&mux_lock, flags);
365 reg = pg_readl(drive_pingroups[pg].reg);
366 if (hsm == TEGRA_HSM_ENABLE)
370 pg_writel(reg, drive_pingroups[pg].reg);
372 spin_unlock_irqrestore(&mux_lock, flags);
377 static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
378 enum tegra_schmitt schmitt)
382 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
385 if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
388 spin_lock_irqsave(&mux_lock, flags);
390 reg = pg_readl(drive_pingroups[pg].reg);
391 if (schmitt == TEGRA_SCHMITT_ENABLE)
395 pg_writel(reg, drive_pingroups[pg].reg);
397 spin_unlock_irqrestore(&mux_lock, flags);
402 static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
403 enum tegra_drive drive)
407 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
410 if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
413 spin_lock_irqsave(&mux_lock, flags);
415 reg = pg_readl(drive_pingroups[pg].reg);
418 pg_writel(reg, drive_pingroups[pg].reg);
420 spin_unlock_irqrestore(&mux_lock, flags);
425 static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
426 enum tegra_pull_strength pull_down)
430 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
433 if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
436 spin_lock_irqsave(&mux_lock, flags);
438 reg = pg_readl(drive_pingroups[pg].reg);
439 reg &= ~(0x1f << 12);
440 reg |= pull_down << 12;
441 pg_writel(reg, drive_pingroups[pg].reg);
443 spin_unlock_irqrestore(&mux_lock, flags);
448 static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
449 enum tegra_pull_strength pull_up)
453 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
456 if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
459 spin_lock_irqsave(&mux_lock, flags);
461 reg = pg_readl(drive_pingroups[pg].reg);
462 reg &= ~(0x1f << 12);
463 reg |= pull_up << 12;
464 pg_writel(reg, drive_pingroups[pg].reg);
466 spin_unlock_irqrestore(&mux_lock, flags);
471 static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
472 enum tegra_slew slew_rising)
476 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
479 if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
482 spin_lock_irqsave(&mux_lock, flags);
484 reg = pg_readl(drive_pingroups[pg].reg);
486 reg |= slew_rising << 28;
487 pg_writel(reg, drive_pingroups[pg].reg);
489 spin_unlock_irqrestore(&mux_lock, flags);
494 static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
495 enum tegra_slew slew_falling)
499 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
502 if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
505 spin_lock_irqsave(&mux_lock, flags);
507 reg = pg_readl(drive_pingroups[pg].reg);
509 reg |= slew_falling << 30;
510 pg_writel(reg, drive_pingroups[pg].reg);
512 spin_unlock_irqrestore(&mux_lock, flags);
517 static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
519 enum tegra_schmitt schmitt,
520 enum tegra_drive drive,
521 enum tegra_pull_strength pull_down,
522 enum tegra_pull_strength pull_up,
523 enum tegra_slew slew_rising,
524 enum tegra_slew slew_falling)
528 err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
530 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
531 drive_pinmux_name(pingroup),
532 enable_name(hsm), err);
534 err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
536 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
537 drive_pinmux_name(pingroup),
538 enable_name(schmitt), err);
540 err = tegra_drive_pinmux_set_drive(pingroup, drive);
542 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
543 drive_pinmux_name(pingroup),
544 drive_name(drive), err);
546 err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
548 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
549 drive_pinmux_name(pingroup),
552 err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
554 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
555 drive_pinmux_name(pingroup),
558 err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
560 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
561 drive_pinmux_name(pingroup),
562 slew_name(slew_rising), err);
564 err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
566 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
567 drive_pinmux_name(pingroup),
568 slew_name(slew_falling), err);
571 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
576 for (i = 0; i < len; i++)
577 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
583 config[i].slew_rising,
584 config[i].slew_falling);
587 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
591 struct tegra_pingroup_config c;
593 for (i = 0; i < len; i++) {
596 if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
600 c.func = pingroups[c.pingroup].func_safe;
601 err = tegra_pinmux_set_func(&c);
603 pr_err("%s: tegra_pinmux_set_func returned %d setting "
604 "%s to %s\n", __func__, err,
605 pingroup_name(c.pingroup), func_name(c.func));
609 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
614 for (i = 0; i < len; i++) {
616 if (config[i].pingroup < 0 ||
617 config[i].pingroup >= TEGRA_MAX_PINGROUP) {
621 err = tegra_pinmux_set_func(&config[i]);
623 pr_err("%s: tegra_pinmux_set_func returned %d setting "
624 "%s to %s\n", __func__, err,
625 pingroup_name(config[i].pingroup),
626 func_name(config[i].func));
630 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
631 int len, enum tegra_tristate tristate)
635 enum tegra_pingroup pingroup;
637 for (i = 0; i < len; i++) {
638 pingroup = config[i].pingroup;
639 if (pingroups[pingroup].tri_reg >= 0) {
640 err = tegra_pinmux_set_tristate(pingroup, tristate);
642 pr_err("pinmux: can't set pingroup %s tristate"
643 " to %s: %d\n", pingroup_name(pingroup),
644 tri_name(tristate), err);
649 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
650 int len, enum tegra_pullupdown pupd)
654 enum tegra_pingroup pingroup;
656 for (i = 0; i < len; i++) {
657 pingroup = config[i].pingroup;
658 if (pingroups[pingroup].pupd_reg >= 0) {
659 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
661 pr_err("pinmux: can't set pingroup %s pullupdown"
662 " to %s: %d\n", pingroup_name(pingroup),
663 pupd_name(pupd), err);
668 #ifdef CONFIG_DEBUG_FS
670 #include <linux/debugfs.h>
671 #include <linux/seq_file.h>
673 static void dbg_pad_field(struct seq_file *s, int len)
681 static int dbg_pinmux_show(struct seq_file *s, void *unused)
686 for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
691 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
692 len = strlen(pingroups[i].name);
693 dbg_pad_field(s, 5 - len);
695 if (pingroups[i].mux_reg < 0) {
696 seq_printf(s, "TEGRA_MUX_NONE");
697 len = strlen("NONE");
699 mux = (pg_readl(pingroups[i].mux_reg) >>
700 pingroups[i].mux_bit) & 0x3;
701 if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
702 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
705 seq_printf(s, "TEGRA_MUX_%s",
706 tegra_mux_names[pingroups[i].funcs[mux]]);
707 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
710 dbg_pad_field(s, 13-len);
712 if (pingroups[i].pupd_reg < 0) {
713 seq_printf(s, "TEGRA_PUPD_NORMAL");
714 len = strlen("NORMAL");
716 pupd = (pg_readl(pingroups[i].pupd_reg) >>
717 pingroups[i].pupd_bit) & 0x3;
718 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
719 len = strlen(pupd_name(pupd));
721 dbg_pad_field(s, 9 - len);
723 if (pingroups[i].tri_reg < 0) {
724 seq_printf(s, "TEGRA_TRI_NORMAL");
726 tri = (pg_readl(pingroups[i].tri_reg) >>
727 pingroups[i].tri_bit) & 0x1;
729 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
731 seq_printf(s, "},\n");
736 static int dbg_pinmux_open(struct inode *inode, struct file *file)
738 return single_open(file, dbg_pinmux_show, &inode->i_private);
741 static const struct file_operations debug_fops = {
742 .open = dbg_pinmux_open,
745 .release = single_release,
748 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
753 for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
756 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
757 drive_pingroups[i].name);
758 len = strlen(drive_pingroups[i].name);
759 dbg_pad_field(s, 7 - len);
762 reg = pg_readl(drive_pingroups[i].reg);
764 seq_printf(s, "TEGRA_HSM_ENABLE");
767 seq_printf(s, "TEGRA_HSM_DISABLE");
770 dbg_pad_field(s, 17 - len);
773 seq_printf(s, "TEGRA_SCHMITT_ENABLE");
776 seq_printf(s, "TEGRA_SCHMITT_DISABLE");
779 dbg_pad_field(s, 22 - len);
781 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
782 len = strlen(drive_name(LPMD(reg)));
783 dbg_pad_field(s, 5 - len);
785 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
786 len = DRVDN(reg) < 10 ? 1 : 2;
787 dbg_pad_field(s, 2 - len);
789 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
790 len = DRVUP(reg) < 10 ? 1 : 2;
791 dbg_pad_field(s, 2 - len);
793 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
794 len = strlen(slew_name(SLWR(reg)));
795 dbg_pad_field(s, 7 - len);
797 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
799 seq_printf(s, "},\n");
804 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
806 return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
809 static const struct file_operations debug_drive_fops = {
810 .open = dbg_drive_pinmux_open,
813 .release = single_release,
816 static int __init tegra_pinmux_debuginit(void)
818 (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
819 NULL, NULL, &debug_fops);
820 (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
821 NULL, NULL, &debug_drive_fops);
824 late_initcall(tegra_pinmux_debuginit);