2 * linux/arch/arm/mach-tegra/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
7 * Copyright (C) 2009 Palm
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/jiffies.h>
19 #include <linux/smp.h>
22 #include <asm/cacheflush.h>
23 #include <asm/hardware/gic.h>
24 #include <asm/mach-types.h>
25 #include <asm/smp_scu.h>
28 #include <mach/iomap.h>
29 #include <mach/powergate.h>
34 #include "tegra_cpu_car.h"
36 extern void tegra_secondary_startup(void);
38 static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
40 #define EVP_CPU_RESET_VECTOR \
41 (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
43 void __cpuinit platform_secondary_init(unsigned int cpu)
46 * if any interrupts are already enabled for the primary
47 * core (e.g. timer irq), then they will not have been enabled
50 gic_secondary_init(0);
54 static int tegra20_power_up_cpu(unsigned int cpu)
56 /* Enable the CPU clock. */
57 tegra_enable_cpu_clock(cpu);
59 /* Clear flow controller CSR. */
60 flowctrl_write_cpu_csr(cpu, 0);
65 static int tegra30_power_up_cpu(unsigned int cpu)
68 unsigned long timeout;
70 pwrgateid = tegra_cpu_powergate_id(cpu);
74 /* If this is the first boot, toggle powergates directly. */
75 if (!tegra_powergate_is_powered(pwrgateid)) {
76 ret = tegra_powergate_power_on(pwrgateid);
80 /* Wait for the power to come up. */
81 timeout = jiffies + 10*HZ;
82 while (tegra_powergate_is_powered(pwrgateid)) {
83 if (time_after(jiffies, timeout))
89 /* CPU partition is powered. Enable the CPU clock. */
90 tegra_enable_cpu_clock(cpu);
93 /* Remove I/O clamps. */
94 ret = tegra_powergate_remove_clamping(pwrgateid);
97 /* Clear flow controller CSR. */
98 flowctrl_write_cpu_csr(cpu, 0);
103 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
108 * Force the CPU into reset. The CPU must remain in reset when the
109 * flow controller state is cleared (which will cause the flow
110 * controller to stop driving reset if the CPU has been power-gated
111 * via the flow controller). This will have no effect on first boot
112 * of the CPU since it should already be in reset.
114 tegra_put_cpu_in_reset(cpu);
117 * Unhalt the CPU. If the flow controller was used to power-gate the
118 * CPU this will cause the flow controller to stop driving reset.
119 * The CPU will remain in reset because the clock and reset block
120 * is now driving reset.
122 flowctrl_write_cpu_halt(cpu, 0);
124 switch (tegra_chip_id) {
126 status = tegra20_power_up_cpu(cpu);
129 status = tegra30_power_up_cpu(cpu);
139 /* Take the CPU out of reset. */
140 tegra_cpu_out_of_reset(cpu);
146 * Initialise the CPU possible map early - this describes the CPUs
147 * which may be present or become present in the system.
149 void __init smp_init_cpus(void)
151 unsigned int i, ncores = scu_get_core_count(scu_base);
153 if (ncores > nr_cpu_ids) {
154 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
159 for (i = 0; i < ncores; i++)
160 set_cpu_possible(i, true);
162 set_smp_cross_call(gic_raise_softirq);
165 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
167 tegra_cpu_reset_handler_init();
168 scu_enable(scu_base);