2 * CPU complex suspend & resume functions for Tegra SoCs
4 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/kernel.h>
20 #include <linux/spinlock.h>
22 #include <linux/cpumask.h>
23 #include <linux/delay.h>
24 #include <linux/cpu_pm.h>
25 #include <linux/suspend.h>
26 #include <linux/err.h>
27 #include <linux/clk/tegra.h>
29 #include <asm/smp_plat.h>
30 #include <asm/cacheflush.h>
31 #include <asm/suspend.h>
32 #include <asm/idmap.h>
33 #include <asm/proc-fns.h>
34 #include <asm/tlbflush.h>
44 #ifdef CONFIG_PM_SLEEP
45 static DEFINE_SPINLOCK(tegra_lp2_lock);
46 static u32 iram_save_size;
47 static void *iram_save_addr;
48 struct tegra_lp1_iram tegra_lp1_iram;
49 void (*tegra_tear_down_cpu)(void);
50 void (*tegra_sleep_core_finish)(unsigned long v2p);
51 static int (*tegra_sleep_func)(unsigned long v2p);
53 static void tegra_tear_down_cpu_init(void)
55 switch (tegra_chip_id) {
57 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
58 tegra_tear_down_cpu = tegra20_tear_down_cpu;
62 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
63 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
64 tegra_tear_down_cpu = tegra30_tear_down_cpu;
72 * restores cpu clock setting, clears flow controller
74 * Always called on CPU 0.
76 static void restore_cpu_complex(void)
78 int cpu = smp_processor_id();
83 cpu = cpu_logical_map(cpu);
86 /* Restore the CPU clock settings */
87 tegra_cpu_clock_resume();
89 flowctrl_cpu_suspend_exit(cpu);
95 * saves pll state for use by restart_plls, prepares flow controller for
96 * transition to suspend state
98 * Must always be called on cpu 0.
100 static void suspend_cpu_complex(void)
102 int cpu = smp_processor_id();
107 cpu = cpu_logical_map(cpu);
110 /* Save the CPU clock settings */
111 tegra_cpu_clock_suspend();
113 flowctrl_cpu_suspend_enter(cpu);
116 void tegra_clear_cpu_in_lp2(void)
118 int phy_cpu_id = cpu_logical_map(smp_processor_id());
119 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
121 spin_lock(&tegra_lp2_lock);
123 BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
124 *cpu_in_lp2 &= ~BIT(phy_cpu_id);
126 spin_unlock(&tegra_lp2_lock);
129 bool tegra_set_cpu_in_lp2(void)
131 int phy_cpu_id = cpu_logical_map(smp_processor_id());
132 bool last_cpu = false;
133 cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
134 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
136 spin_lock(&tegra_lp2_lock);
138 BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
139 *cpu_in_lp2 |= BIT(phy_cpu_id);
141 if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
143 else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
144 tegra20_cpu_set_resettable_soon();
146 spin_unlock(&tegra_lp2_lock);
150 int tegra_cpu_do_idle(void)
152 return cpu_do_idle();
155 static int tegra_sleep_cpu(unsigned long v2p)
157 setup_mm_for_reboot();
158 tegra_sleep_cpu_finish(v2p);
160 /* should never here */
166 void tegra_idle_lp2_last(void)
168 tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
170 cpu_cluster_pm_enter();
171 suspend_cpu_complex();
173 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
175 restore_cpu_complex();
176 cpu_cluster_pm_exit();
179 enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
180 enum tegra_suspend_mode mode)
183 * The Tegra devices support suspending to LP1 or lower currently.
185 if (mode > TEGRA_SUSPEND_LP1)
186 return TEGRA_SUSPEND_LP1;
191 static int tegra_sleep_core(unsigned long v2p)
193 setup_mm_for_reboot();
194 tegra_sleep_core_finish(v2p);
196 /* should never here */
203 * tegra_lp1_iram_hook
205 * Hooking the address of LP1 reset vector and SDRAM self-refresh code in
206 * SDRAM. These codes not be copied to IRAM in this fuction. We need to
207 * copy these code to IRAM before LP0/LP1 suspend and restore the content
208 * of IRAM after resume.
210 static bool tegra_lp1_iram_hook(void)
212 switch (tegra_chip_id) {
214 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
215 tegra20_lp1_iram_hook();
219 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
220 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
221 tegra30_lp1_iram_hook();
227 if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
230 iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
231 iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
238 static bool tegra_sleep_core_init(void)
240 switch (tegra_chip_id) {
242 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
243 tegra20_sleep_core_init();
247 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
248 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
249 tegra30_sleep_core_init();
255 if (!tegra_sleep_core_finish)
261 static void tegra_suspend_enter_lp1(void)
265 /* copy the reset vector & SDRAM shutdown code into IRAM */
266 memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA),
268 memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr,
271 *((u32 *)tegra_cpu_lp1_mask) = 1;
274 static void tegra_suspend_exit_lp1(void)
279 memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr,
282 *(u32 *)tegra_cpu_lp1_mask = 0;
285 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
286 [TEGRA_SUSPEND_NONE] = "none",
287 [TEGRA_SUSPEND_LP2] = "LP2",
288 [TEGRA_SUSPEND_LP1] = "LP1",
289 [TEGRA_SUSPEND_LP0] = "LP0",
292 static int tegra_suspend_enter(suspend_state_t state)
294 enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
296 if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
297 mode >= TEGRA_MAX_SUSPEND_MODE))
300 pr_info("Entering suspend state %s\n", lp_state[mode]);
302 tegra_pmc_pm_set(mode);
306 suspend_cpu_complex();
308 case TEGRA_SUSPEND_LP1:
309 tegra_suspend_enter_lp1();
311 case TEGRA_SUSPEND_LP2:
312 tegra_set_cpu_in_lp2();
318 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
321 case TEGRA_SUSPEND_LP1:
322 tegra_suspend_exit_lp1();
324 case TEGRA_SUSPEND_LP2:
325 tegra_clear_cpu_in_lp2();
330 restore_cpu_complex();
337 static const struct platform_suspend_ops tegra_suspend_ops = {
338 .valid = suspend_valid_only_mem,
339 .enter = tegra_suspend_enter,
342 void __init tegra_init_suspend(void)
344 enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
346 if (mode == TEGRA_SUSPEND_NONE)
349 tegra_tear_down_cpu_init();
350 tegra_pmc_suspend_init();
352 if (mode >= TEGRA_SUSPEND_LP1) {
353 if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
354 pr_err("%s: unable to allocate memory for SDRAM"
355 "self-refresh -- LP0/LP1 unavailable\n",
357 tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
358 mode = TEGRA_SUSPEND_LP2;
362 /* set up sleep function for cpu_suspend */
364 case TEGRA_SUSPEND_LP1:
365 tegra_sleep_func = tegra_sleep_core;
367 case TEGRA_SUSPEND_LP2:
368 tegra_sleep_func = tegra_sleep_cpu;
374 suspend_set_ops(&tegra_suspend_ops);